From e0a6590d8ceb7d6c4e35b5b5eb368d9fb800487f Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 27 Apr 2023 22:34:29 +0200 Subject: [PATCH 01/27] ARM: dts: qcom: msm8974-hammerhead: Add vibrator The Nexus 5 has a vibrator connected to the clock output of GP1_CLK which we can use with the clk-pwm driver, then we can use that pwm with pwm-vibrator to get haptics functionality. This patch is based on Brian Masney's previous patch with clk-vibrator. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Caleb Connolly Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230427-hammerhead-vibra-v1-4-e87eeb94da51@z3ntu.xyz --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index ab35f2d644c0..fea8a6be9021 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -41,6 +41,25 @@ key-volume-down { }; }; + clk_pwm: pwm { + compatible = "clk-pwm"; + clocks = <&mmcc CAMSS_GP1_CLK>; + + pinctrl-0 = <&vibrator_pin>; + pinctrl-names = "default"; + + #pwm-cells = <2>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&clk_pwm 0 100000>; + pwm-names = "enable"; + + vcc-supply = <&pm8941_l19>; + enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + }; + vreg_wlan: wlan-regulator { compatible = "regulator-fixed"; @@ -637,6 +656,22 @@ shutdown-pins { function = "gpio"; }; }; + + vibrator_pin: vibrator-state { + core-pins { + pins = "gpio27"; + function = "gp1_clk"; + drive-strength = <6>; + bias-disable; + }; + + enable-pins { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; }; &usb { From 311bbc884b2edcf584b67d331be85ce43b27586f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 10 Apr 2023 19:52:32 +0200 Subject: [PATCH 02/27] ARM: dts: qcom: msm8974: do not use underscore in node name (again) Align RPM requests node with DT schema by using hyphen instead of underscore. Fixes: f300826d27be ("ARM: dts: qcom-msm8974: Sort and clean up nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230410175232.22317-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8208012684d4..38d3ee152dcb 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -300,7 +300,7 @@ rpm { qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests: rpm_requests { + rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8974"; qcom,smd-channels = "rpm_requests"; From a0f19091d4f5bbe97485592257b88007eb5b1998 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 14 Apr 2023 15:57:47 +0200 Subject: [PATCH 03/27] ARM: dts: qcom: msm8660: Fix regulator node names commit 04715461abf7 altered the node names in a DTSI file used by qcom-apq8060-dragonboard.dts breaking the board. Align the node names in the DTS file and the board boots again. Cc: stable@vger.kernel.org Fixes: 85055a1eecc1 ("ARM: dts: qcom-msm8660: align RPM regulators node name with bindings") Signed-off-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230414135747.34994-1-linus.walleij@linaro.org --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 8e4b61e4d4b1..e8fe321f3d89 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -451,7 +451,7 @@ &rpm { * PM8901 supplies "preliminary regulators" whatever * that means */ - pm8901-regulators { + regulators-0 { vdd_l0-supply = <&pm8901_s4>; vdd_l1-supply = <&vph>; vdd_l2-supply = <&vph>; @@ -537,7 +537,7 @@ lvs0 { }; - pm8058-regulators { + regulators-1 { vdd_l0_l1_lvs-supply = <&pm8058_s3>; vdd_l2_l11_l12-supply = <&vph>; vdd_l3_l4_l5-supply = <&vph>; From 392a1aab14542a9e393f89c985679cf3ac161156 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:53:18 +0200 Subject: [PATCH 04/27] ARM: dts: qcom: msm8974: drop unit addresses from USB phys The ulpi node does not allow children to have unit address: Warning (unit_address_vs_reg): /soc/usb@f9a55000/ulpi/phy@a: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420065318.23503-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 38d3ee152dcb..9f0a6d7a3867 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -675,7 +675,7 @@ usb: usb@f9a55000 { #reset-cells = <1>; ulpi { - usb_hs1_phy: phy@a { + usb_hs1_phy: phy-0 { compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; #phy-cells = <0>; @@ -686,7 +686,7 @@ usb_hs1_phy: phy@a { status = "disabled"; }; - usb_hs2_phy: phy@b { + usb_hs2_phy: phy-1 { compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; #phy-cells = <0>; From edcbdd57de499305e2a3737d4a73fe387f71d84c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:28:11 +0200 Subject: [PATCH 05/27] ARM: dts: qcom: ipq4019: fix broken NAND controller properties override After renaming NAND controller node name from "qpic-nand" to "nand-controller", the board DTS/DTSI also have to be updated: Warning (unit_address_vs_reg): /soc/qpic-nand@79b0000: node has a unit name, but no reg or ranges property Cc: Fixes: 9e1e00f18afc ("ARM: dts: qcom: Fix node name for NAND controller node") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420072811.36947-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 8 ++++---- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 10 +++++----- arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 12 ++++++------ 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts index 79b0c6318e52..0993f840d1fc 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts @@ -11,9 +11,9 @@ soc { dma-controller@7984000 { status = "okay"; }; - - qpic-nand@79b0000 { - status = "okay"; - }; }; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi index a63b3778636d..468ebc40d2ad 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -102,10 +102,10 @@ pci@40000000 { status = "okay"; perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; - - qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - }; }; }; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi index 0107f552f520..7ef635997efa 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi @@ -65,11 +65,11 @@ i2c@78b7000 { /* BLSP1 QUP2 */ dma-controller@7984000 { status = "okay"; }; - - qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "okay"; - }; }; }; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; +}; From e054c9c38f439613a2c4dd81db46909ba532b1b9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:44 +0200 Subject: [PATCH 06/27] ARM: dts: qcom: ipq4019: correct syscon unit-address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/syscon@1fcb000: simple-bus unit address format error, expected "1fc0000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 342c3d14001e..72d82a9a6cc5 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -515,7 +515,7 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; - tcsr: syscon@1fcb000 { + tcsr: syscon@1fc0000 { compatible = "qcom,sdx55-tcsr", "syscon"; reg = <0x01fc0000 0x1000>; }; From fd9936dfe45765bd74c8100b8e228675482cd3ca Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:45 +0200 Subject: [PATCH 07/27] ARM: dts: qcom: sdx55: correct rsc unit-address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/rsc@17840000: simple-bus unit address format error, expected "17830000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 72d82a9a6cc5..06c2646dd673 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -792,7 +792,7 @@ frame@17829000 { }; }; - apps_rsc: rsc@17840000 { + apps_rsc: rsc@17830000 { compatible = "qcom,rpmh-rsc"; reg = <0x17830000 0x10000>, <0x17840000 0x10000>; reg-names = "drv-0", "drv-1"; From dcbd24008bfa9b2fc63ea34092b036f3f76b35db Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:46 +0200 Subject: [PATCH 08/27] ARM: dts: qcom: msm8974: correct pronto unit-address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/remoteproc@fb21b000: simple-bus unit address format error, expected "fb204000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-3-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 9f0a6d7a3867..b30d59844136 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -706,7 +706,7 @@ rng@f9bff000 { clock-names = "core"; }; - pronto: remoteproc@fb21b000 { + pronto: remoteproc@fb204000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; From 1c7d01ba0f36ad7f7c5f6f7fd7b69375d97350e7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:47 +0200 Subject: [PATCH 09/27] ARM: dts: qcom: ipq8064: drop leading 0 from unit-address Unit-address should not start with 0: Warning (simple_bus_reg): /soc/syscon@03000000: simple-bus unit address format error, expected "3000000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-4-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index af6764770fd1..5a42d920e4f9 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -606,7 +606,7 @@ saw1: regulator@2099000 { regulator; }; - nss_common: syscon@03000000 { + nss_common: syscon@3000000 { compatible = "syscon"; reg = <0x03000000 0x0000FFFF>; }; From 24643b229c3d93cc4c7368e00dad89d300dd5e8a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:48 +0200 Subject: [PATCH 10/27] ARM: dts: qcom: ipq8064: drop invalid GCC thermal-sensor unit-address GCC comes with syscon compatible so the thermal-sensor child node should not have unit-address (bindings also do not expect it): Warning (unit_address_vs_reg): /soc/clock-controller@900000/thermal-sensor@900000: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-5-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 5a42d920e4f9..2ca20a2765e7 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -520,7 +520,7 @@ gcc: clock-controller@900000 { #reset-cells = <1>; #power-domain-cells = <1>; - tsens: thermal-sensor@900000 { + tsens: thermal-sensor { compatible = "qcom,ipq8064-tsens"; nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; From 51500b3aac5d2fc102d607c3517f7a1ee2f29dca Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:49 +0200 Subject: [PATCH 11/27] ARM: dts: qcom: ipq8064: correct LED node names GPIO LEDs is not a bus, so drop unit-address and also start suffix numbering from 0: Warning (unit_address_vs_reg): /soc/leds/led@7: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-6-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 2 +- arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts index 4d509876294b..104eb729c2d6 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -323,7 +323,7 @@ leds { pinctrl-0 = <&leds_pins>; pinctrl-names = "default"; - led@7 { + led-0 { label = "rb3011:green:user"; color = ; gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index 411c8d63c38e..c5abe7151f14 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -92,34 +92,34 @@ leds { pinctrl-0 = <&leds_pins>; pinctrl-names = "default"; - led@7 { + led-0 { label = "led_usb1"; gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "usbdev"; default-state = "off"; }; - led@8 { + led-1 { label = "led_usb3"; gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "usbdev"; default-state = "off"; }; - led@9 { + led-2 { label = "status_led_fail"; function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@26 { + led-3 { label = "sata_led"; gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@53 { + led-4 { label = "status_led_pass"; function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; From 8b96065dd257f74ed03645978d2e076894d864b2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:50 +0200 Subject: [PATCH 12/27] ARM: dts: qcom: ipq8064: align USB node names with bindings Bindings expect USB controller node names to be named "usb". Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-7-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 2ca20a2765e7..5ef5026fb7bc 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -611,7 +611,7 @@ nss_common: syscon@3000000 { reg = <0x03000000 0x0000FFFF>; }; - usb3_0: usb3@100f8800 { + usb3_0: usb@100f8800 { compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -626,7 +626,7 @@ usb3_0: usb3@100f8800 { status = "disabled"; - dwc3_0: dwc3@10000000 { + dwc3_0: usb@10000000 { compatible = "snps,dwc3"; reg = <0x10000000 0xcd00>; interrupts = ; @@ -657,7 +657,7 @@ ss_phy_0: phy@100f8830 { status = "disabled"; }; - usb3_1: usb3@110f8800 { + usb3_1: usb@110f8800 { compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -672,7 +672,7 @@ usb3_1: usb3@110f8800 { status = "disabled"; - dwc3_1: dwc3@11000000 { + dwc3_1: usb@11000000 { compatible = "snps,dwc3"; reg = <0x11000000 0xcd00>; interrupts = ; From 600efc01c98d3369d1fc5caee531159c43bc3939 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:51 +0200 Subject: [PATCH 13/27] ARM: dts: qcom: apq8060-dragonboard: move regulators out of simple-bus Regulators is not a bus, so drop incomplete simple-bus usage to fix dtbs W=1 warnings: Warning (simple_bus_reg): /regulators/regulator-fixed: missing or empty reg/ranges property Warning (simple_bus_reg): /regulators/xc622a331mrg: missing or empty reg/ranges property Warning (simple_bus_reg): /regulators/nds332p: missing or empty reg/ranges property Warning (simple_bus_reg): /regulators/txb0104rgyr: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-8-krzysztof.kozlowski@linaro.org --- .../arm/boot/dts/qcom-apq8060-dragonboard.dts | 78 +++++++++---------- 1 file changed, 37 insertions(+), 41 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index e8fe321f3d89..db4c791b2e2f 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -18,50 +18,46 @@ chosen { stdout-path = "serial0:115200n8"; }; - regulators { - compatible = "simple-bus"; + /* Main power of the board: 3.7V */ + vph: regulator-fixed { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-name = "VPH"; + regulator-type = "voltage"; + regulator-always-on; + regulator-boot-on; + }; - /* Main power of the board: 3.7V */ - vph: regulator-fixed { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-always-on; - regulator-boot-on; - }; + /* GPIO controlled ethernet power regulator */ + dragon_veth: xc622a331mrg { + compatible = "regulator-fixed"; + regulator-name = "XC6222A331MR-G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vph>; + gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_veth_gpios>; + regulator-always-on; + }; - /* GPIO controlled ethernet power regulator */ - dragon_veth: xc622a331mrg { - compatible = "regulator-fixed"; - regulator-name = "XC6222A331MR-G"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vph>; - gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_veth_gpios>; - regulator-always-on; - }; + /* VDDvario fixed regulator */ + dragon_vario: nds332p { + compatible = "regulator-fixed"; + regulator-name = "NDS332P"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8058_s3>; + }; - /* VDDvario fixed regulator */ - dragon_vario: nds332p { - compatible = "regulator-fixed"; - regulator-name = "NDS332P"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&pm8058_s3>; - }; - - /* This is a levelshifter for SDCC5 */ - dragon_vio_txb: txb0104rgyr { - compatible = "regulator-fixed"; - regulator-name = "Dragon SDCC levelshifter"; - vin-supply = <&pm8058_l14>; - regulator-always-on; - }; + /* This is a levelshifter for SDCC5 */ + dragon_vio_txb: txb0104rgyr { + compatible = "regulator-fixed"; + regulator-name = "Dragon SDCC levelshifter"; + vin-supply = <&pm8058_l14>; + regulator-always-on; }; /* From 26fe8ec355328c35e2768cb9758341c0256dc953 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:52 +0200 Subject: [PATCH 14/27] ARM: dts: qcom: msm8960-cdp: move regulator out of simple-bus Regulators is not a bus, so drop incomplete simple-bus usage to fix dtbs W=1 warning: Warning (simple_bus_reg): /regulators/gpio-regulator: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-9-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8960-cdp.dts | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 8fa2befa629a..6c1bc3818883 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -15,16 +15,12 @@ chosen { stdout-path = "serial0:115200n8"; }; - regulators { - compatible = "simple-bus"; - - ext_l2: gpio-regulator { - compatible = "regulator-fixed"; - regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; - startup-delay-us = <10000>; - enable-active-high; - }; + ext_l2: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "ext_l2"; + gpio = <&msmgpio 91 0>; + startup-delay-us = <10000>; + enable-active-high; }; }; From 05e916f1db2fff88f316b6f94929b4b3b8414498 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:53 +0200 Subject: [PATCH 15/27] ARM: dts: qcom: apq8084: correct thermal sensor unit-address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/thermal-sensor@fc4a8000: simple-bus unit address format error, expected "fc4a9000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-10-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8084.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index b653ea40c441..207124d68128 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -506,7 +506,7 @@ tsens_s4_p2_backup: s4-p2_backup@44e { }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ From d2f1bd8f0b91ce77951d983a094c157b2efd789c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Apr 2023 21:54:37 +0200 Subject: [PATCH 16/27] ARM: dts: qcom: msm8974: align WCNSS Bluetooth node name with bindings Bindings expect WCNSS Bluetooth child to be named "bluetooth": remoteproc@fb204000: smd-edge:wcnss: 'bt' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230421195437.31513-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index b30d59844136..7dcbe0810e34 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -745,7 +745,7 @@ wcnss { qcom,mmio = <&pronto>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; From 57b60d03d5a682d366a4850b1f69c53fc13beb22 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 23:17:50 +0530 Subject: [PATCH 17/27] ARM: dts: qcom: sdx65: Add support for PCIe PHY Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684432073-28490-3-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 525dd8a1f664..2fe61c296e39 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -295,6 +295,37 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_phy: phy@1c06000 { + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; + reg = <0x01c06000 0x2000>; + + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; From 9c0bb38414a45a03d1100f033ab6f96bedffe43a Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 23:17:51 +0530 Subject: [PATCH 18/27] ARM: dts: qcom: sdx65: Add support for PCIe EP Add support for PCIe Endpoint controller on the Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684432073-28490-4-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 2fe61c296e39..1a3583029a64 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -295,6 +296,56 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie_phy: phy@1c06000 { compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; reg = <0x01c06000 0x2000>; @@ -332,6 +383,11 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + tcsr: syscon@1fcb000 { + compatible = "qcom,sdx65-tcsr", "syscon"; + reg = <0x01fc0000 0x1000>; + }; + ipa: ipa@3f40000 { compatible = "qcom,sdx65-ipa"; From 2e69f6882b69ea98e785469481bf9a4d111e3b96 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 23:17:52 +0530 Subject: [PATCH 19/27] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY Enable PCIe PHY on SDX65 MTP for PCIe EP. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684432073-28490-5-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 57bc3b03d3aa..29ccb158f8fc 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -250,6 +250,13 @@ &ipa { status = "okay"; }; +&pcie_phy { + vdda-phy-supply = <&vreg_l1b_1p2>; + vdda-pll-supply = <&vreg_l4b_0p88>; + + status = "okay"; +}; + &qpic_bam { status = "okay"; }; From fd817375091b35c4368244a9872158eb719534b0 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 23:17:53 +0530 Subject: [PATCH 20/27] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP Enable PCIe Endpoint controller on the SDX65 MTP board based on Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684432073-28490-6-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 29ccb158f8fc..02d8d6e241ae 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -250,6 +250,18 @@ &ipa { status = "okay"; }; +&pcie_ep { + pinctrl-0 = <&pcie_ep_clkreq_default + &pcie_ep_perst_default + &pcie_ep_wake_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l1b_1p2>; vdda-pll-supply = <&vreg_l4b_0p88>; @@ -281,6 +293,29 @@ &remoteproc_mpss { status = "okay"; }; +&tlmm { + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie_ep_perst_default: pcie-ep-perst-default-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + pcie_ep_wake_default: pcie-ep-wake-default-state { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &usb { status = "okay"; }; From 38cd0f2d86f1dbfef2bef4e2b0a8b19d32a82760 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sat, 20 May 2023 15:19:31 +0300 Subject: [PATCH 21/27] ARM: dts: qcom: msm8226: Add PMU node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable perf events on MSM8226 devices by adding the PMU node. Signed-off-by: Matti Lehtimäki Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230520121933.15533-3-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 42acb9ddb8cc..185a8fff62be 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -47,6 +47,12 @@ scm { }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; From a22a576af30d4366ff13662c8b57c951374c7674 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sat, 20 May 2023 15:19:32 +0300 Subject: [PATCH 22/27] ARM: dts: qcom: msm8226: Add rpm-stats device node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device node for the rpm-stats pseudo device. Signed-off-by: Matti Lehtimäki Reviewed-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230520121933.15533-4-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 185a8fff62be..dc706d5b185c 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -598,6 +598,11 @@ frame@f9028000 { }; }; + sram@fc190000 { + compatible = "qcom,msm8226-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + rpm_msg_ram: sram@fc428000 { compatible = "qcom,rpm-msg-ram"; reg = <0xfc428000 0x4000>; From 9cf9832d4f5f7659159a036ccae2e10f6eeadf5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sat, 20 May 2023 15:19:33 +0300 Subject: [PATCH 23/27] ARM: dts: qcom: msm8226: Add IMEM node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This enables userspace to signal the bootloader to go into the bootloader or recovery mode. The magic values can be found in both the downstream kernel and the LK kernel (bootloader). Signed-off-by: Matti Lehtimäki Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230520121933.15533-5-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index dc706d5b185c..a3a9162e9c28 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -647,6 +647,20 @@ smd-edge { label = "lpass"; }; }; + + sram@fe805000 { + compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; + reg = <0xfe805000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-bootloader = <0x77665500>; + mode-normal = <0x77665501>; + mode-recovery = <0x77665502>; + }; + }; }; timer { From b41fb001bebff28dd05a7c74e728ce7f024856ac Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 30 Apr 2023 20:20:57 +0200 Subject: [PATCH 24/27] ARM: dts: qcom: apq8026-huawei-sturgeon: Add vibrator The watch has a DRV2605 for haptics. Add a node for it based on the values found in the downstream board file. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230430-drv260x-improvements-v1-5-1fb28b4cc698@z3ntu.xyz --- .../boot/dts/qcom-apq8026-huawei-sturgeon.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts b/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts index d64096028ab1..eb73b992a696 100644 --- a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts +++ b/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts @@ -7,6 +7,7 @@ #include "qcom-msm8226.dtsi" #include "qcom-pm8226.dtsi" +#include /delete-node/ &adsp_region; @@ -68,6 +69,26 @@ &adsp { status = "okay"; }; +&blsp1_i2c2 { + clock-frequency = <384000>; + + status = "okay"; + + vibrator@5a { + compatible = "ti,drv2605"; + reg = <0x5a>; + enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + + mode = ; + library-sel = ; + vib-rated-mv = <2765>; + vib-overdrive-mv = <3525>; + + pinctrl-0 = <&vibrator_default_state>; + pinctrl-names = "default"; + }; +}; + &blsp1_i2c5 { clock-frequency = <384000>; @@ -347,6 +368,13 @@ reset-pins { }; }; + vibrator_default_state: vibrator-default-state { + pins = "gpio59", "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + wlan_hostwake_default_state: wlan-hostwake-default-state { pins = "gpio66"; function = "gpio"; From e60c230588d88036f974cec7e93361e2c4f62226 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 7 May 2023 22:07:33 +0300 Subject: [PATCH 25/27] ARM: dts: qcom: apq8074-dragonboard: Set DMA as remotely controlled Add the qcom,controlled-remotely property for the blsp2_bam controller node. This board requires this, otherwise the board stalls during the boot for some reason (most probably because TZ mishandles the protection error and keeps on looping somewhere inside). Fixes: 62bc81792223 dts: msm8974: Add blsp2_bam dma node Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507190735.2333145-3-dmitry.baryshkov@linaro.org --- arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 1345df7cbd00..6b047c679370 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -23,6 +23,10 @@ &blsp1_uart2 { status = "okay"; }; +&blsp2_dma { + qcom,controlled-remotely; +}; + &blsp2_i2c5 { status = "okay"; clock-frequency = <200000>; From 1ca793c3714a754488c782eb0d68b279d811b977 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 7 May 2023 22:07:34 +0300 Subject: [PATCH 26/27] ARM: dts: qcom: apq8074-dragonboard: enable adsp and MSS Enable ADSP and Modem DSPs on APQ8074 dragonboard. The MSS region differs from the one defined in the msm8974, so it overriden locally. The modem is specified use mba.mbn instead of mbn.b00 (for the sake of similarity with other platforms). This requires a patch for remoteproc to be applied [1]. [1] https://lore.kernel.org/all/20230507172041.2320279-1-dmitry.baryshkov@linaro.org/ Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507190735.2333145-4-dmitry.baryshkov@linaro.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 6b047c679370..c893afc00eb4 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -4,6 +4,8 @@ #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" +/delete-node/ &mpss_region; + / { model = "Qualcomm APQ8074 Dragonboard"; compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; @@ -17,6 +19,13 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + reserved-memory { + mpss_region: mpss@ac00000 { + reg = <0x0ac00000 0x2500000>; + no-map; + }; + }; }; &blsp1_uart2 { @@ -39,6 +48,25 @@ eeprom: eeprom@52 { }; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; + + firmware-name = "qcom/apq8074/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + + firmware-name = "qcom/apq8074/mba.mbn", "qcom/apq8074/modem.mbn"; + + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8841-regulators"; From 925bac3caa46c5790d21ee236869b017090aad2d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 7 May 2023 22:07:35 +0300 Subject: [PATCH 27/27] ARM: dts: qcom: apq8074-dragonboard: enable DSI panel Enable MDSS, GPU and DSI panel output on the APQ8074 dragonboard. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507190735.2333145-5-dmitry.baryshkov@linaro.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index c893afc00eb4..72f7e09a5bbf 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -48,6 +48,57 @@ eeprom: eeprom@52 { }; }; +&dsi0 { + vdda-supply = <&pm8941_l2>; + vdd-supply = <&pm8941_l22>; + vddio-supply = <&pm8941_l12>; + + status = "okay"; + + panel: panel@0 { + compatible = "sharp,ls043t1le01-qhd"; + reg = <0>; + + avdd-supply = <&pm8941_l22>; + backlight = <&pm8941_wled>; + reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + + vddio-supply = <&pm8941_l12>; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&pm8941_wled { + qcom,cs-out; + qcom,switching-freq = <3200>; + qcom,ovp = <32>; + qcom,num-strings = <1>; + + status = "okay"; +}; + &remoteproc_adsp { cx-supply = <&pm8841_s2>;