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arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes

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Referred in the documentation as the Software Timer Watchdog (SWT),
the s32g3 has 12 watchdogs. The number of watchdogs is designed to
allow dedicating one watchdog per Cortex-M7/A53 present on the SoC.

Add the SWT nodes in the device tree.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Cc: Thomas Fossati <thomas.fossati@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Daniel Lezcano 2025-07-31 16:01:40 +02:00 committed by Shawn Guo
parent 88a1e2d865
commit 6db84f0427
1 changed files with 96 additions and 0 deletions
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96
arch/arm64/boot/dts/freescale/s32g3.dtsi
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@ -383,6 +383,38 @@ usdhc0-200mhz-grp4 {
};
};
swt0: watchdog@40100000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40100000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt1: watchdog@40104000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40104000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt2: watchdog@40108000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40108000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt3: watchdog@4010c000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x4010c000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm0: timer@4011c000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x4011c000 0x3000>;
@ -578,6 +610,38 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
swt4: watchdog@40200000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt5: watchdog@40204000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40204000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt6: watchdog@40208000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40208000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt7: watchdog@4020C000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x4020C000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm4: timer@4021c000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x4021c000 0x3000>;
@ -733,6 +797,38 @@ usdhc0: mmc@402f0000 {
status = "disabled";
};
swt8: watchdog@40500000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <40500000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt9: watchdog@40504000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40504000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt10: watchdog@40508000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40508000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt11: watchdog@4050c000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x4050c000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm8: timer@40520000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40520000 0x3000>;