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drm/amd/pm: Add message control for SMUv11

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Initialize smu message control in SMUv11 SOCs.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2026-01-06 13:29:25 +05:30 committed by Alex Deucher
parent 4f379370a4
commit 6d74c9ff6a
7 changed files with 24 additions and 0 deletions
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2
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
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@ -283,6 +283,8 @@ int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
void smu_v11_0_init_msg_ctl(struct smu_context *smu,
const struct cmn2asic_msg_mapping *message_map);
#endif
#endif

1
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
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@ -1966,4 +1966,5 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
smu->pwr_src_map = arcturus_pwr_src_map;
smu->workload_map = arcturus_workload_map;
smu_v11_0_set_smu_mailbox_registers(smu);
smu_v11_0_init_msg_ctl(smu, arcturus_message_map);
}

1
drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
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@ -605,4 +605,5 @@ void cyan_skillfish_set_ppt_funcs(struct smu_context *smu)
smu->table_map = cyan_skillfish_table_map;
smu->is_apu = true;
smu_v11_0_set_smu_mailbox_registers(smu);
smu_v11_0_init_msg_ctl(smu, cyan_skillfish_message_map);
}

1
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
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@ -3376,4 +3376,5 @@ void navi10_set_ppt_funcs(struct smu_context *smu)
smu->pwr_src_map = navi10_pwr_src_map;
smu->workload_map = navi10_workload_map;
smu_v11_0_set_smu_mailbox_registers(smu);
smu_v11_0_init_msg_ctl(smu, navi10_message_map);
}

1
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
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@ -3189,4 +3189,5 @@ void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
smu->pwr_src_map = sienna_cichlid_pwr_src_map;
smu->workload_map = sienna_cichlid_workload_map;
smu_v11_0_set_smu_mailbox_registers(smu);
smu_v11_0_init_msg_ctl(smu, sienna_cichlid_message_map);
}

17
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
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@ -2176,3 +2176,20 @@ void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
}
void smu_v11_0_init_msg_ctl(struct smu_context *smu,
const struct cmn2asic_msg_mapping *message_map)
{
struct amdgpu_device *adev = smu->adev;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
ctl->smu = smu;
mutex_init(&ctl->lock);
ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
ctl->config.num_arg_regs = 1;
ctl->ops = &smu_msg_v1_ops;
ctl->default_timeout = adev->usec_timeout * 20;
ctl->message_map = message_map;
}

1
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
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@ -2569,4 +2569,5 @@ void vangogh_set_ppt_funcs(struct smu_context *smu)
smu->workload_map = vangogh_workload_map;
smu->is_apu = true;
smu_v11_0_set_smu_mailbox_registers(smu);
smu_v11_0_init_msg_ctl(smu, vangogh_message_map);
}