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arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC

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As per C3 datasheet add missing cache information to the Amlogic C3 SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-9-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Anand Moon 2025-08-25 12:21:48 +05:30 committed by Neil Armstrong
parent 57273dc063
commit 6d4ab38a0a
1 changed files with 23 additions and 0 deletions
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23
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
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@ -23,6 +23,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@ -30,6 +37,22 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x7d000>; /* L2. 512 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};