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pinctrl: samsung: Add Exynos9810 SoC specific data
Add Samsung Exynos9810 SoC specific data to enable pinctrl support for platforms based on Exynos9810. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241026-exynos9810-v3-8-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Markuss Broks
Krzysztof Kozlowski
parent
e830431e0a
commit
6d2dbd4cec
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@ -767,6 +767,160 @@ const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = {
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.num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl),
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};
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/* pin banks of exynos9810 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = {
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EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"),
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EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00),
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EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04),
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EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08),
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EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c),
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EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"),
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EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10),
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};
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/* pin banks of exynos9810 pin-controller 1 (AUD) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04),
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EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08),
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};
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/* pin banks of exynos9810 pin-controller 2 (CHUB) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04),
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};
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/* pin banks of exynos9810 pin-controller 3 (CMGP) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = {
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EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
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EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
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EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
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EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C),
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EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C),
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EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20),
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EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24),
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EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28),
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EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C),
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EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30),
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EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34),
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EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38),
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EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C),
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EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40),
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EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44),
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EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48),
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EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C),
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};
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/* pin banks of exynos9810 pin-controller 4 (FSYS0) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00),
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};
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/* pin banks of exynos9810 pin-controller 5 (FSYS1) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00),
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EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04),
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};
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/* pin banks of exynos9810 pin-controller 6 (PERIC0) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04),
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EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08),
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EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C),
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EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
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EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
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EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18),
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};
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/* pin banks of exynos9810 pin-controller 7 (PERIC1) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00),
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EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04),
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EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08),
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EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C),
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EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10),
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EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
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EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18),
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};
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/* pin banks of exynos9810 pin-controller 8 (VTS) */
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static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00),
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};
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static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = {
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{
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/* pin-controller instance 0 ALIVE data */
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.pin_banks = exynos9810_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks0),
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.eint_wkup_init = exynos_eint_wkup_init,
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 1 AUD data */
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.pin_banks = exynos9810_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks1),
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}, {
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/* pin-controller instance 2 CHUB data */
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.pin_banks = exynos9810_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks2),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 3 CMGP data */
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.pin_banks = exynos9810_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks3),
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.eint_wkup_init = exynos_eint_wkup_init,
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 4 FSYS0 data */
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.pin_banks = exynos9810_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks4),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 5 FSYS1 data */
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.pin_banks = exynos9810_pin_banks5,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks5),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 6 PERIC0 data */
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.pin_banks = exynos9810_pin_banks6,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks6),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 7 PERIC1 data */
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.pin_banks = exynos9810_pin_banks7,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks7),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 8 VTS data */
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.pin_banks = exynos9810_pin_banks8,
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.nr_banks = ARRAY_SIZE(exynos9810_pin_banks8),
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},
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};
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const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = {
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.ctrl = exynos9810_pin_ctrl,
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.num_ctrl = ARRAY_SIZE(exynos9810_pin_ctrl),
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};
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/* pin banks of exynosautov9 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = {
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EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
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@ -1479,6 +1479,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = &exynos850_of_data },
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{ .compatible = "samsung,exynos8895-pinctrl",
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.data = &exynos8895_of_data },
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{ .compatible = "samsung,exynos9810-pinctrl",
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.data = &exynos9810_of_data },
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{ .compatible = "samsung,exynos990-pinctrl",
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.data = &exynos990_of_data },
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{ .compatible = "samsung,exynosautov9-pinctrl",
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@ -385,6 +385,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos9810_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos990_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
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