From 6d09a56b49380d996f225fcbcb96a64512bbe8e8 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Sat, 21 Feb 2026 16:22:30 +0100 Subject: [PATCH] drm/xe/pf: Don't use LMTT page size if no LMTT While today all our DGFX platforms have LMTT, we already started preparation to do not rely on this assumption. Add check for the LMTT presence and return default page size as VRAM/LMEM alignment if there is no LMTT. Signed-off-by: Michal Wajdeczko Reviewed-by: Matthew Brost Link: https://patch.msgid.link/20260221152230.7071-4-michal.wajdeczko@intel.com --- drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c index 53f03e7075d2..b867203b4997 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c @@ -1451,7 +1451,8 @@ int xe_gt_sriov_pf_config_set_fair_dbs(struct xe_gt *gt, unsigned int vfid, static u64 pf_get_lmem_alignment(struct xe_gt *gt) { - return xe_lmtt_page_size(>->tile->sriov.pf.lmtt); + return xe_device_has_lmtt(gt_to_xe(gt)) ? + xe_lmtt_page_size(>_to_tile(gt)->sriov.pf.lmtt) : XE_PAGE_SIZE; } static u64 pf_get_min_spare_lmem(struct xe_gt *gt)