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dt-bindings: pci: layerscape-pci: Add a optional property big-endian

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This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.

Link: https://lore.kernel.org/r/20220311234938.8706-2-leoyang.li@nxp.com
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Hou Zhiqiang 2022-03-11 17:49:35 -06:00 committed by Lorenzo Pieralisi
parent 3123109284
commit 6c389328c9
1 changed files with 4 additions and 0 deletions
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4
Documentation/devicetree/bindings/pci/layerscape-pci.txt
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@ -40,6 +40,10 @@ Required properties:
of the data transferred from/to the IP block. This can avoid the software
cache flush/invalid actions, and improve the performance significantly.
Optional properties:
- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
this property.
Example:
pcie@3400000 {