From 7ed7d1ed852d8f4c4dee7a4d4f7807ad59c7915d Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Mon, 16 Dec 2024 09:54:10 +0100 Subject: [PATCH 01/71] arm64: dts: imx8mm-phyboard-polis-peb-av-10: Set lvds-vod-swing Set custom differential output voltage for LVDS, to fulfill requirements of the connected display. LVDS differential voltage for data-lanes and clock output has to be between 200 mV and 600 mV. Driver sets 200 Ohm near-end termination by default. Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso index 840f83293452..e5ca5a664b61 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso @@ -186,6 +186,8 @@ port@2 { reg = <2>; bridge_out: endpoint { remote-endpoint = <&panel_in>; + ti,lvds-vod-swing-clock-microvolt = <200000 600000>; + ti,lvds-vod-swing-data-microvolt = <200000 600000>; }; }; }; From 0005617c5e2fc04b2dc94cf849e5556b952571ca Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 26 Feb 2025 10:42:55 +0800 Subject: [PATCH 02/71] arm64: dts: imx8mq: Add linux,pci-domain into pcie-ep node Add linux,pci-domain into pcie-ep node of i.MX8MQ. Signed-off-by: Richard Zhu Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d51de8d899b2..387b3e227cfc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1828,6 +1828,7 @@ pcie1_ep: pcie-ep@33c00000 { interrupts = ; interrupt-names = "dma"; fsl,max-link-speed = <2>; + linux,pci-domain = <1>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_PHY>, From 9f0928ea7258172514ac3d6ebdb9162970ccc965 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Tue, 11 Mar 2025 12:32:55 -0400 Subject: [PATCH 03/71] arm64: dts: imx: add imx95 dts for sof Add imx95 DTS for SOF usage. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Iuliana Prodan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx95-19x19-evk-sof.dts | 84 +++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b6d3fe26d621..dba0c9ac10cf 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -303,6 +303,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts new file mode 100644 index 000000000000..808a9fe3ebb2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include "imx95-19x19-evk.dts" + +/ { + sof_cpu: cm7-cpu@80000000 { + compatible = "fsl,imx95-cm7-sof"; + reg = <0x0 0x80000000 0x0 0x6100000>; + reg-names = "sram"; + memory-region = <&adma_res>; + memory-region-names = "dma"; + mboxes = <&mu7 2 0>, <&mu7 2 1>, <&mu7 3 0>, <&mu7 3 1>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + + sai3_cpu: port { + sai3_cpu_ep: endpoint { + remote-endpoint = <&wm8962_ep>; + }; + }; + }; + + reserved-memory { + adma_res: memory@86100000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x86100000 0x0 0x100000>; + no-map; + }; + }; + + sof-sound { + compatible = "audio-graph-card2"; + links = <&sai3_cpu>; + label = "audio"; + hp-det-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + widgets = "Headphone", "Headphones", + "Microphone", "Headset Mic"; + routing = "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic", + "IN1R", "Headset Mic"; + }; + + sound-wm8962 { + status = "disabled"; + }; + +}; + +&edma2 { + /* channels 30 and 31 reserved for FW usage */ + dma-channel-mask = <0xc0000000>, <0x0>; +}; + +&sai3 { + status = "disabled"; +}; + +&wm8962 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, + <12288000>; + + port { + wm8962_ep: endpoint { + bitclock-master; + frame-master; + remote-endpoint = <&sai3_cpu_ep>; + }; + }; +}; From adcf4a5216ccca3b0ffa3d64203780d09afc00af Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Thu, 20 Mar 2025 14:09:51 +0200 Subject: [PATCH 04/71] arm64: dts: imx8mp: Use resets property Add resets property to dsp node in order to be able to control the dsp run/stall bit from audio block control. Reviewed-by: Peng Fan Reviewed-by: Frank Li Signed-off-by: Daniel Baluta Reviewed-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ce6793b2d57e..3b725fe442d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2422,6 +2423,8 @@ dsp: dsp@3b6e8000 { mboxes = <&mu2 2 0>, <&mu2 2 1>, <&mu2 3 0>, <&mu2 3 1>; memory-region = <&dsp_reserved>; + resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; + reset-names = "runstall"; status = "disabled"; }; }; From caa2ee72e0da7b969deb52bfd04729009c59f03c Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Thu, 20 Mar 2025 14:09:52 +0200 Subject: [PATCH 05/71] arm64: dts: imx8mp: Add mu2 root clock Enable MU2 node and add mu2 root clock. MU2 is used to communicate with DSP core. Reviewed-by: Iuliana Prodan Reviewed-by: Peng Fan Signed-off-by: Daniel Baluta Reviewed-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3b725fe442d0..fc0d244cfd1e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1253,6 +1253,7 @@ mu2: mailbox@30e60000 { reg = <0x30e60000 0x10000>; interrupts = ; #mbox-cells = <2>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; status = "disabled"; }; From f048f2126fcccaff2c534a3c08a109875cff7b0e Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Thu, 20 Mar 2025 14:09:53 +0200 Subject: [PATCH 06/71] arm64: dts: imx8mp: Configure dsp node for rproc usage DSP can be used with various frameworks (e.g audio firmware, rproc). Currently 'dsp' configuration is intended for audio firmware but it doesn't work well with board level DTs (e.g imx8mp-evk) because board level DT enables audio related IPs (e.g SAI) while audio firmware needs this IPs disabled (because firmware will configure them). So, configure 'dsp' node to be used with rproc. This way users will be able to use board DT to use the DSP as long as they don't clash with Audio IP configurations. More comples usage of 'dsp' node (e.g by audio firmware) will need to create a separate dts file (or an overlay). This change follows the approach taken for other i.MX8 boards in commit 391a319c81f6d7 ("arm64: dts: imx8-ss-audio: configure dsp node for rproc usage") Reviewed-by: Iuliana Prodan Reviewed-by: Peng Fan Signed-off-by: Daniel Baluta Reviewed-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index fc0d244cfd1e..708d3f61b4e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -281,7 +281,7 @@ reserved-memory { ranges; dsp_reserved: dsp@92400000 { - reg = <0 0x92400000 0 0x2000000>; + reg = <0 0x92400000 0 0x1000000>; no-map; status = "disabled"; }; @@ -2417,13 +2417,12 @@ usb_dwc3_1: usb@38200000 { }; dsp: dsp@3b6e8000 { - compatible = "fsl,imx8mp-dsp"; + compatible = "fsl,imx8mp-hifi4"; reg = <0x3b6e8000 0x88000>; - mbox-names = "txdb0", "txdb1", - "rxdb0", "rxdb1"; - mboxes = <&mu2 2 0>, <&mu2 2 1>, - <&mu2 3 0>, <&mu2 3 1>; - memory-region = <&dsp_reserved>; + power-domains = <&pgc_audio>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu2 0 0>, <&mu2 1 0>, <&mu2 3 0>; + firmware-name = "imx/dsp/hifi4.bin"; resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; reset-names = "runstall"; status = "disabled"; From ebccbe8d43cea95f16aec8ee6668474625c7a2a8 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Thu, 20 Mar 2025 14:09:54 +0200 Subject: [PATCH 07/71] arm64: dts: imx8mp: Add DSP clocks DSP core needs ocram, core and debug clocks. Reviewed-by: Iuliana Prodan Reviewed-by: Peng Fan Signed-off-by: Daniel Baluta Reviewed-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 708d3f61b4e1..c017eb98c49d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2419,6 +2419,11 @@ usb_dwc3_1: usb@38200000 { dsp: dsp@3b6e8000 { compatible = "fsl,imx8mp-hifi4"; reg = <0x3b6e8000 0x88000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>; + clock-names = "ipg", "ocram", "core", "debug"; power-domains = <&pgc_audio>; mbox-names = "tx", "rx", "rxdb"; mboxes = <&mu2 0 0>, <&mu2 1 0>, <&mu2 3 0>; From 68770d888192cd0b1d9d77baef3c2075d80a4a0f Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Thu, 20 Mar 2025 14:09:55 +0200 Subject: [PATCH 08/71] arm64: dts: imx8mp-evk: Enable DSP node for remoteproc usage Enable all relevant nodes to support remoteproc with imx8mp-evk board. - add rproc specific memory regions - enable dsp_reserved node - enable mu2 node - enable dsp node Signed-off-by: Daniel Baluta Reviewed-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index c26954e5a605..9ab3ee93a35b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -309,6 +309,16 @@ &aud2htx { status = "okay"; }; +&dsp_reserved { + status = "okay"; +}; + +&dsp { + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status = "okay"; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -690,6 +700,10 @@ dsi_out: endpoint { }; }; +&mu2 { + status = "okay"; +}; + &pcie_phy { fsl,refclk-pad-mode = ; clocks = <&pcie0_refclk>; From c197f323ed64ccd902832ddee907b2eb157f39dd Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Mar 2025 17:52:14 -0400 Subject: [PATCH 09/71] arm64: dts: imx8qm-mek: consolidate reserved-memory Move dsp_vdev* to under existed reserved-memory node to consolidate all reserved-memory together. Signed-off-by: Frank Li Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 34 +++++++++---------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index a669a5d500d3..4ba8ddd47223 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -40,24 +40,6 @@ memory@80000000 { reg = <0x00000000 0x80000000 0 0x40000000>; }; - reserved-memory { - dsp_vdev0vring0: memory@942f0000 { - reg = <0 0x942f0000 0 0x8000>; - no-map; - }; - - dsp_vdev0vring1: memory@942f8000 { - reg = <0 0x942f8000 0 0x8000>; - no-map; - }; - - dsp_vdev0buffer: memory@94300000 { - compatible = "shared-dma-pool"; - reg = <0 0x94300000 0 0x100000>; - no-map; - }; - }; - reg_usdhc2_vmmc: usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; @@ -189,6 +171,22 @@ vdevbuffer: memory@90400000 { no-map; }; + dsp_vdev0vring0: memory@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: memory@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: memory@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + gpu_reserved: memory@880000000 { no-map; reg = <0x8 0x80000000 0 0x10000000>; From 42b2ac9f1bfee9401adabde61e24082dd88b3d3e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 3 Apr 2025 21:59:31 -0500 Subject: [PATCH 10/71] arm64: dts: imx: Drop redundant CPU "clock-latency" The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". The OPP tables have values of 150000, so it can be removed. Signed-off-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ---- 4 files changed, 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 4de3bf22902b..cfebaa01217e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -62,7 +62,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -83,7 +82,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -102,7 +100,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -121,7 +118,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a5f9cfb46e5d..848ba5e46ee6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -62,7 +62,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -83,7 +82,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -102,7 +100,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -121,7 +118,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c017eb98c49d..75a1d02d39da 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -66,7 +66,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -87,7 +86,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -106,7 +104,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -125,7 +122,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 387b3e227cfc..07925b387677 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -106,7 +106,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -126,7 +125,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -144,7 +142,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -162,7 +159,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; From 4e13da7c73932572c7ee1c3bdc64cb94a3c0d875 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 8 Apr 2025 22:29:38 +0200 Subject: [PATCH 11/71] arm64: dts: freescale: imx8mp-verdin: Add EEPROM compatible fallback According to the AT24 EEPROM bindings the compatible string should contain first the actual manufacturer, and second the corresponding atmel model. Add the atmel compatible fallback accordingly. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index e3869efe4fd0..d43ba0087126 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -657,7 +657,7 @@ channel@7 { }; eeprom@50 { - compatible = "st,24c02"; + compatible = "st,24c02", "atmel,24c02"; pagesize = <16>; reg = <0x50>; }; @@ -770,7 +770,7 @@ hwmon_temp: sensor@4f { /* EEPROM on display adapter (MIPI DSI Display Adapter) */ eeprom_display_adapter: eeprom@50 { - compatible = "st,24c02"; + compatible = "st,24c02", "atmel,24c02"; pagesize = <16>; reg = <0x50>; status = "disabled"; @@ -778,7 +778,7 @@ eeprom_display_adapter: eeprom@50 { /* EEPROM on carrier board */ eeprom_carrier_board: eeprom@57 { - compatible = "st,24c02"; + compatible = "st,24c02", "atmel,24c02"; pagesize = <16>; reg = <0x57>; status = "disabled"; From ac1c1d2e2124387752b4cc955dd359753783c147 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 8 Apr 2025 22:29:39 +0200 Subject: [PATCH 12/71] arm64: dts: freescale: imx8mm-verdin: Add EEPROM compatible fallback According to the AT24 EEPROM bindings the compatible string should contain first the actual manufacturer, and second the corresponding atmel model. Add the atmel compatible fallback accordingly. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 7251ad3a0017..d3d3ebf035db 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -528,7 +528,7 @@ channel@7 { }; eeprom@50 { - compatible = "st,24c02"; + compatible = "st,24c02", "atmel,24c02"; pagesize = <16>; reg = <0x50>; }; @@ -633,7 +633,7 @@ hwmon_temp: sensor@4f { /* EEPROM on display adapter (MIPI DSI Display Adapter) */ eeprom_display_adapter: eeprom@50 { - compatible = "st,24c02"; + compatible = "st,24c02", "atmel,24c02"; pagesize = <16>; reg = <0x50>; status = "disabled"; @@ -641,7 +641,7 @@ eeprom_display_adapter: eeprom@50 { /* EEPROM on carrier board */ eeprom_carrier_board: eeprom@57 { - compatible = "st,24c02"; + compatible = "st,24c02", "atmel,24c02"; pagesize = <16>; reg = <0x57>; status = "disabled"; From ab4d874c9f44e448814f13b0fc8257d0efcfe230 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Wed, 9 Apr 2025 19:37:27 +0100 Subject: [PATCH 13/71] arm64: dts: imx8mp: Add device tree for Nitrogen8M Plus ENC Carrier Board Add support for Boundary Devices/Ezurio Nitrogen8M Plus ENC Carrier Board and it's SOM. Supported interfaces: - Serial Console - EQoS Ethernet - USB - eMMC - HDMI Signed-off-by: Martyn Welch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx8mp-nitrogen-enc-carrier-board.dts | 452 ++++++++++++++++++ .../dts/freescale/imx8mp-nitrogen-som.dtsi | 409 ++++++++++++++++ 3 files changed, 862 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index dba0c9ac10cf..09d16424ff91 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -202,6 +202,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts new file mode 100644 index 000000000000..1df9488aaeb2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Boundary Devices + * Copyright 2025 Collabora Ltd. + */ + +/dts-v1/; + +#include "imx8mp-nitrogen-som.dtsi" + +/ { + model = "Boundary Devices Nitrogen8M Plus ENC Carrier Board"; + compatible = "boundary,imx8mp-nitrogen-enc-carrier-board", + "boundary,imx8mp-nitrogen-som", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + reg_usb_vbus: regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_vbus>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + usb-hub-reset-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + line-name = "usb-hub-reset"; + output-low; + }; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-0 = <&pinctrl_hdmi>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c2 { + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinctrl_i2c2_pca9546>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + + rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + interrupts-extended = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv3028>; + wakeup-source; + }; + }; + }; +}; + +&i2c4 { + usb-mux@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + interrupts-extended = <&gpio1 8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_hd3ss3220>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; +}; + +&isp_0 { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3_0>; + usb-role-switch; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + + port@1 { + reg = <1>; + + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + bus-width = <4>; + cd-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x143 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x100 + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x119 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x41 + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x41 + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x41 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x41 + MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x41 + >; + }; + + pinctrl_i2c2_pca9546: i2c2-pca9546grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x100 + >; + }; + + pinctrl_i2c4_hd3ss3220: i2c4-hd3ss3220grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x03 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x100 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0xd6 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_reg_usb_vbus: reg-usb-vbusgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x100 + >; + }; + + pinctrl_rv3028: rv3028grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usb3_0: usb3-0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x116 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi new file mode 100644 index 000000000000..f658309612ef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Boundary Devices + * Copyright 2025 Collabora Ltd. + */ + +#include "imx8mp.dtsi" + +/ { + model = "Boundary Devices Nitrogen8M Plus Som"; + compatible = "boundary,imx8mp-nitrogen-som", "fsl,imx8mp"; + + rfkill-bt { + compatible = "rfkill-gpio"; + label = "rfkill-bluetooth"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rfkill_bt>; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + }; + + rfkill-wlan { + compatible = "rfkill-gpio"; + label = "rfkill-wlan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rfkill_wlan>; + radio-type = "wlan"; + shutdown-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + eee-broken-1000t; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_OPEN_DRAIN>; + sda-gpios = <&gpio5 15 GPIO_OPEN_DRAIN>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + interrupt-parent = <&gpio3>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + + regulators { + + buck1: BUCK1 { + regulator-name = "VDD_SOC (BUCK1)"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "VDD_ARM (BUCK2)"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3P3V (BUCK4)"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1P8V (BUCK5)"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + buck6: BUCK6 { + regulator-name = "NVCC_DRAM_1P1V (BUCK6)"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + ldo1: LDO1 { + regulator-name = "NVCC_SNVS_1V8 (LDO1)"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + }; + + ldo3: LDO3 { + regulator-name = "VDDA_1V8 (LDO3)"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD1 (LDO5)"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_OPEN_DRAIN>; + sda-gpios = <&gpio5 17 GPIO_OPEN_DRAIN>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_OPEN_DRAIN>; + sda-gpios = <&gpio5 19 GPIO_OPEN_DRAIN>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 GPIO_OPEN_DRAIN>; + sda-gpios = <&gpio5 21 GPIO_OPEN_DRAIN>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <8>; + non-removable; + no-mmc-hs400; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x20 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0xa0 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + + MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x10 + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x100 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41 + >; + }; + + pinctrl_rfkill_bt: rfkill-btgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 + >; + }; + + pinctrl_rfkill_wlan: rfkill-wlangrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x10 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x150 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x150 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x150 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x150 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x150 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x150 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x150 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x150 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x150 + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x140 + + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x14 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x154 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x154 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x154 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x154 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x154 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x154 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x154 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x154 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x154 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x12 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x152 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x152 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x152 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x152 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x152 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x152 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x152 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x152 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x152 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; From b6bf37e40cbec2ceb880b625d0635784dd64afec Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Thu, 10 Apr 2025 14:49:05 +0800 Subject: [PATCH 14/71] arm64: dts: imx95: add USB2.0 nodes Add USB2.0 controller and phy nodes. Tested-by: Alexander Stein # TQMa95xxSA Reviewed-by: Frank Li Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 9bb26b466a06..8dd859d8d319 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -470,6 +470,13 @@ its: msi-controller@48040000 { }; }; + usbphynop: usbphynop { + compatible = "usb-nop-xceiv"; + clocks = <&scmi_clk IMX95_CLK_HSIO>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -1621,6 +1628,29 @@ usb3_phy: phy@4c1f0040 { status = "disabled"; }; + usb2: usb@4c200000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c200000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + iommus = <&smmu 0xf>; + phys = <&usbphynop>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbmisc: usbmisc@4c200200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x0 0x4c200200 0x0 0x200>, + <0x0 0x4c010014 0x0 0x04>; + #index-cells = <1>; + }; + pcie0: pcie@4c300000 { compatible = "fsl,imx95-pcie"; reg = <0 0x4c300000 0 0x10000>, From c7358655579d280a2129eef047542101ac4e3579 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Thu, 10 Apr 2025 14:49:06 +0800 Subject: [PATCH 15/71] arm64: dts: imx95-19x19-evk: enable USB2.0 node On this board, USB2.0 is a host-only port, add vbus regulator node and enable USB2.0 node. Reviewed-by: Frank Li Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx95-19x19-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 25ac331f0318..a41d542488ed 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -145,6 +145,15 @@ reg_usdhc2_vmmc: regulator-usdhc2 { off-on-delay-us = <12000>; }; + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&i2c7_pcal6524 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,name = "bt-sco-audio"; @@ -461,6 +470,13 @@ &sai3 { status = "okay"; }; +&usb2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + &usb3 { status = "okay"; }; From a5b22b72e92a67e42f236a7c1c62245e30b1d477 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Thu, 10 Apr 2025 14:49:07 +0800 Subject: [PATCH 16/71] arm64: dts: imx95-15x15-evk: enable USB2.0 node On this board, USB2.0 is a host-only port, add vbus regulator node and enable USB2.0 node. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx95-15x15-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 514f2429dcbc..aa0b9a4c3688 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -136,6 +136,15 @@ reg_usdhc3_vmmc: regulator-usdhc3 { startup-delay-us = <20000>; }; + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_vcc_12v: regulator-vcc-12v { compatible = "regulator-fixed"; regulator-max-microvolt = <12000000>; @@ -1023,6 +1032,13 @@ &tpm6 { status = "okay"; }; +&usb2 { + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; + disable-over-current; + status = "okay"; +}; + &usb3 { status = "okay"; }; From eb0aadf0bd5edc8466ebff08bd17649807cc4da5 Mon Sep 17 00:00:00 2001 From: Ciprian Marian Costea Date: Thu, 10 Apr 2025 17:48:26 +0300 Subject: [PATCH 17/71] arm64: dts: s32gxxxa-rdb: Add PCA85073A RTC module over I2C0 Add support for the PCA85073A RTC module connected via I2C0 on S32G274A-RDB2 and S32G399A-RDB3 boards. Note that the PCA85073A RTC module is not battery backed. Signed-off-by: Ciprian Marian Costea Reviewed-by: Frank Li Reviewed-by: Matthias Brugger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi index ba53ec622f0b..4587e1cb8835 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi @@ -153,6 +153,11 @@ pcal6524: gpio-expander@22 { gpio-controller; #gpio-cells = <2>; }; + + pca85073a: rtc@51 { + compatible = "nxp,pca85073a"; + reg = <0x51>; + }; }; &i2c2 { From 97dc91c0455815137960bebd8c77a64544fd1251 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Mon, 14 Apr 2025 13:38:27 +0100 Subject: [PATCH 18/71] arm64: dts: freescale: add Toradex SMARC iMX8MP Add DT support for Toradex SMARC iMX8MP SoM and Toradex SMARC Development carrier board. Link: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx-8m-plus Link: https://www.toradex.com/products/carrier-board/smarc-development-board-kit Co-developed-by: Hiago De Franco Signed-off-by: Hiago De Franco Signed-off-by: Vitor Soares Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-toradex-smarc-dev.dts | 297 ++++ .../dts/freescale/imx8mp-toradex-smarc.dtsi | 1284 +++++++++++++++++ 3 files changed, 1582 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 09d16424ff91..edf9b2a66687 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -213,6 +213,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-bd500.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-tian-g07017.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts new file mode 100644 index 000000000000..581f221323b7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (C) 2025 Toradex */ + +/dts-v1/; + +#include "imx8mp-toradex-smarc.dtsi" + +/ { + model = "Toradex SMARC iMX8M Plus on Toradex SMARC Development Board"; + compatible = "toradex,smarc-imx8mp-dev", + "toradex,smarc-imx8mp", + "fsl,imx8mp"; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "J64"; + type = "a"; + + port { + native_hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + reg_carrier_1p8v: regulator-carrier-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier 1V8"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "tdx-smarc-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; +}; + +&aud2htx { + status = "okay"; +}; + +/* SMARC SPI0 */ +&ecspi1 { + status = "okay"; +}; + +/* SMARC GBE0 */ +&eqos { + status = "okay"; +}; + +/* SMARC GBE1 */ +&fec { + status = "okay"; +}; + +/* SMARC CAN1 */ +&flexcan1 { + status = "okay"; +}; + +/* SMARC CAN0 */ +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>, + <&pinctrl_gpio8>, + <&pinctrl_gpio9>, + <&pinctrl_gpio10>, + <&pinctrl_gpio11>, + <&pinctrl_gpio12>, + <&pinctrl_gpio13>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_dsi_sel>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>; +}; + +&hdmi_pvi { + status = "okay"; +}; + +/* SMARC HDMI */ +&hdmi_tx { + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&native_hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +/* SMARC I2C_LCD */ +&i2c2 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pins 4/6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pins 52/54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* SMARC I2C_CAM0 */ +&i2c3 { + status = "okay"; +}; + +/* SMARC I2C_GP */ +&i2c4 { + /* Audio Codec */ + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>, <&pinctrl_sai1_mclk>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <®_carrier_1p8v>; + CPVDD-supply = <®_carrier_1p8v>; + DBVDD-supply = <®_carrier_1p8v>; + DCVDD-supply = <®_carrier_1p8v>; + MICVDD-supply = <®_carrier_1p8v>; + }; + + /* On-Carrier Temperature Sensor */ + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* On-Carrier EEPROM */ + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* SMARC I2C_CAM1 */ +&i2c5 { + status = "okay"; +}; + +/* SMARC I2C_PM */ +&i2c6 { + clock-frequency = <100000>; + status = "okay"; + + /* Fan controller */ + fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + /* Current measurement into module VDD */ + hwmon@40 { + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +/* SMARC PCIE_A, M2 Key B */ +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* SMARC LCD1_BKLT_PWM */ +&pwm1 { + status = "okay"; +}; + +/* SMARC LCD0_BKLT_PWM */ +&pwm2 { + status = "okay"; +}; + +/* SMARC I2S0 */ +&sai1 { + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* SMARC HDMI Audio */ +&sound_hdmi { + status = "okay"; +}; + +/* SMARC SER0, RS485. Optional M.2 KEY E */ +&uart1 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +/* SMARC SER2 */ +&uart2 { + status = "okay"; +}; + +/* SMARC SER1, used as the Linux Console */ +&uart4 { + status = "okay"; +}; + +/* SMARC USB0 */ +&usb3_0 { + status = "okay"; +}; + +/* SMARC USB1..4 */ +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +/* SMARC SDIO */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi new file mode 100644 index 000000000000..0a8b9eee5ed9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi @@ -0,0 +1,1284 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (C) 2025 Toradex */ + +#include +#include +#include "imx8mp.dtsi" + +/ { + aliases { + can0 = &flexcan2; + can1 = &flexcan1; + ethernet0 = &eqos; + ethernet1 = &fec; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + serial0 = &uart1; + serial1 = &uart4; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart4; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_id>; + id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + label = "USB0"; + self-powered; + type = "micro"; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_0_dwc>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sleep>; + + smarc_key_sleep: key-sleep { + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + label = "SMARC_SLEEP#"; + wakeup-source; + linux,code = ; + }; + }; + + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_en_oc>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB0_EN_OC#"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_en_oc>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB2_EN_OC#"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3V3_SD"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vsel>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "PMIC_USDHC_VSELECT"; + vin-supply = <®_sd_3v3_1v8>; + }; + + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CTRL_EN_WIFI"; + startup-delay-us = <2000>; + }; + + reserved-memory { + linux,cma { + size = <0 0x20000000>; + alloc-ranges = <0 0x40000000 0 0x80000000>; + }; + }; + + sound_hdmi: sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +/* SMARC SPI0 */ +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio4 28 GPIO_ACTIVE_LOW>; +}; + +/* SMARC SPI1 */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio4 3 GPIO_ACTIVE_LOW>, + <&gpio3 6 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@2 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <2>; + spi-max-frequency = <18500000>; + }; +}; + +/* SMARC GBE0 */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>, + <&pinctrl_eth_mdio>, + <&pinctrl_eqos_1588_event>; + phy-handle = <&eqos_phy>; + phy-mode = "rgmii-id"; + snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; +}; + +/* SMARC GBE1 */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_1588_event>; + phy-handle = <&fec_phy>; + phy-mode = "rgmii-id"; + fsl,magic-packet; +}; + +/* SMARC CAN1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* SMARC CAN0 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&gpio1 { + gpio-line-names = "SMARC_GPIO7", /* 0 */ + "SMARC_GPIO8", + "", + "PMIC_INT#", + "PMIC_USDHC_VSELECT", + "SMARC_GPIO9", + "SMARC_GPIO10", + "SMARC_GPIO11", + "SMARC_GPIO12", + "", + "SMARC_GPIO5", /* 10 */ + "", + "SMARC_USB0_EN_OC#", + "SMARC_GPIO13", + "SMARC_USB2_EN_OC#"; +}; + +&gpio2 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "SMARC_SDIO_CD#", + "", + "", + "", + "", + "", + "", + "SMARC_SDIO_PWR_EN", + "SMARC_SDIO_WP"; /* 20 */ +}; + +&gpio3 { + gpio-line-names = "ETH_0_INT#", /* 0 */ + "SLEEP#", + "", + "", + "", + "", + "TPM_CS#", + "LVDS_DSI_SEL", + "MCU_INT#", + "GPIO_EX_INT#", + "", /* 10 */ + "", + "", + "", + "", + "", + "SMARC_SMB_ALERT#", + "", + "", + "", + "SMARC_I2C_PM_DAT", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "SMARC_I2C_PM_CK"; + + lvds_dsi_mux_hog: lvds-dsi-mux-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "LVDS_DSI_SEL"; + /* LVDS_DSI_SEL as DSI */ + output-low; + }; +}; + +&gpio4 { + gpio-line-names = "SMARC_PCIE_WAKE#", /* 0 */ + "", + "", + "SMARC_SPI1_CS1#", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "SMARC_GPIO4", + "SMARC_PCIE_A_RST#", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "SMARC_SPI0_CS1#", + "SMARC_GPIO6"; +}; + +&gpio5 { + gpio-line-names = "", /* 0 */ + "", + "SMARC_USB0_OTG_ID", + "SMARC_I2C_CAM1_CK", + "SMARC_I2C_CAM1_DAT", + "", + "", + "", + "", + "SMARC_SPI0_CS0#", + "", /* 10 */ + "", + "", + "SMARC_SPI1_CS0#", + "CTRL_I2C_SCL", + "CTRL_I2C_SDA", + "SMARC_I2C_LCD_CK", + "SMARC_I2C_LCD_DAT", + "SMARC_I2C_CAM0_CK", + "SMARC_I2C_CAM0_DAT", + "SMARC_I2C_GP_CK", /* 20 */ + "SMARC_I2C_GP_DAT"; +}; + +/* SMARC HDMI */ +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; +}; + +/* On-module I2C */ +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; + status = "okay"; + + som_gpio_expander: gpio-expander@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6408>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "SMARC_GPIO0", + "SMARC_GPIO1", + "SMARC_GPIO2", + "SMARC_GPIO3", + "SMARC_LCD0_VDD_EN", + "SMARC_LCD0_BKLT_EN", + "SMARC_LCD1_VDD_EN", + "SMARC_LCD1_BKLT_EN"; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <805000>; + regulator-name = "+VDD_SOC (PMIC BUCK1)"; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <805000>; + regulator-name = "+VDD_ARM (PMIC BUCK2)"; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3 (PMIC BUCK4)"; + }; + + reg_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8 (PMIC BUCK5)"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "+VDD_DDR (PMIC BUCK6)"; + }; + + LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1710000>; + regulator-name = "+V1.8_SNVS (PMIC LDO1)"; + }; + + LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A (PMIC LDO3)"; + }; + + LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_ADC (PMIC LDO4)"; + }; + + reg_sd_3v3_1v8: LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V3.3_1.8_SD (PMIC LDO5)"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* SMARC I2C_LCD */ +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* SMARC I2C_CAM0 */ +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* SMARC I2C_GP */ +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; + status = "okay"; + + eeprom@50 { + compatible = "st,24c32", "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +/* SMARC I2C_CAM1 */ +&i2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* SMARC I2C_PM */ +&i2c6 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +&mdio { + eqos_phy: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; + + fec_phy: ethernet-phy@2 { + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +/* SMARC PCIE_A */ +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; +}; + +/* SMARC LCD1_BKLT_PWM */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_bklt_pwm1>; +}; + +/* SMARC LCD0_BKLT_PWM */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_bklt_pwm2>; +}; + +/* SMARC GPIO5 as PWM */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5_pwm>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* SMARC SER0 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; +}; + +/* SMARC SER2 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +/* On-module Bluetooth, optional SMARC SER3 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + uart-has-rtscts; + status = "okay"; + + som_bt: bluetooth { + compatible = "mrvl,88w8997"; + max-speed = <921600>; + }; +}; + +/* SMARC SER1, used as the Linux Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +/* SMARC USB0 */ +&usb3_0 { + fsl,disable-port-power-control; +}; + +/* SMARC USB1..4 */ +&usb3_1 { + fsl,disable-port-power-control; +}; + +&usb3_phy1 { + vbus-supply = <®_usb1_vbus>; +}; + +&usb_dwc3_0 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + maximum-speed = "high-speed"; + srp-disable; + usb-role-switch; + + port { + usb3_0_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; +}; + +/* On-module Wi-Fi */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +/* SMARC SDIO */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, + <&pinctrl_usdhc2_cd>, + <&pinctrl_usdhc2_wp>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, + <&pinctrl_usdhc2_cd>, + <&pinctrl_usdhc2_wp>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, + <&pinctrl_usdhc2_cd>, + <&pinctrl_usdhc2_wp>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, + <&pinctrl_usdhc2_cd_sleep>, + <&pinctrl_usdhc2_wp>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +}; + +/* On-module eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + /* On-module Bluetooth */ + pinctrl_bt_uart: btuartgrp { + fsl,pins = , /* WiFi_UART_TXD */ + , /* WiFi_UART_RXD */ + , /* WiFi_UART_RTS */ + ; /* WiFi_UART_CTS */ + }; + + /* SMARC CAM_MCK */ + pinctrl_csi_mclk: csimclkgrp { + fsl,pins = ; /* SMARC S6 - CAM_MCK */ + }; + + /* SMARC SPI0 */ + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , /* SMARC P45 - SPI0_DIN */ + , /* SMARC P46 - SPI0_DO */ + , /* SMARC P44 - SPI0_CK */ + , /* SMARC P43 - SPI0_CS0# */ + ; /* SMARC P31 - SPI0_CS1# */ + }; + + /* SMARC SPI1 */ + pinctrl_ecspi2: ecspi2grp { + fsl,pins = , /* SMARC P56 - SPI1_DIN */ + , /* SMARC P57 - SPI1_DO */ + , /* SMARC P58 - SPI1_CK */ + , /* SMARC P54 - SPI1_CS0# */ + ; /* SMARC P55 - SPI1_CS1# */ + }; + + /* ETH_0 RGMII (On-module PHY) */ + pinctrl_eqos: eqosgrp { + fsl,pins = , /* ETH0_RGMII_RXD0 */ + , /* ETH0_RGMII_RXD1 */ + , /* ETH0_RGMII_RXD2 */ + , /* ETH0_RGMII_RXD3 */ + , /* ETH0_RGMII_RXC */ + , /* ETH0_RGMII_RX_CTL */ + , /* ETH0_RGMII_TXD0 */ + , /* ETH0_RGMII_TXD1 */ + , /* ETH0_RGMII_TXD2 */ + , /* ETH0_RGMII_TXD3 */ + , /* ETH0_RGMII_TX_CTL */ + ; /* ETH0_RGMII_TXC */ + }; + + /* SMARC GBE0_SDP */ + pinctrl_eqos_1588_event: eqos1588eventgrp { + fsl,pins = ; /* SMARC P6 - GBE0_SDP */ + }; + + /* ETH_0_MDIO and ETH_0_INT# shared between ETH_PHY0 and ETH_PHY1 */ + pinctrl_eth_mdio: ethmdiogrp { + fsl,pins = , /* ETH_0_MDC */ + , /* ETH_0_MDIO */ + ; /* ETH_0_INT# */ + }; + + /* ETH_1 RGMII (On-module PHY) */ + pinctrl_fec: fecgrp { + fsl,pins = , /* ETH1_RGMII_RXD0 */ + , /* ETH1_RGMII_RXD1 */ + , /* ETH1_RGMII_RXD2 */ + , /* ETH1_RGMII_RXD3 */ + , /* ETH1_RGMII_RXC */ + , /* ETH1_RGMII_RX_CTL */ + , /* ETH1_RGMII_TXD0 */ + , /* ETH1_RGMII_TXD1 */ + , /* ETH1_RGMII_TXD2 */ + , /* ETH1_RGMII_TXD3 */ + , /* ETH1_RGMII_TX_CTL */ + ; /* ETH1_RGMII_TXC */ + }; + + /* SMARC GBE1_SDP */ + pinctrl_fec_1588_event: fec1588eventgrp { + fsl,pins = ; /* SMARC P5 - GBE1_SDP */ + }; + + /* SMARC CAN1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , /* SMARC P146 - CAN1_RX */ + ; /* SMARC P145 - CAN1_TX */ + }; + + /* SMARC CAN0 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , /* SMARC P144 - CAN0_RX */ + ; /* SMARC P143 - CAN0_TX */ + }; + + /* SMARC GPIO4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = ; /* SMARC P112 - GPIO4 */ + }; + + /* SMARC GPIO5 */ + pinctrl_gpio5: gpio5grp { + fsl,pins = ; /* SMARC P113 - GPIO5 */ + }; + + /* SMARC GPIO5 as PWM */ + pinctrl_gpio5_pwm: gpio5pwmgrp { + fsl,pins = ; /* SMARC P113 - PWM_OUT */ + }; + + /* SMARC GPIO6 */ + pinctrl_gpio6: gpio6grp { + fsl,pins = ; /* SMARC P114 - GPIO6 */ + }; + + /* SMARC GPIO7 */ + pinctrl_gpio7: gpio7grp { + fsl,pins = ; /* SMARC P115 - GPIO7 */ + }; + + /* SMARC GPIO8 */ + pinctrl_gpio8: gpio8grp { + fsl,pins = ; /* SMARC P116 - GPIO8 */ + }; + + /* SMARC GPIO9 */ + pinctrl_gpio9: gpio9grp { + fsl,pins = ; /* SMARC P117 - GPIO9 */ + }; + + /* SMARC GPIO10 */ + pinctrl_gpio10: gpio10grp { + fsl,pins = ; /* SMARC P118 - GPIO10 */ + }; + + /* SMARC GPIO11 */ + pinctrl_gpio11: gpio11grp { + fsl,pins = ; /* SMARC P119 - GPIO11 */ + }; + + /* SMARC GPIO12 */ + pinctrl_gpio12: gpio12grp { + fsl,pins = ; /* SMARC S142 - GPIO12 */ + }; + + /* SMARC GPIO13 */ + pinctrl_gpio13: gpio13grp { + fsl,pins = ; /* SMARC S123 - GPIO13 */ + }; + + /* SMARC HDMI */ + pinctrl_hdmi: hdmigrp { + fsl,pins = , /* SMARC P105 - HDMI_CTRL_CK */ + , /* SMARC P106 - HDMI_CTRL_DAT */ + ; /* SMARC P104 - HDMI_HPD */ + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = , /* CTRL_I2C_SCL */ + ; /* CTRL_I2C_SDA */ + }; + + /* On-module I2C as GPIOs */ + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = , /* CTRL_I2C_SCL */ + ; /* CTRL_I2C_SDA */ + }; + + /* SMARC I2C_LCD */ + pinctrl_i2c2: i2c2grp { + fsl,pins = , /* SMARC S139 - I2C_LCD_CK */ + ; /* SMARC S140 - I2C_LCD_DAT */ + }; + + /* SMARC I2C_LCD as GPIOs */ + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = , /* SMARC S139 - I2C_LCD_CK */ + ; /* SMARC S140 - I2C_LCD_DAT */ + }; + + /* SMARC I2C_CAM0 */ + pinctrl_i2c3: i2c3grp { + fsl,pins = , /* SMARC S5 - I2C_CAM0_CK */ + ; /* SMARC S7 - I2C_CAM0_DAT */ + }; + + /* SMARC I2C_CAM0 as GPIOs */ + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = , /* SMARC S5 - I2C_CAM0_CK */ + ; /* SMARC S7 - I2C_CAM0_DAT */ + }; + + /* SMARC I2C_GP */ + pinctrl_i2c4: i2c4grp { + fsl,pins = , /* SMARC S48 - I2C_GP_CK */ + ; /* SMARC S49 - I2C_GP_DAT */ + }; + + /* SMARC I2C_GP as GPIOs */ + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = , /* SMARC S48 - I2C_GP_CK */ + ; /* SMARC S49 - I2C_GP_DAT */ + }; + + /* SMARC I2C_CAM1 */ + pinctrl_i2c5: i2c5grp { + fsl,pins = , /* SMARC S2 - I2C_CAM1_DAT */ + ; /* SMARC S1 - I2C_CAM1_CK */ + }; + + /* SMARC I2C_CAM1 as GPIOs */ + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = , /* SMARC S2 - I2C_CAM1_DAT */ + ; /* SMARC S1 - I2C_CAM1_CK */ + }; + + /* SMARC I2C_PM */ + pinctrl_i2c6: i2c6grp { + fsl,pins = , /* SMARC P121 - I2C_PM_CK */ + ; /* SMARC P122 - I2C_PM_DAT */ + }; + + /* SMARC I2C_PM as GPIOs */ + pinctrl_i2c6_gpio: i2c6gpiogrp { + fsl,pins = , /* SMARC P121 - I2C_PM_CK */ + ; /* SMARC P122 - I2C_PM_DAT */ + }; + + pinctrl_lvds_dsi_sel: lvdsdsiselgrp { + fsl,pins = ; /* LVDS_DSI_SEL */ + }; + + pinctrl_mcu_int: mcuintgrp { + fsl,pins = ; /* MCU_INT# */ + }; + + /* SMARC LCD1_BKLT_PWM */ + pinctrl_lcd1_bklt_pwm1: pwm1grp { + fsl,pins = ; /* SMARC S122 - LCD1_BKLT_PWM */ + }; + + /* SMARC LCD0_BKLT_PWM */ + pinctrl_lcd0_bklt_pwm2: pwm2grp { + fsl,pins = ; /* SMARC S141 - LCD0_BKLT_PWM */ + }; + + /* PCAL6408 Interrupt */ + pinctrl_pcal6408: pcal6408intgrp { + fsl,pins = ; /* GPIO_EX_INT# */ + }; + + /* SMARC PCIE_A */ + pinctrl_pcie: pciegrp { + fsl,pins = , /* SMARC S146 - PCIE_WAKE# */ + ; /* SMARC P75 - PCIE_A_RST# */ + }; + + /* PMIC Interrupt */ + pinctrl_pmic: pmicintgrp { + fsl,pins = ; /* PMIC_INT# */ + }; + + /* SMARC I2S0 */ + pinctrl_sai1: sai1grp { + fsl,pins = , /* SMARC S42 - I2S0_CK */ + , /* SMARC S39 - I2S0_LRCLK */ + , /* SMARC S41 - I2S0_SDIN */ + ; /* SMARC S40 - I2S0_SDOUT */ + }; + + /* SMARC AUDIO_MCK */ + pinctrl_sai1_mclk: sai1mclkgrp { + fsl,pins = ; /* SMARC S38 - AUDIO_MCK */ + }; + + /* SMARC I2S2 */ + pinctrl_sai3: sai3grp { + fsl,pins = , /* SMARC S52 - I2S2_SDIN */ + , /* SMARC S53 - I2S2_CK */ + , /* SMARC S51 - I2S2_SDOUT */ + ; /* SMARC S50 - I2S2_LRCLK */ + }; + + /* SMARC SLEEP# */ + pinctrl_sleep: sleepgrp { + fsl,pins = ; /* SMARC S149 - SLEEP# */ + }; + + /* SMARC SMB_ALERT# */ + pinctrl_smb_alert: smbalertgrp { + fsl,pins = ; /* SMARC P1 - SMB_ALERT# */ + }; + + /* TPM_CS# */ + pinctrl_tpm_cs: tpmcsgrp { + fsl,pins = ; /* TPM_CS# */ + }; + + /* WIFI_BT_WKUP_HOST/TPM_INT# */ + pinctrl_tpm_irq_wifi_bt_wkup: tpmirq-wifibtwkupgrp { + fsl,pins = ; /* WIFI_BT_WKUP_HOST/TPM_INT# */ + }; + + /* SMARC SER0 */ + pinctrl_uart1: uart1grp { + fsl,pins = , /* SMARC P132 - SER2_CTS */ + , /* SMARC P131 - SER2_RTS */ + , /* SMARC P130 - SER2_RX */ + ; /* SMARC P139 - SER2_TX */ + }; + + /* SMARC SER2 */ + pinctrl_uart2: uart2grp { + fsl,pins = , /* SMARC P139 - SER2_CTS */ + , /* SMARC P138 - SER2_RTS */ + , /* SMARC P137 - SER2_RX */ + ; /* SMARC P136 - SER2_TX */ + }; + + /* SMARC SER3 */ + pinctrl_uart3: uart3grp { + fsl,pins = , /* SMARC P141 - SER3_RX */ + ; /* SMARC P140 - SER3_TX */ + }; + + /* SMARC SER1 */ + pinctrl_uart4: uart4grp { + fsl,pins = , /* SMARC P135 - SER1_RX */ + ; /* SMARC P134 - SER1_TX */ + }; + + /* SMARC USB0_OTG_ID */ + pinctrl_usb0_id: usb0idgrp { + fsl,pins = ; /* SMARC P64 - USB0_OTG_ID */ + }; + + /* SMARC USB0_EN_OC# */ + pinctrl_usb0_en_oc: usb0enocgrp { + fsl,pins = ; /* SMARC P62 - USB0_EN_OC# */ + }; + + /* On module USB Hub VBUS, or SMARC USB2_EN_OC# depending on assembling */ + pinctrl_usb1_en_oc: usb1enocgrp { + fsl,pins = ; /* SMARC P71 - USB2_EN_OC# */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , /* WiFi_SDIO_CLK */ + , /* WiFi_SDIO_CMD */ + , /* WiFi_SDIO_DATA0 */ + , /* WiFi_SDIO_DATA1 */ + , /* WiFi_SDIO_DATA2 */ + ; /* WiFi_SDIO_DATA3 */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , /* WiFi_SDIO_CLK */ + , /* WiFi_SDIO_CMD */ + , /* WiFi_SDIO_DATA0 */ + , /* WiFi_SDIO_DATA1 */ + , /* WiFi_SDIO_DATA2 */ + ; /* WiFi_SDIO_DATA3 */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , /* WiFi_SDIO_CLK */ + , /* WiFi_SDIO_CMD */ + , /* WiFi_SDIO_DATA0 */ + , /* WiFi_SDIO_DATA1 */ + , /* WiFi_SDIO_DATA2 */ + ; /* WiFi_SDIO_DATA3 */ + }; + + /* SMARC SDIO */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , /* SMARC P36 - SDIO_CK */ + , /* SMARC P34 - SDIO_CMD */ + , /* SMARC P39 - SDIO_DO */ + , /* SMARC P40 - SDIO_D1 */ + , /* SMARC P41 - SDIO_D2 */ + ; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO 100MHz */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , /* SMARC P36 - SDIO_CK */ + , /* SMARC P34 - SDIO_CMD */ + , /* SMARC P39 - SDIO_DO */ + , /* SMARC P40 - SDIO_D1 */ + , /* SMARC P41 - SDIO_D2 */ + ; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO 200MHz */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , /* SMARC P36 - SDIO_CK */ + , /* SMARC P34 - SDIO_CMD */ + , /* SMARC P39 - SDIO_DO */ + , /* SMARC P40 - SDIO_D1 */ + , /* SMARC P41 - SDIO_D2 */ + ; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO_CD# */ + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = ; /* SMARC P35 - SDIO_CD# */ + }; + + /* SMARC SDIO_CD# */ + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = ; /* SMARC P35 - SDIO_CD# */ + }; + + /* SMARC SDIO_PWR_EN */ + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = ; /* SMARC P37 - SDIO_PWR_EN */ + }; + + /* SMARC SDIO Sleep - Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = , /* SMARC P36 - SDIO_CK */ + , /* SMARC P34 - SDIO_CMD */ + , /* SMARC P39 - SDIO_DO */ + , /* SMARC P39 - SDIO_D1 */ + , /* SMARC P39 - SDIO_D2 */ + ; /* SMARC P39 - SDIO_D3 */ + }; + + pinctrl_usdhc2_vsel: usdhc2vselgrp { + fsl,pins = ; /* PMIC_USDHC_VSELECT */ + }; + + /* SMARC SDIO_WP */ + pinctrl_usdhc2_wp: usdhc2wpgrp { + fsl,pins = ; /* SMARC P33 - SDIO_WP */ + }; + + /* On-module eMMC */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , /* eMMC_STROBE */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_CLK */ + ; /* eMMC_CMD */ + }; + + /* On-module eMMC */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , /* eMMC_STROBE */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_CLK */ + ; /* eMMC_CMD */ + }; + + /* On-module eMMC */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , /* eMMC_STROBE */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_CLK */ + ; /* eMMC_CMD */ + }; + + /* SoC Watchdog */ + pinctrl_wdog: wdoggrp { + fsl,pins = ; /* CTRL_SOC_WDOG */ + }; + + /* On-module Wi-Fi power enable */ + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = ; /* CTRL_EN_WIFI */ + }; +}; From e5bc07026f9489908ab8aa11544a26123af0c54c Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 15 Apr 2025 14:59:45 +0200 Subject: [PATCH 19/71] arm64: add initial device tree for TQMa93xx/MBa91xxCA This adds support for TQMa93xx module attached to MBa91xxCA board. TQMa93xx is a SOM using i.MX93 SOC. The SOM features PMIC, RAM, e-MMC and some optional peripherals like SPI-NOR, RTC, EEPROM, gyroscope and secure element. TQMa93xxCA can be attached directly while TQMa93xxLA needs an adapter. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx93-tqma9352-mba91xxca.dts | 749 ++++++++++++++++++ 2 files changed, 750 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index edf9b2a66687..186101781440 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -300,6 +300,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts new file mode 100644 index 000000000000..7b78faa4bfd0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts @@ -0,0 +1,749 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include "imx93-tqma9352.dtsi" + +/{ + model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa91xxCA starter kit"; + compatible = "tq,imx93-tqma9352-mba91xxca", "tq,imx93-tqma9352", "fsl,imx93"; + chassis-type = "embedded"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = &eqos; + ethernet1 = &fec; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm2 2 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + power-supply = <®_3v3>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + status = "disabled"; + + port { + panel_in: endpoint { + }; + }; + }; + + fan0: gpio-fan { + compatible = "gpio-fan"; + gpios = <&expander2 4 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, <10000 1>; + fan-supply = <®_12v0>; + #cooling-cells = <2>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = ; + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label = "switchb"; + linux,code = ; + gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + lvds_encoder: lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + powerdown-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; + power-supply = <®_3v3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + }; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_MB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + thermal-zones { + cpu-thermal { + trips { + cpu_active: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_active>; + cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + /* 00 */ "", "", "", "PMIC_IRQ#", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#", + /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* 00 */ "SD2_CD#", "", "", "", + /* 04 */ "", "", "", "SD2_RST#", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + label = "X17"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + typec-power-opmode = "default"; + pd-disable; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + + eeprom2: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3>; + gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#", + "MPCIE_1V5_EN", "MPCIE_3V3_EN", + "MPCIE_PERST#", "MPCIE_WDISABLE#", + "BUTTON_A#", "BUTTON_B#"; + + temp-event-mod-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "TEMP_EVENT_MOD#"; + }; + + mpcie-wake-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "MPCIE_WAKE#"; + }; + + /* + * Controls the mPCIE slot reset which is low active as + * reset signal. The output-low states, the signal is + * inactive, e.g. not in reset + */ + mpcie_rst_hog: mpcie-rst-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_PERST#"; + }; + + /* + * Controls the mPCIE slot WDISABLE pin which is low active + * as disable signal. The output-low states, the signal is + * inactive, e.g. not disabled + */ + mpcie_wdisable_hog: mpcie-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_WDISABLE#"; + }; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the WiFi card PD pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + wlan-pd-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PD#"; + }; + + /* + * Controls the WiFi card disable pin which is low active + * as disable signal. The output-low states, the signal + * is inactive, e.g. not disabled + */ + wlan-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible = "nxp,pca9538"; + reg = <0x72>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", + "LCD_BLT_EN", "LVDS_SHDN#", + "FAN_PWR_EN", "", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&se97_som { + /* TEMP_EVENT# from SoM is connected on mainboard */ + interrupt-parent = <&expander0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +}; + +&tpm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + disable-wp; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | ODE | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X3 */ + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_fec: fecgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | ODE | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X3 */ + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = ; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_rgbdisp: rgbdispgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_touch: touchgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_tpm2: tpm2grp { + fsl,pins = ; + }; + + pinctrl_typec: typecgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X5 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + /* HYS | PU | FSEL_3 | DSE X3 */ + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X6 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; +}; From 2e98d456666d63f897ba153210bcef9d78ba0f3a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:27 -0500 Subject: [PATCH 20/71] arm64: dts: imx8mm-beacon: Fix RTC capacitive load Although not noticeable when used every day, the RTC appears to drift when left to sit over time. This is due to the capacitive load not being properly set. Fix RTC drift by correcting the capacitive load setting from 7000 to 12500, which matches the actual hardware configuration. Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit") Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 62ed64663f49..9ba0cb89fa24 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -233,6 +233,7 @@ eeprom@50 { rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + quartz-load-femtofarads = <12500>; }; }; From c3f03bec30efd5082b55876846d57b5d17dae7b9 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:28 -0500 Subject: [PATCH 21/71] arm64: dts: imx8mn-beacon: Fix RTC capacitive load Although not noticeable when used every day, the RTC appears to drift when left to sit over time. This is due to the capacitive load not being properly set. Fix RTC drift by correcting the capacitive load setting from 7000 to 12500, which matches the actual hardware configuration. Fixes: 36ca3c8ccb53 ("arm64: dts: imx: Add Beacon i.MX8M Nano development kit") Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 2a64115eebf1..bb11590473a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -242,6 +242,7 @@ eeprom@50 { rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + quartz-load-femtofarads = <12500>; }; }; From 6821ee17537938e919e8b86a541aae451f73165b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:29 -0500 Subject: [PATCH 22/71] arm64: dts: imx8mp-beacon: Fix RTC capacitive load Although not noticeable when used every day, the RTC appears to drift when left to sit over time. This is due to the capacitive load not being properly set. Fix RTC drift by correcting the capacitive load setting from 7000 to 12500, which matches the actual hardware configuration. Fixes: 25a5ccdce767 ("arm64: dts: freescale: Introduce imx8mp-beacon-kit") Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi index 15f7ab58db36..88561df70d03 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi @@ -257,6 +257,7 @@ eeprom@50 { rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + quartz-load-femtofarads = <12500>; }; }; From 8c716f80dfe8cd6ed9a2696847cea1affeeff6ff Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:30 -0500 Subject: [PATCH 23/71] arm64: dts: imx8mm-beacon: Set SAI5 MCLK direction to output for HDMI audio The HDMI bridge chip fails to generate an audio source due to the SAI5 master clock (MCLK) direction not being set to output. This prevents proper clocking of the HDMI audio interface. Add the `fsl,sai-mclk-direction-output` property to the SAI5 node to ensure the MCLK is driven by the SoC, resolving the HDMI sound issue. Fixes: 8ad7d14d99f3 ("arm64: dts: imx8mm-beacon: Add HDMI video with sound") Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts index 97ff1ddd6318..734a75198f06 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts @@ -124,6 +124,7 @@ &sai5 { assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; status = "okay"; }; From a747c4dd2a60c4d0179b372032a4b98548135096 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:31 -0500 Subject: [PATCH 24/71] arm64: dts: imx8mn-beacon: Set SAI5 MCLK direction to output for HDMI audio The HDMI bridge chip fails to generate an audio source due to the SAI5 master clock (MCLK) direction not being set to output. This prevents proper clocking of the HDMI audio interface. Add the `fsl,sai-mclk-direction-output` property to the SAI5 node to ensure the MCLK is driven by the SoC, resolving the HDMI sound issue. Fixes: 1d6880ceef43 ("arm64: dts: imx8mn-beacon: Add HDMI video with sound") Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts index 1df5ceb11387..37fc5ed98d7f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts @@ -124,6 +124,7 @@ &sai5 { assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; status = "okay"; }; From 1c98ceb0d75e17aa59308ed0cf46e48b90006241 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:32 -0500 Subject: [PATCH 25/71] arm64: dts: imx8mm-beacon: Configure Ethernet PHY reset and GPIO IRQ The Ethernet PHY setup currently assumes that the bootloader will take the PHY out of reset, but this behavior is not guaranteed across all bootloaders. Add the reset GPIO to ensure the kernel can properly control the PHY reset line. Also configure the PHY IRQ GPIO to enable interrupt-driven link status reporting, instead of relying on polling. This ensures more reliable Ethernet initialization and improves PHY event handling. Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 9ba0cb89fa24..ed7a1be4a1a6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -78,6 +78,9 @@ mdio { ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -315,6 +318,7 @@ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; From b08fc2f0fd99abc6cb2320fc58e2ff22a02f2b92 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:33 -0500 Subject: [PATCH 26/71] arm64: dts: imx8mn-beacon: Configure Ethernet PHY reset and GPIO IRQ The Ethernet PHY setup currently assumes that the bootloader will take the PHY out of reset, but this behavior is not guaranteed across all bootloaders. Add the reset GPIO to ensure the kernel can properly control the PHY reset line. Also configure the PHY IRQ GPIO to enable interrupt-driven link status reporting, instead of relying on polling. This ensures more reliable Ethernet initialization and improves PHY event handling. Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index bb11590473a4..b3692b367a42 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -88,6 +88,9 @@ mdio { ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -326,6 +329,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; From 2cb333ddd62f265be052842454e310c0a433b65a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:34 -0500 Subject: [PATCH 27/71] arm64: dts: imx8mm-beacon: Enable RTC interrupt and wakeup-source Enable the interrupts and wakeup-source to allow the external RTC to be used as an alarm. Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index ed7a1be4a1a6..c7a8f2a6fe90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -236,7 +236,12 @@ eeprom@50 { rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; quartz-load-femtofarads = <12500>; + wakeup-source; }; }; @@ -354,6 +359,12 @@ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 From 12cc5a3898db7ea2ee756672f511a2cde370142a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:35 -0500 Subject: [PATCH 28/71] arm64: dts: imx8mn-beacon: Enable RTC interrupt and wakeup-source Enable the interrupts and wakeup-source to allow the external RTC to be used as an alarm. Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index b3692b367a42..987c14d3af9d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -245,7 +245,12 @@ eeprom@50 { rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; quartz-load-femtofarads = <12500>; + wakeup-source; }; }; @@ -365,6 +370,12 @@ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 From 8dd0e8a4966804e8aaf40c03e508191256e1437b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:36 -0500 Subject: [PATCH 29/71] arm64: dts: imx8mp-beacon: Enable RTC interrupt and wakeup-source Enable the interrupts and wakeup-source to allow the external RTC to be used as an alarm. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi index 88561df70d03..6a62cb32e22e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi @@ -257,7 +257,12 @@ eeprom@50 { rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; quartz-load-femtofarads = <12500>; + wakeup-source; }; }; @@ -382,6 +387,12 @@ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1d0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 From 14e66e4b13221d1b50291441600f5739abe50e09 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Thu, 17 Apr 2025 10:15:19 +0200 Subject: [PATCH 30/71] Revert "arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIO" Using the MDIO pins with Open Drain causes spec violations of the signals. Revert the changes. This reverts commit 9015397c2f2d9d327c0cf88d74e39c4858cb4912. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index ebbac5f8d2b2..137b8ed242a2 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -627,8 +627,8 @@ pinctrl_eqos: eqosgrp { fsl,pins = < /* PD | FSEL_2 | DSE X4 */ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e - /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000191e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e /* HYS | FSEL_0 | DSE no drive */ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000 @@ -659,8 +659,8 @@ pinctrl_fec: fecgrp { fsl,pins = < /* PD | FSEL_2 | DSE X4 */ MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e - /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000191e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e /* HYS | FSEL_0 | DSE no drive */ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000 From e05fae71e68f84c0743eda72fdddeee1e468e9e5 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Thu, 17 Apr 2025 10:15:20 +0200 Subject: [PATCH 31/71] Revert "arm64: dts: imx93-tqma9352-mba93xxla: enable Open Drain for MDIO" Using the MDIO pins with Open Drain causes spec violations of the signals. Revert the changes. This reverts commit 315d7f301e234b99c1b9619f0b14cf288dc7c33f. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index 9e88c42c3d17..219f49a4f87f 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -597,8 +597,8 @@ pinctrl_eqos: eqosgrp { fsl,pins = < /* PD | FSEL_2 | DSE X4 */ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e - /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000191e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e /* HYS | FSEL_0 | DSE no drive */ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000 @@ -629,8 +629,8 @@ pinctrl_fec: fecgrp { fsl,pins = < /* PD | FSEL_2 | DSE X4 */ MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e - /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000191e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e /* HYS | FSEL_0 | DSE no drive */ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000 From e2cfc140ae25cff0aae5a417adef0c0da61951c4 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 16 Apr 2025 17:13:41 +0200 Subject: [PATCH 32/71] arm64: dts: imx8-apalis: Add PCIe and SATA support The needed drivers to support PCIe and SATA for i.MX 8QM have been added. Configure them for the Apalis iMX8 SoM. The pciea and pcieb blocks each get a single PCIe lane, pciea is available on the carrier boards while pcieb is connected to the on module Wi-Fi/BT module. The SATA lane is available on the carrier boards. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-apalis-eval.dtsi | 10 ++- .../dts/freescale/imx8-apalis-ixora-v1.1.dtsi | 10 ++- .../dts/freescale/imx8-apalis-ixora-v1.2.dtsi | 10 ++- .../boot/dts/freescale/imx8-apalis-v1.1.dtsi | 70 ++++++++++++------- .../boot/dts/freescale/imx8qm-apalis.dtsi | 10 ++- 5 files changed, 74 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi index dc127298715b..311d4950793c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi @@ -104,7 +104,10 @@ &lsio_pwm3 { status = "okay"; }; -/* TODO: Apalis PCIE1 */ +/* Apalis PCIE1 */ +&pciea { + status = "okay"; +}; /* TODO: Apalis BKL1_PWM */ @@ -121,7 +124,10 @@ &sai5_lpcg { status = "okay"; }; -/* TODO: Apalis SATA1 */ +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; /* Apalis SPDIF1 */ &spdif0 { diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index d4a1ad528f65..3d8731504ce1 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -191,7 +191,10 @@ &lsio_pwm3 { status = "okay"; }; -/* TODO: Apalis PCIE1 */ +/* Apalis PCIE1 */ +&pciea { + status = "okay"; +}; /* TODO: Apalis BKL1_PWM */ @@ -208,7 +211,10 @@ &sai5_lpcg { status = "okay"; }; -/* TODO: Apalis SATA1 */ +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; /* Apalis SPDIF1 */ &spdif0 { diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi index 5e132c83e1b2..106e802a68ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -240,7 +240,10 @@ &lsio_pwm3 { status = "okay"; }; -/* TODO: Apalis PCIE1 */ +/* Apalis PCIE1 */ +&pciea { + status = "okay"; +}; /* TODO: Apalis BKL1_PWM */ @@ -257,7 +260,10 @@ &sai5_lpcg { status = "okay"; }; -/* TODO: Apalis SATA1 */ +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; /* Apalis SPDIF1 */ &spdif0 { diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index dbea1eefdeec..6f27a9cc2494 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -339,6 +339,25 @@ &flexcan3 { pinctrl-0 = <&pinctrl_flexcan3>; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-pcieb-sata"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + +&hsio_refa_clk { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_sata_refclk>; + enable-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; +}; + +&hsio_refb_clk { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; + clocks = <&hsio_refa_clk>; + enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>; +}; + /* TODO: Apalis HDMI1 */ &gpu_alert0 { @@ -514,7 +533,10 @@ &lsio_gpio0 { "MXM3_112", "MXM3_118", "MXM3_114", - "MXM3_116"; + "MXM3_116", + "", + "", + "MXM3_26"; }; &lsio_gpio1 { @@ -586,15 +608,6 @@ &lsio_gpio2 { "MXM3_183", "MXM3_185", "MXM3_187"; - - pcie-wifi-hog { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - line-name = "PCIE_WIFI_CLK"; - output-high; - }; }; &lsio_gpio3 { @@ -660,16 +673,6 @@ &lsio_gpio4 { "MXM3_291", "MXM3_289", "MXM3_287"; - - /* Enable pcie root / sata ref clock unconditionally */ - pcie-sata-hog { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_sata_refclk>; - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - line-name = "PCIE_SATA_CLK"; - output-high; - }; }; &lsio_gpio5 { @@ -771,9 +774,30 @@ &mu2_m0 { status = "okay"; }; -/* TODO: Apalis PCIE1 */ +/* Apalis PCIE1 */ +&pciea { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + reset-gpio = <&lsio_gpio0 30 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_switch>; +}; -/* TODO: On-module Wi-Fi */ +/* On-module Wi-Fi */ +&pcieb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>; + phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy"; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&phyx2_lpcg { + clocks = <&hsio_refa_clk>, <&hsio_refb_clk>, + <&hsio_refa_clk>, <&hsio_per_clk>; +}; /* TODO: Apalis BKL1_PWM */ @@ -806,8 +830,6 @@ &sai5 { <722534400>, <45158400>, <11289600>, <49152000>; }; -/* TODO: Apalis SATA1 */ - /* Apalis SPDIF1 */ &spdif0 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi index c18f57039f6e..f97feee52c81 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -22,6 +22,10 @@ &fec1 { phy-mode = "rgmii-rxid"; }; +&hsio_refa_clk { + enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_HIGH>; +}; + /* TODO: Apalis HDMI1 */ /* Apalis I2C2 (DDC) */ @@ -188,12 +192,6 @@ &lsio_gpio4 { "MXM3_291", "MXM3_289", "MXM3_287"; - - /* Enable pcie root / sata ref clock unconditionally */ - pcie-sata-hog { - gpios = <27 GPIO_ACTIVE_HIGH>; - }; - }; &lsio_gpio5 { From 06d9879c106f683bd43bc9509ce444b11b863a83 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:23 -0400 Subject: [PATCH 33/71] arm64: dts: imx8: create unified pcie0 and pcie0_ep label for all chips Add unified pcie and pcie_ep label for existed chipes to prepare applied one overay file to enable EP function. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 23 +++++++++++-------- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++-- .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 6 ++--- .../boot/dts/freescale/imx8qxp-ss-hsio.dtsi | 6 +++++ 4 files changed, 24 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi index afbe962d78ce..67c5c6029cd9 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -37,15 +37,18 @@ hsio_phy: phy@5f1a0000 { power-domains = <&pd IMX_SC_R_SERDES_1>; status = "disabled"; }; -}; -&pcieb { - #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; - interrupt-map = <0 0 0 1 &gic 0 47 4>, - <0 0 0 2 &gic 0 48 4>, - <0 0 0 3 &gic 0 49 4>, - <0 0 0 4 &gic 0 50 4>; - interrupt-map-mask = <0 0 0 0x7>; + pcie0: pcie@5f010000 { + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + interrupt-map = <0 0 0 1 &gic 0 47 4>, + <0 0 0 2 &gic 0 48 4>, + <0 0 0 3 &gic 0 49 4>, + <0 0 0 4 &gic 0 50 4>; + interrupt-map-mask = <0 0 0 0x7>; + }; + + pcie0_ep: pcie-ep@5f010000 { + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 75a1d02d39da..50a07c56faff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2153,7 +2153,7 @@ hdmi_tx_phy: phy@32fdff00 { }; }; - pcie: pcie@33800000 { + pcie0: pcie: pcie@33800000 { compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config"; @@ -2191,7 +2191,7 @@ pcie: pcie@33800000 { status = "disabled"; }; - pcie_ep: pcie-ep@33800000 { + pcie0_ep: pcie_ep: pcie-ep@33800000 { compatible = "fsl,imx8mp-pcie-ep"; reg = <0x33800000 0x100000>, <0x18000000 0x8000000>, diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index e80f722dbe65..50c0f6b0f0bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -12,7 +12,7 @@ &hsio_subsys { #address-cells = <1>; #size-cells = <1>; - pciea: pcie@5f000000 { + pcie0: pciea: pcie@5f000000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f000000 0x10000>, <0x4ff00000 0x80000>; @@ -42,7 +42,7 @@ pciea: pcie@5f000000 { status = "disabled"; }; - pciea_ep: pcie-ep@5f000000 { + pcie0_ep: pciea_ep: pcie-ep@5f000000 { compatible = "fsl,imx8q-pcie-ep"; reg = <0x5f000000 0x00010000>, <0x40000000 0x10000000>; @@ -61,7 +61,7 @@ pciea_ep: pcie-ep@5f000000 { status = "disabled"; }; - pcieb: pcie@5f010000 { + pcie1: pcieb: pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi index 47fc6e0cff4a..255b8c91c88c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi @@ -38,4 +38,10 @@ hsio_phy: phy@5f1a0000 { power-domains = <&pd IMX_SC_R_SERDES_1>; status = "disabled"; }; + + pcie0: pcie@5f010000 { + }; + + pcie0_ep: pcie-ep@5f010000 { + }; }; From 6f3287eae412a1bd3919a1085d4b72f13690fc97 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:24 -0400 Subject: [PATCH 34/71] arm64: dts: imx8dxl-ss-hsio: correct irq number for imx8dxl i.MX8DXL use difference irq number for PCIe EP DMA. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi index 67c5c6029cd9..bbc6abb0fdf2 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -50,5 +50,7 @@ pcie0: pcie@5f010000 { }; pcie0_ep: pcie-ep@5f010000 { + interrupts = ; + interrupt-names = "dma"; }; }; From c1c4820b60d7a2ad19c428aa8668c87adb0e6e80 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:25 -0400 Subject: [PATCH 35/71] arm64: dts: imx8dxl-evk: Add pcie0-ep node and use unified pcie0 label Use unified pcie0 label and add pcie0-ep node. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 5f3b4014e152..b6d64d3906ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -642,7 +642,7 @@ &lsio_gpio5 { status = "okay"; }; -&pcieb { +&pcie0 { phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; @@ -652,6 +652,16 @@ &pcieb { status = "okay"; }; +&pcie0_ep{ + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcieb>; + status = "disabled"; +}; + &sai0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai0>; From 1c9b0c6044c22835e2998d270ecca8a636e30294 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:26 -0400 Subject: [PATCH 36/71] arm64: dts: imx8: use common imx-pcie0-ep.dtso to enable PCI ep function Use common imx-pcie0-ep.dtso for imx8mp-evk-pcie-ep and imx8qxp-mek-pcie-ep. No functional change. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 8 +++++-- ...8mp-evk-pcie-ep.dtso => imx-pcie0-ep.dtso} | 6 ++--- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 8 ++++++- .../dts/freescale/imx8qxp-mek-pcie-ep.dtso | 22 ------------------- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 11 +++++++++- 5 files changed, 25 insertions(+), 30 deletions(-) rename arch/arm64/boot/dts/freescale/{imx8mp-evk-pcie-ep.dtso => imx-pcie0-ep.dtso} (64%) delete mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 186101781440..4f50cd5aa0f7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -104,6 +104,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb + +imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb @@ -239,7 +243,7 @@ imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds- imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo -imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo +imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb @@ -286,7 +290,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb -imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx8qxp-mek-pcie-ep.dtbo +imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso similarity index 64% rename from arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso rename to arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso index 244e820699b5..ed73284d9bb6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso +++ b/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso @@ -6,12 +6,10 @@ /dts-v1/; /plugin/; -&pcie { +&pcie0 { status = "disabled"; }; -&pcie_ep { - pinctrl-0 = <&pinctrl_pcie0>; - pinctrl-names = "default"; +&pcie0_ep { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9ab3ee93a35b..1ba3018c621e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -711,7 +711,7 @@ &pcie_phy { status = "okay"; }; -&pcie { +&pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; @@ -719,6 +719,12 @@ &pcie { status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + status = "disabled"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso deleted file mode 100644 index 4f562eb5c5b1..000000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2025 NXP - */ - -#include - -/dts-v1/; -/plugin/; - -&pcieb { - status = "disabled"; -}; - -&pcieb_ep { - phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; - phy-names = "pcie-phy"; - pinctrl-0 = <&pinctrl_pcieb>; - pinctrl-names = "default"; - vpcie-supply = <®_pcieb>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 4ba8ddd47223..c93d123670bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -537,7 +537,7 @@ &mu1_m0 { status = "okay"; }; -&pcieb { +&pcie0 { phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; @@ -547,6 +547,15 @@ &pcieb { status = "okay"; }; +&pcie0_ep { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + vpcie-supply = <®_pcieb>; + status = "disabled"; +}; + &scu_key { status = "okay"; }; From 58bea81052d0bf6e8fc438dda361569b72d3e8f1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:27 -0400 Subject: [PATCH 37/71] arm64: dts: imx95: add pcie1 ep overlay file and create pcie-ep dtb files Create imx95-15x15-evk pcie0-ep and imx95-19x19-evk pcie[0,1]-ep dtb files. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 6 ++++++ arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso | 15 +++++++++++++++ arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 7 +++++++ arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 14 ++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 4f50cd5aa0f7..51a97fd1dd58 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -312,6 +312,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb +imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb +imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo +imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb + imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb diff --git a/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso b/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso new file mode 100644 index 000000000000..0e7ef7ef8560 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; +/plugin/; + +&pcie1 { + status = "disabled"; +}; + +&pcie1_ep { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index aa0b9a4c3688..6c47f4b47356 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -534,6 +534,13 @@ &pcie0 { status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + vpcie-supply = <®_m2_pwr>; + status = "disabled"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index a41d542488ed..6886ea766655 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -426,6 +426,13 @@ &pcie0 { status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + vpcie-supply = <®_pcie0>; + status = "disabled"; +}; + &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; pinctrl-names = "default"; @@ -434,6 +441,13 @@ &pcie1 { status = "okay"; }; +&pcie1_ep { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + vpcie-supply = <®_slot_pwr>; + status = "disabled"; +}; + &sai1 { #sound-dai-cells = <0>; pinctrl-names = "default"; From a705eb167ca4abd62b24540bcde19c592730caee Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:28 -0400 Subject: [PATCH 38/71] arm64: dts: imx8mm-evk: add pcie0-ep node and apply pcie0-ep overlay file Add pcie0-ep node information and apply pcie0-ep overlay file. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 5 +++++ arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 51a97fd1dd58..995f03ed28c9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -116,6 +116,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb + +imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo +imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 5f8336217bb8..622caaa78eaf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -544,6 +544,19 @@ &pcie0 { status = "okay"; }; +&pcie0_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "disabled"; +}; + &sai2 { #sound-dai-cells = <0>; pinctrl-names = "default"; From 627b791541204a365ec64d4609ba3a98ff3aaccb Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:29 -0400 Subject: [PATCH 39/71] arm64: dts: imx8mq: add pcie0-ep node Add pcie0-ep node for i.MX8QM. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 07925b387677..c9040d1131a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1770,6 +1770,41 @@ pcie0: pcie@33800000 { status = "disabled"; }; + pcie0_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33800000 0x100000>, + <0x18000000 0x8000000>, + <0x33900000 0x100000>, + <0x33b00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + linux,pci-domain = <0>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; + num-ib-windows = <4>; + num-ob-windows = <4>; + fsl,max-link-speed = <2>; + status = "disabled"; + }; + pcie1: pcie@33c00000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33c00000 0x400000>, From 6e94adb40a8a24a4cc54459a13b6ca0de8f2fd04 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:30 -0400 Subject: [PATCH 40/71] arm64: dts: imx8mq-evk: add pcie[0,1]-ep nodes Add pcie[0,1]-ep nodes and apply imx-pcie1-ep overlay file. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 +++ arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 995f03ed28c9..90652292a911 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -262,6 +262,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie1-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index a87d0692c3bb..43e45b0bd0d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -377,6 +377,16 @@ &pcie0 { status = "okay"; }; +&pcie0_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&pcie0_refclk>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_AUX>; + status = "disabled"; +}; + &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; @@ -390,6 +400,16 @@ &pcie1 { status = "okay"; }; +&pcie1_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&pcie0_refclk>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + status = "disabled"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; From 95727d056c8f5cad668c1f5711b25102b474216f Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Thu, 17 Apr 2025 14:01:13 +0200 Subject: [PATCH 41/71] arm64: dts: add imx8mp-libra-rdk-fpsc board Add device tree for the Libra-i.MX 8M Plus FPSC board. The Libra is a pure development board and has hardware to support FPSC-24-A.0 set of features. It can be populated with the phyCORE-i.MX 8M Plus SoM to form a SBC. The phyCORE-i.MX 8M Plus FPSC [1] SoM uses only a subset of the hardware features the Libra board provides. The phyCORE-i.MX8MP FPSC itself is a System on Module based on the i.MX 8M Plus SoC utilizing the Future Proof Solder Core [2] standard. To be able to easily map FPSC interface names to SoC interfaces, the FPSC interface names are added as inline comments. Example: &i2c5 { /* FPSC I2C4 */ pinctrl-0 = <&pinctrl_i2c5>; [...] }; Here, I2C4 is the FPSC interface name. The i2c5 instance of the i.MX 8M Plus SoC is used to fulfill the i2c functionality and its signals are routed to the FPSC I2C4 signal pins: pinctrl_i2c5: i2c5grp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 /* I2C4_SDA */ MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 /* I2C4_SCL */ >; }; The features are almost identical to the existing phyCORE-i.MX 8M Plus SoM (dts: imx8mp-phycore-som.dtsi), but the pin muxing is different due to the FPSC standard as well as 1.8V IO voltage instead of 3.3V. [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc/ Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-libra-rdk-fpsc.dts | 290 +++++++ .../dts/freescale/imx8mp-phycore-fpsc.dtsi | 796 ++++++++++++++++++ 3 files changed, 1087 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 90652292a911..4ec67b438e82 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -209,6 +209,7 @@ imx8mp-kontron-dl-dtbs += imx8mp-kontron-bl-osm-s.dtb imx8mp-kontron-dl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts new file mode 100644 index 000000000000..6f3a7b863dca --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; + +#include +#include +#include +#include "imx8mp-phycore-fpsc.dtsi" + +/ { + compatible = "phytec,imx8mp-libra-rdk-fpsc", + "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp"; + model = "PHYTEC i.MX8MP Libra RDK FPSC"; + + backlight_lvds0: backlight0 { + compatible = "pwm-backlight"; + pinctrl-0 = <&pinctrl_lvds0>; + pinctrl-names = "default"; + power-supply = <®_vdd_12v0>; + status = "disabled"; + }; + + chosen { + stdout-path = &uart4; + }; + + panel0_lvds: panel-lvds { + /* compatible panel in overlay */ + backlight = <&backlight_lvds0>; + power-supply = <®_vdd_3v3>; + status = "disabled"; + + port { + panel0_in: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "can1-stby"; + gpio = <&gpio_expander 10 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "can2-stby"; + gpio = <&gpio_expander 9 GPIO_ACTIVE_LOW>; + }; + + reg_vdd_12v0: regulator-vdd-12v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VDD_12V0"; + }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8"; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3"; + }; + + reg_vdd_5v0: regulator-vdd-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VDD_5V0"; + }; +}; + +&eqos { + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; + }; +}; + +/* CAN FD */ +&flexcan1 { + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&flexspi { + status = "okay"; + + spi_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <®_vdd_1v8>; + }; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", "I2C5_SDA", + "GPIO1", "", "", "", "SPI1_CS", + "", "", "", "SPI2_CS", "I2C1_SCL", + "I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA", + "", "GPIO2", "", "LVDS1_BL_EN", "SPI3_CS", + "", "GPIO3"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + vcc-supply = <®_vdd_1v8>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-1 { + type = ; + }; + + led-2 { + type = ; + }; + + led-3 { + type = ; + }; + }; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3", + "CSI1_CTRL4", "CSI2_CTRL1", "CSI2_CTRL2", + "CSI2_CTRL3", "CSI2_CTRL4", "CLK_EN_AV", + "nCAN2_EN", "nCAN1_EN", "PCIE1_nWAKE", + "PCIE2_nWAKE", "PCIE2_nALERT_3V3", + "UART1_BT_RS_SEL", "UART1_RS232_485_SEL"; + vcc-supply = <®_vdd_1v8>; + + uart1_bt_rs_sel: bt-rs-hog { + gpios = <14 GPIO_ACTIVE_HIGH>; + gpio-hog; + line-name = "UART1_BT_RS_SEL"; + output-low; /* default RS232/RS485 */ + }; + + uart1_rs232_485_sel: rs232-485-hog { + gpios = <15 GPIO_ACTIVE_HIGH>; + gpio-hog; + line-name = "UART1_RS232_485_SEL"; + output-high; /* default RS232 */ + }; + }; +}; + +&iomuxc { + pinctrl_lvds0: lvds0grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x12 + >; + }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1C0 + >; + }; +}; + +&lvds_bridge { + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +/* Mini PCIe */ +&pcie { + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_vdd_3v3>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +®_vdd_io { + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; +}; + +&rv3028 { + interrupt-parent = <&gpio5>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + aux-voltage-chargeable = <1>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; + trickle-resistor-ohms = <3000>; + wakeup-source; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* debug console */ +&uart4 { + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + disable-wp; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi new file mode 100644 index 000000000000..8b0e8cf86cad --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi @@ -0,0 +1,796 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include "imx8mp.dtsi" + +/ { + compatible = "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp"; + model = "PHYTEC phyCORE-i.MX8MP FPSC"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x80000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDDSW_SD2"; + startup-delay-us = <100>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_io: regulator-vdd-io { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_IO"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { /* FPSC SPI1 */ + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; +}; + +&ecspi2 { /* FPSC SPI2 */ + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; +}; + +&ecspi3 { /* FPSC SPI3 */ + pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-names = "default"; +}; + +&eqos { /* FPSC RGMII2 */ + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-names = "default"; +}; + +&fec { /* FPSC GB_ETH1 */ + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-names = "default"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; + }; +}; + +&flexcan1 { /* FPSC CAN1 */ + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default"; +}; + +&flexcan2 { /* FPSC CAN2 */ + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; +}; + +&flexspi { /* FPSC QSPI */ + pinctrl-0 = <&pinctrl_flexspi>; + pinctrl-names = "default"; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", "", + "", "", "", "PCIE1_nPERST"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "SD2_RESET_B"; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "I2C6_SCL", + "I2C6_SDA", "I2C5_SCL"; +}; + +&gpio4 { /* FPSC GPIO */ + gpio-line-names = "GPIO6", "RGMII2_nINT", "GPIO7", "GPIO4", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "X_PMIC_IRQ_B", "", + "", "GPIO5", "", "", "RGMII2_EVENT_OUT", + "", "", "RGMII2_EVENT_IN"; + pinctrl-0 = <&pinctrl_gpio4>; + pinctrl-names = "default"; +}; + +&gpio5 { /* FPSC GPIO */ + gpio-line-names = "", "", "", "", "I2C5_SDA", + "GPIO1", "", "", "", "SPI1_CS", + "", "", "", "SPI2_CS", "I2C1_SCL", + "I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA", + "", "GPIO2", "", "", "SPI3_CS", + "", "GPIO3"; + pinctrl-0 = <&pinctrl_gpio5>; + pinctrl-names = "default"; +}; + +&i2c1 { /* FPSC I2C1 */ + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + + regulators { + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <850000>; + regulator-name = "VDD_SOC (BUCK1)"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <850000>; + regulator-name = "VDD_ARM (BUCK2)"; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3 (BUCK4)"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8 (BUCK5)"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SNVS_1V8 (LDO1)"; + }; + + ldo3: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDDA_1V8 (LDO3)"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO5)"; + }; + }; + }; + + /* User EEPROM */ + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_vdd_io>; + }; + + /* factory EEPROM */ + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + read-only; + vcc-supply = <®_vdd_io>; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&i2c2 { /* FPSC I2C2 */ + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c3 { /* FPSC I2C3 */ + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c5 { /* FPSC I2C4 */ + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c6 { /* FPSC I2C5 */ + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&iomuxc { + pinctrl_flexcan1: can1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 /* CAN1_TX */ + MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 /* CAN1_RX */ + >; + }; + + pinctrl_flexcan2: can2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 /* CAN2_TX */ + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 /* CAN2_RX */ + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* RGMII2_nINT */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10 /* RGMII2_EVENT_IN */ + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x10 /* RGMII2_EVENT_OUT */ + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 /* RGMII2_MDIO */ + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 /* RGMII2_MDC */ + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 /* RGMII2_TX_D3 */ + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 /* RGMII2_TX_D2 */ + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 /* RGMII2_TX_D1 */ + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 /* RGMII2_TX_D0 */ + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 /* RGMII2_TX_CTL */ + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 /* RGMII2_TXC */ + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 /* RGMII2_RX_D3 */ + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 /* RGMII2_RX_D2 */ + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 /* RGMII2_RX_D1 */ + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 /* RGMII2_RX_D0 */ + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 /* RGMII2_RX_CTL */ + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 /* RGMII2_RXC */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 /* QSPI_CE */ + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 /* QSPI_CLK */ + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 /* QSPI_DATA_0 */ + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 /* QSPI_DATA_1 */ + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 /* QSPI_DATA_2 */ + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 /* QSPI_DATA_3 */ + MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82 /* QSPI_DQS */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* GPIO4 */ + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 /* GPIO5 */ + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x106 /* GPIO6 */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x106 /* GPIO7 */ + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x106 /* GPIO1 */ + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x106 /* GPIO2 */ + MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x106 /* GPIO3 */ + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x106 /* HDMI_CEC */ + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x106 /* HDMI_SCL */ + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x106 /* HDMI_SDA */ + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x106 /* HDMI_HPD */ + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 /* I2C1_SDA_DNU */ + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 /* I2C1_SCL_DNU */ + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 /* I2C2_SDA */ + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 /* I2C2_SCL */ + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2 + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 /* I2C3_SDA */ + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 /* I2C3_SCL */ + >; + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 /* I2C4_SDA */ + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 /* I2C4_SCL */ + >; + }; + + pinctrl_i2c6_gpio: i2c6gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x1e2 + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x1e2 + >; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c2 /* I2C5_SDA */ + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c2 /* I2C5_SCL */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x10 /* PCIE1_nCLKREQ */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* PCIE1_nPERST */ + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x106 /* PWM1 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x106 /* PWM2 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x106 /* PWM3 */ + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x106 /* PWM4 */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x106 /* SAI1_MCLK */ + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x106 /* SAI1_RX_SYNC */ + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x106 /* SAI1_RX_BCLK */ + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x106 /* SAI1_RX_DATA */ + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x106 /* SAI1_TX_SYNC */ + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x106 /* SAI1_TX_BCLK */ + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x106 /* SAI1_TX_DATA */ + >; + }; + + pinctrl_ecspi1: spi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 /* SPI1_SCLK */ + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 /* SPI1_MOSI */ + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 /* SPI1_MISO */ + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x106 /* SPI1_CS */ + >; + }; + + pinctrl_ecspi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 /* SPI2_SCLK */ + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 /* SPI2_MOSI */ + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 /* SPI2_MISO */ + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x106 /* SPI2_CS */ + >; + }; + + pinctrl_ecspi3: spi3grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x82 /* SPI3_SCLK */ + MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x82 /* SPI3_MOSI */ + MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x82 /* SPI3_MISO */ + MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x106 /* SPI3_CS */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x140 /* UART2_RXD */ + MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x140 /* UART2_TXD */ + MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x140 /* UART2_RTS */ + MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x140 /* UART2_CTS */ + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x140 /* UART1_RXD */ + MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x140 /* UART1_TXD */ + MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x140 /* UART1_RTS */ + MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x140 /* UART1_CTS */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 /* UART3_RXD */ + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 /* UART3_TXD */ + >; + }; + + pinctrl_usb0: usb0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x106 /* USB1_PWR_EN */ + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x106 /* USB1_OC */ + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x106 /* USB1_ID */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x106 /* USB2_PWR_EN */ + MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x106 /* USB2_OC */ + MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x106 /* USB2_ID */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x106 /* SDIO_WP */ + MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x106 /* SDIO_CD */ + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x106 /* SDIO_CLK */ + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x106 /* SDIO_CLK */ + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x106 /* SDIO_DATA0 */ + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x106 /* SDIO_DATA1 */ + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x106 /* SDIO_DATA2 */ + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x106 /* SDIO_DATA3 */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ + MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 /* SDCARD_CLK */ + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 /* SDCARD_CMD */ + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDCARD_DATA0 */ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDCARD_DATA1 */ + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDCARD_DATA2 */ + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDCARD_DATA3 */ + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ + MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 /* SDCARD_CLK */ + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 /* SDCARD_CMD */ + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDCARD_DATA0 */ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDCARD_DATA1 */ + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDCARD_DATA2 */ + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDCARD_DATA3 */ + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ + MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 /* SDCARD_CLK */ + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 /* SDCARD_CMD */ + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDCARD_DATA0 */ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDCARD_DATA1 */ + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDCARD_DATA2 */ + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDCARD_DATA3 */ + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 + >; + }; +}; + +&pcie { /* FPSC PCIE1 */ + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; +}; + +&pwm1 { /* FPSC PWM1 */ + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; +}; + +&pwm2 { /* FPSC PWM2 */ + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; +}; + +&pwm3 { /* FPSC PWM3 */ + pinctrl-0 = <&pinctrl_pwm3>; + pinctrl-names = "default"; +}; + +&pwm4 { /* FPSC PWM4 */ + pinctrl-0 = <&pinctrl_pwm4>; + pinctrl-names = "default"; +}; + +&sai5 { /* FPSC SAI1 */ + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-names = "default"; +}; + +&uart2 { /* FPSC UART2 */ + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + fsl,dte-mode; +}; + +&uart3 { /* FPSC UART1 */ + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + fsl,dte-mode; +}; + +&uart4 { /* FPSC UART3 */ + pinctrl-0 = <&pinctrl_uart4>; + pinctrl-names = "default"; +}; + +&usb3_0 { /* FPSC USB1 */ + pinctrl-0 = <&pinctrl_usb0>; + pinctrl-names = "default"; +}; + +&usb3_1 { /* FPSC USB2 */ + pinctrl-0 = <&pinctrl_usb1>; + pinctrl-names = "default"; +}; + +&usdhc1 { /* FPSC SDIO */ + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; +}; + +&usdhc2 { /* FPSC SDCARD */ + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + sd-uhs-sdr104; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <&ldo5>; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&pinctrl_wdog>; + pinctrl-names = "default"; + fsl,ext-reset-output; + status = "okay"; +}; From 2b743164ecfe906803f5632243549f897350f51e Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Thu, 17 Apr 2025 14:01:14 +0200 Subject: [PATCH 42/71] arm64: dts: add imx8mp-libra-rdk-fpsc LVDS panel overlay The Libra board has an LVDS connector. Add an overlay for an etml1010g3dra LVDS panel supported for the phyCORE-i.MX 8M Plus that may be connected to it. Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + ...8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso | 44 +++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 4ec67b438e82..d63000efdf27 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -210,6 +210,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb +imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso new file mode 100644 index 000000000000..1dcf249ca90d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + pwms = <&pwm1 0 66667 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates = <0>, <506800000>; + status = "okay"; +}; + +&panel0_lvds { + compatible = "edt,etml1010g3dra"; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; From 98363ac3664001ed3990478ba09e87bd1820a892 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:30 +0200 Subject: [PATCH 43/71] arm64: dts: freescale: imx93-phycore-som: Add PMIC support PMIC driver for PCA9451A used on phyCORE-i.MX93 SOM is available since commit 5edeb7d31262 ("regulator: pca9450: add pca9451a support"). Add support for it in the SOM device-tree. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-phycore-som.dtsi | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 88c2657b50e6..507a71f9294b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -72,6 +72,90 @@ ethphy1: ethernet-phy@1 { }; }; +/* I2C3 */ +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3_BUCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "VDD_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "PMIC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + /* eMMC */ &usdhc1 { pinctrl-names = "default"; @@ -108,6 +192,19 @@ MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e >; }; + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e From 31ff2efe6484000f103d5df0f32a4cb3a1dee06d Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:31 +0200 Subject: [PATCH 44/71] arm64: dts: freescale: imx93-phycore-som: Add EEPROM support Add support for the EEPROM chip available on I2C3 bus (address 0x50), used for the PHYTEC SOM detection. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 507a71f9294b..0528e293c03d 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -154,6 +154,14 @@ ldo5: LDO5 { }; }; }; + + /* EEPROM */ + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&buck4>; + }; }; /* eMMC */ From d6241ba41f2c676b3f5a01497d99e5acb6ca2aef Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:32 +0200 Subject: [PATCH 45/71] arm64: dts: freescale: imx93-phycore-som: Disable LED pull-up There is already an external pull-down resistor on the LED output line. It makes no sense to have both pull-down and pull-up resistors enabled at the same time. Thus disable the internal pull-up. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 0528e293c03d..06a9e674e338 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -196,7 +196,7 @@ MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e pinctrl_leds: ledsgrp { fsl,pins = < - MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x11e >; }; From 54be09bdb1e7b6291eb9b99c5b60fc5026576bd1 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:33 +0200 Subject: [PATCH 46/71] arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrl Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl modes. This enables to use eMMC at enhanced data rates (e.g. HS400). While at it, apply a workaround for the i.MX93 chip errata ERR052021. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++---- 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 06a9e674e338..663530a7e2bb 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -166,8 +166,10 @@ eeprom@50 { /* eMMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; @@ -213,18 +215,53 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e >; }; From 9ed135ca48391848766f61a37580737dcd86524f Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:34 +0200 Subject: [PATCH 47/71] arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by default The phyCORE-i.MX93 SoM comes in two variants, one with VDD_IO set to 3.3V and the other variant to 1.8V. The 3.3V variant can only support DDR52 mode, while 1.8V variant is capable of HS400ES eMMC mode. The information about VDD_IO option is encoded in the SoM's EEPROM. EEPROM is read in the bootloader and bootloader clears the "no-1-8-v" flag in case of 1.8V SoM variant is detected. Thus add property 'no-1-8-v' by default to usdhc1 (eMMC) node and let bootloader handle the flag. In case EEPROM is erased or read-out fails, flag "no-1-8-v" also ensures fall-back compatibility with both SoM variants. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 663530a7e2bb..22dbcc89e311 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -172,6 +172,7 @@ &usdhc1 { pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; + no-1-8-v; status = "okay"; }; From bdd3071e10926847f4985056a0d80be88fc7cfd4 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:35 +0200 Subject: [PATCH 48/71] arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag Drop redundant 'no-1-8-v' flag from usdhc1 (eMMC) node. Flag is now set by default in the SOM include file (imx93-phycore-som.dtsi). Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 85fb188b057f..902b523fc92c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -40,11 +40,6 @@ &lpuart1 { status = "okay"; }; -/* eMMC */ -&usdhc1 { - no-1-8-v; -}; - /* SD-Card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; From 99cf1026b7af5fa347aafd273f44494f52b0877c Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:36 +0200 Subject: [PATCH 49/71] arm64: dts: freescale: imx93-phyboard-segin: Disable SD-card write-protect Add disable-wp flag (write-protect) to usdhc2 node (SD-card) to get rid of the following kernel boot warning: host does not support reading read-only switch, assuming write-enable Micro SD cards can't be physically write-protected like full-sized cards anyways. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 902b523fc92c..3d5cd0561362 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -48,6 +48,7 @@ &usdhc2 { pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; bus-width = <4>; cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + disable-wp; no-mmc; no-sdio; vmmc-supply = <®_usdhc2_vmmc>; From ff44686256ffb16a3bdb0c7600556d26ea7e0328 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:37 +0200 Subject: [PATCH 50/71] arm64: dts: freescale: imx93-phyboard-segin: Fix SD-card pinctrl Until now, all usdhc2 (SD-card) pinctrl labels pointed to one pinctrl group "usdhc2grp" which was overwritten twice by the 100 and 200 MHz modes. Fix this by using unique pinctrl names. Additionally, adjust MX93_PAD_SD2_CLK__USDHC2_CLK pad drive-strength according to values obtained by measurements from the PHYTEC hardware department to improve signal integrity. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 3d5cd0561362..541297052b62 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -77,7 +77,7 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e pinctrl_usdhc2_default: usdhc2grp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e @@ -87,9 +87,9 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; - pinctrl_usdhc2_100mhz: usdhc2grp { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e @@ -99,9 +99,9 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; - pinctrl_usdhc2_200mhz: usdhc2grp { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e From d84fc1fc8e5e53afd95823bbc8450bb50ebec4a4 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:38 +0200 Subject: [PATCH 51/71] arm64: dts: freescale: imx93-phyboard-segin: Set CMD/DATA SION bit to fix ERR052021 Implement fix for i.MX 93 silicon errata ERR052021. ERR052021 uSDHC: Sometimes uSDHC does not work under VDD_SOC low drive mode and nominal mode Description: uSDHC PADs have one integration issue. When CMD/DATA lines direction change from output to input, uSDHC controller begin sampling, the integration issue will make input enable signal from uSDHC propagated to the PAD with a long delay, thus the new input value on the pad comes to uSDHC lately. The uSDHC sampled the old input value and the sampling result is wrong. Workaround: Set uSDHC CMD/DATA PADs iomux register SION bit to 1, then PADs will propagate input to uSDHC with no delay, so correct value is sampled. This issue will wrongly trigger the start bit when sample the USDHC command response, cause the USDHC trigger command CRC/index/endbit error, which will finally impact the tuning pass window, especially will impact the standard tuning logic, and can't find a correct delay cell to get the best timing. Based on commit bb89601282fc ("arm64: dts: imx93-11x11-evk: set SION for cmd and data pad of USDHC"). Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-phyboard-segin.dts | 37 ++++++++++--------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 541297052b62..525f52789f8b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -75,39 +75,42 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_default: usdhc2grp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; }; From 1a69251c26c851fe8be83c6a63100439a8dfc9ce Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:39 +0200 Subject: [PATCH 52/71] arm64: dts: freescale: imx93-phyboard-segin: Add RTC support Add support for RTC connected via I2C on phyBOARD-Segin-i.MX93. Set default RTC by configuring the aliases. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-phyboard-segin.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 525f52789f8b..38b89398e646 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -17,6 +17,11 @@ /{ compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", "fsl,imx93"; + aliases { + rtc0 = &i2c_rtc; + rtc1 = &bbnsm_rtc; + }; + chosen { stdout-path = &lpuart1; }; @@ -33,6 +38,24 @@ reg_usdhc2_vmmc: regulator-usdhc2 { }; }; +/* I2C2 */ +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + /* RTC */ + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + /* Console */ &lpuart1 { pinctrl-names = "default"; @@ -56,6 +79,13 @@ &usdhc2 { }; &iomuxc { + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e @@ -69,6 +99,12 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e + >; + }; + pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = < MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e From 0a8275f31f34cde151a03c3d6c812696303443f7 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:40 +0200 Subject: [PATCH 53/71] arm64: dts: freescale: imx93-phyboard-segin: Add CAN support Add support for CAN networking on phyBOARD-Segin-i.MX93 via the flexcan1 interface. The CAN PHY chip SN65HVD234D used on the board is compatible with the TCAN1043 driver using the generic "can-transceiver-phy" and is capable of up to 1Mbps data rate. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-phyboard-segin.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 38b89398e646..be9c0a436734 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -26,6 +26,15 @@ chosen { stdout-path = &lpuart1; }; + flexcan1_tc: can-phy0 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_tc>; + enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; enable-active-high; @@ -38,6 +47,14 @@ reg_usdhc2_vmmc: regulator-usdhc2 { }; }; +/* CAN */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + phys = <&flexcan1_tc>; + status = "okay"; +}; + /* I2C2 */ &lpi2c2 { clock-frequency = <400000>; @@ -79,6 +96,19 @@ &usdhc2 { }; &iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + >; + }; + + pinctrl_flexcan1_tc: flexcan1tcgrp { + fsl,pins = < + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e + >; + }; + pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e From b7fed5065b65306f4d747f77ea1366c60c4194d6 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:41 +0200 Subject: [PATCH 54/71] arm64: dts: freescale: imx93-phyboard-segin: Add USB support Add support for both USB controllers. Set first controller in OTG mode (USB micro-AB connector X8) and the second one in host mode (USB type A connector X7) by default. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-phyboard-segin.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index be9c0a436734..e4f959f665b2 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -80,6 +80,19 @@ &lpuart1 { status = "okay"; }; +/* USB */ +&usbotg1 { + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + /* SD-Card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; From c3f6c388d30e5cb62eae2203363f50d9e2a7eabd Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:42 +0200 Subject: [PATCH 55/71] arm64: dts: freescale: imx93-phyboard-segin: Add I2S audio Add support for I2S audio found on phyBOARD-Segin-i.MX93. Audio codec TLV320AIC3007 is connected to SAI1 interface as a DAI master. MCLK is provided from the SAI's internal audio PLL (19.2 MHz). Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-phyboard-segin.dts | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index e4f959f665b2..54e084e69706 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -35,6 +35,20 @@ flexcan1_tc: can-phy0 { enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; }; + reg_sound_1v8: regulator-sound-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC1V8_AUDIO"; + }; + + reg_sound_3v3: regulator-sound-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC3V3_ANALOG"; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; enable-active-high; @@ -45,6 +59,34 @@ reg_usdhc2_vmmc: regulator-usdhc2 { regulator-max-microvolt = <3300000>; regulator-name = "VCC_SD"; }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + clocks = <&clk IMX93_CLK_SAI1>; + }; + }; }; /* CAN */ @@ -62,6 +104,17 @@ &lpi2c2 { pinctrl-0 = <&pinctrl_lpi2c2>; status = "okay"; + /* Codec */ + audio_codec: audio-codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + }; + /* RTC */ i2c_rtc: rtc@68 { compatible = "microcrystal,rv4162"; @@ -80,6 +133,17 @@ &lpuart1 { status = "okay"; }; +/* Audio */ +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <19200000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + /* USB */ &usbotg1 { disable-over-current; @@ -148,6 +212,16 @@ MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_UART2_RXD__SAI1_MCLK 0x1202 + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x1402 + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x1402 + >; + }; + pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = < MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e From 7c4424dd11e4d4ed82f3ede5bac312e0fbc506ae Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:43 +0200 Subject: [PATCH 56/71] arm64: dts: freescale: imx93-phyboard-segin: Add EQOS Ethernet Add support for the carrier-board Micrel KSZ8081 Ethernet PHY. This is a 10/100Mbit PHY connected to the EQOS interface and shares MDIO bus with the Ethernet PHY located on the SoM (FEC interface). Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-phyboard-segin.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 54e084e69706..c62cc06fad4b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -89,6 +89,28 @@ dailink_master: simple-audio-card,codec { }; }; +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-id0022.1561"; + reg = <2>; + clocks = <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "rmii-ref"; + micrel,led-mode = <1>; + }; +}; + /* CAN */ &flexcan1 { pinctrl-names = "default"; @@ -173,6 +195,19 @@ &usdhc2 { }; &iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000050e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x50e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e + MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e From 265bf4ccd703435444c83da74d748a0268be2022 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:44 +0200 Subject: [PATCH 57/71] arm64: dts: freescale: imx93-phyboard-segin: Order node alphabetically Move pinctrl_uart1 to keep nodes in alphabetical order. No functional changes. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-phyboard-segin.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index c62cc06fad4b..0c55b749c834 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -228,13 +228,6 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e >; }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x30e - >; - }; - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e @@ -257,6 +250,13 @@ MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x1402 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = < MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e From a504243058747fd02c58b17191546e346a64a604 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Tue, 22 Apr 2025 13:50:49 +0200 Subject: [PATCH 58/71] arm64: dts: imx8-colibri: Add PCIe support The needed drivers to support PCIe for i.MX 8QXP have been added. Configure PCIe for the Colibri iMX8X SoM. The pcieb block is connected to the on module Wi-Fi/BT module. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8x-colibri.dtsi | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index ecb35c6b67f5..e602d147e39b 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -52,6 +52,15 @@ reg_module_vref_1v8: regulator-module-vref-1v8 { regulator-name = "vref-1v8"; }; + reg_module_wifi: regulator-module-wifi { + compatible = "regulator-fixed"; + gpio = <&gpio_expander_43 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-name = "Wi-Fi_PDn"; + startup-delay-us = <2000>; + }; + reg_usbh_vbus: regulator-usbh-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -261,6 +270,16 @@ ethphy0: ethernet-phy@2 { }; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + +&hsio_refb_clk { + enable-gpios = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>; +}; + /* Colibri SPI */ &lpspi2 { pinctrl-names = "default"; @@ -454,7 +473,15 @@ &mu1_m0 { /* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */ -/* TODO on-module PCIe for Wi-Fi */ +/* On-module PCIe for Wi-Fi */ +&pcieb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; /* On-module I2S */ &sai0 { From b0d011d4841bc00de3f559b3bc8be2de11044597 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 21 Apr 2025 14:51:38 +0800 Subject: [PATCH 59/71] arm64: dts: freescale: Add basic dtsi for imx943 Add the minimal dtsi support for i.MX943. i.MX943 is the first SoC of i.MX94 Family, create a common dtsi for the whole i.MX94 family, and the specific dtsi part for i.MX943. The clock, power domain and perf index need to be used by the device nodes for resource reference, add them along with the dtsi support. Signed-off-by: Jacky Bai Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx94-clock.h | 193 ++ arch/arm64/boot/dts/freescale/imx94-pinfunc.h | 1570 +++++++++++++++++ arch/arm64/boot/dts/freescale/imx94-power.h | 41 + arch/arm64/boot/dts/freescale/imx94.dtsi | 1148 ++++++++++++ arch/arm64/boot/dts/freescale/imx943.dtsi | 148 ++ 5 files changed, 3100 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx94-clock.h create mode 100644 arch/arm64/boot/dts/freescale/imx94-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx94-power.h create mode 100644 arch/arm64/boot/dts/freescale/imx94.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx943.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx94-clock.h b/arch/arm64/boot/dts/freescale/imx94-clock.h new file mode 100644 index 000000000000..27e8c0839722 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx94-clock.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2024-2025 NXP + */ + +#ifndef __IMX94_CLOCK_H +#define __IMX94_CLOCK_H + +#define IMX94_CLK_EXT 0 +#define IMX94_CLK_32K 1 +#define IMX94_CLK_24M 2 +#define IMX94_CLK_FRO 3 +#define IMX94_CLK_SYSPLL1_VCO 4 +#define IMX94_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX94_CLK_SYSPLL1_PFD0 6 +#define IMX94_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX94_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX94_CLK_SYSPLL1_PFD1 9 +#define IMX94_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX94_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX94_CLK_SYSPLL1_PFD2 12 +#define IMX94_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX94_CLK_AUDIOPLL1_VCO 14 +#define IMX94_CLK_AUDIOPLL1 15 +#define IMX94_CLK_AUDIOPLL2_VCO 16 +#define IMX94_CLK_AUDIOPLL2 17 +#define IMX94_CLK_RESERVED18 18 +#define IMX94_CLK_RESERVED19 19 +#define IMX94_CLK_RESERVED20 20 +#define IMX94_CLK_RESERVED21 21 +#define IMX94_CLK_RESERVED22 22 +#define IMX94_CLK_RESERVED23 23 +#define IMX94_CLK_ENCPLL_VCO 24 +#define IMX94_CLK_ENCPLL_PFD0_UNGATED 25 +#define IMX94_CLK_ENCPLL_PFD0 26 +#define IMX94_CLK_ENCPLL_PFD1_UNGATED 27 +#define IMX94_CLK_ENCPLL_PFD1 28 +#define IMX94_CLK_ARMPLL_VCO 29 +#define IMX94_CLK_ARMPLL_PFD0_UNGATED 30 +#define IMX94_CLK_ARMPLL_PFD0 31 +#define IMX94_CLK_ARMPLL_PFD1_UNGATED 32 +#define IMX94_CLK_ARMPLL_PFD1 33 +#define IMX94_CLK_ARMPLL_PFD2_UNGATED 34 +#define IMX94_CLK_ARMPLL_PFD2 35 +#define IMX94_CLK_ARMPLL_PFD3_UNGATED 36 +#define IMX94_CLK_ARMPLL_PFD3 37 +#define IMX94_CLK_DRAMPLL_VCO 38 +#define IMX94_CLK_DRAMPLL 39 +#define IMX94_CLK_HSIOPLL_VCO 40 +#define IMX94_CLK_HSIOPLL 41 +#define IMX94_CLK_LDBPLL_VCO 42 +#define IMX94_CLK_LDBPLL 43 +#define IMX94_CLK_EXT1 44 +#define IMX94_CLK_EXT2 45 +#define IMX94_CLK_ADC 46 +#define IMX94_CLK_BUSAON 47 +#define IMX94_CLK_CAN1 48 +#define IMX94_CLK_GLITCHFILTER 49 +#define IMX94_CLK_GPT1 50 +#define IMX94_CLK_I3C1SLOW 51 +#define IMX94_CLK_LPI2C1 52 +#define IMX94_CLK_LPI2C2 53 +#define IMX94_CLK_LPSPI1 54 +#define IMX94_CLK_LPSPI2 55 +#define IMX94_CLK_LPTMR1 56 +#define IMX94_CLK_LPUART1 57 +#define IMX94_CLK_LPUART2 58 +#define IMX94_CLK_M33 59 +#define IMX94_CLK_M33SYSTICK 60 +#define IMX94_CLK_PDM 61 +#define IMX94_CLK_SAI1 62 +#define IMX94_CLK_TPM2 63 +#define IMX94_CLK_A55 64 +#define IMX94_CLK_A55MTRBUS 65 +#define IMX94_CLK_A55PERIPH 66 +#define IMX94_CLK_DRAMALT 67 +#define IMX94_CLK_DRAMAPB 68 +#define IMX94_CLK_DISPAPB 69 +#define IMX94_CLK_DISPAXI 70 +#define IMX94_CLK_DISPPIX 71 +#define IMX94_CLK_HSIOACSCAN480M 72 +#define IMX94_CLK_HSIOACSCAN80M 73 +#define IMX94_CLK_HSIO 74 +#define IMX94_CLK_HSIOPCIEAUX 75 +#define IMX94_CLK_HSIOPCIETEST160M 76 +#define IMX94_CLK_HSIOPCIETEST400M 77 +#define IMX94_CLK_HSIOPCIETEST500M 78 +#define IMX94_CLK_HSIOPCIETEST50M 79 +#define IMX94_CLK_HSIOUSBTEST60M 80 +#define IMX94_CLK_BUSM70 81 +#define IMX94_CLK_M70 82 +#define IMX94_CLK_M70SYSTICK 83 +#define IMX94_CLK_BUSM71 84 +#define IMX94_CLK_M71 85 +#define IMX94_CLK_M71SYSTICK 86 +#define IMX94_CLK_BUSNETCMIX 87 +#define IMX94_CLK_ECAT 88 +#define IMX94_CLK_ENET 89 +#define IMX94_CLK_ENETPHYTEST200M 90 +#define IMX94_CLK_ENETPHYTEST500M 91 +#define IMX94_CLK_ENETPHYTEST667M 92 +#define IMX94_CLK_ENETREF 93 +#define IMX94_CLK_ENETTIMER1 94 +#define IMX94_CLK_ENETTIMER2 95 +#define IMX94_CLK_ENETTIMER3 96 +#define IMX94_CLK_FLEXIO3 97 +#define IMX94_CLK_FLEXIO4 98 +#define IMX94_CLK_M33SYNC 99 +#define IMX94_CLK_M33SYNCSYSTICK 100 +#define IMX94_CLK_MAC0 101 +#define IMX94_CLK_MAC1 102 +#define IMX94_CLK_MAC2 103 +#define IMX94_CLK_MAC3 104 +#define IMX94_CLK_MAC4 105 +#define IMX94_CLK_MAC5 106 +#define IMX94_CLK_NOCAPB 107 +#define IMX94_CLK_NOC 108 +#define IMX94_CLK_NPUAPB 109 +#define IMX94_CLK_NPU 110 +#define IMX94_CLK_CCMCKO1 111 +#define IMX94_CLK_CCMCKO2 112 +#define IMX94_CLK_CCMCKO3 113 +#define IMX94_CLK_CCMCKO4 114 +#define IMX94_CLK_BISS 115 +#define IMX94_CLK_BUSWAKEUP 116 +#define IMX94_CLK_CAN2 117 +#define IMX94_CLK_CAN3 118 +#define IMX94_CLK_CAN4 119 +#define IMX94_CLK_CAN5 120 +#define IMX94_CLK_ENDAT21 121 +#define IMX94_CLK_ENDAT22 122 +#define IMX94_CLK_ENDAT31FAST 123 +#define IMX94_CLK_ENDAT31SLOW 124 +#define IMX94_CLK_FLEXIO1 125 +#define IMX94_CLK_FLEXIO2 126 +#define IMX94_CLK_GPT2 127 +#define IMX94_CLK_GPT3 128 +#define IMX94_CLK_GPT4 129 +#define IMX94_CLK_HIPERFACE1 130 +#define IMX94_CLK_HIPERFACE1SYNC 131 +#define IMX94_CLK_HIPERFACE2 132 +#define IMX94_CLK_HIPERFACE2SYNC 133 +#define IMX94_CLK_I3C2SLOW 134 +#define IMX94_CLK_LPI2C3 135 +#define IMX94_CLK_LPI2C4 136 +#define IMX94_CLK_LPI2C5 137 +#define IMX94_CLK_LPI2C6 138 +#define IMX94_CLK_LPI2C7 139 +#define IMX94_CLK_LPI2C8 140 +#define IMX94_CLK_LPSPI3 141 +#define IMX94_CLK_LPSPI4 142 +#define IMX94_CLK_LPSPI5 143 +#define IMX94_CLK_LPSPI6 144 +#define IMX94_CLK_LPSPI7 145 +#define IMX94_CLK_LPSPI8 146 +#define IMX94_CLK_LPTMR2 147 +#define IMX94_CLK_LPUART10 148 +#define IMX94_CLK_LPUART11 149 +#define IMX94_CLK_LPUART12 150 +#define IMX94_CLK_LPUART3 151 +#define IMX94_CLK_LPUART4 152 +#define IMX94_CLK_LPUART5 153 +#define IMX94_CLK_LPUART6 154 +#define IMX94_CLK_LPUART7 155 +#define IMX94_CLK_LPUART8 156 +#define IMX94_CLK_LPUART9 157 +#define IMX94_CLK_SAI2 158 +#define IMX94_CLK_SAI3 159 +#define IMX94_CLK_SAI4 160 +#define IMX94_CLK_SWOTRACE 161 +#define IMX94_CLK_TPM4 162 +#define IMX94_CLK_TPM5 163 +#define IMX94_CLK_TPM6 164 +#define IMX94_CLK_USBPHYBURUNIN 165 +#define IMX94_CLK_USDHC1 166 +#define IMX94_CLK_USDHC2 167 +#define IMX94_CLK_USDHC3 168 +#define IMX94_CLK_V2XPK 169 +#define IMX94_CLK_WAKEUPAXI 170 +#define IMX94_CLK_XSPISLVROOT 171 +#define IMX94_CLK_XSPI1 172 +#define IMX94_CLK_XSPI2 173 +#define IMX94_CLK_SEL_EXT 174 +#define IMX94_CLK_SEL_A55C0 175 +#define IMX94_CLK_SEL_A55C1 176 +#define IMX94_CLK_SEL_A55C2 177 +#define IMX94_CLK_SEL_A55C3 178 +#define IMX94_CLK_SEL_A55P 179 +#define IMX94_CLK_SEL_DRAM 180 +#define IMX94_CLK_SEL_TEMPSENSE 181 +#define IMX94_CLK_NPU_CGC 182 + +#endif /* __IMX94_CLOCK_H */ diff --git a/arch/arm64/boot/dts/freescale/imx94-pinfunc.h b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h new file mode 100644 index 000000000000..00255db89185 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h @@ -0,0 +1,1570 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2024-2025 NXP + */ + +#ifndef __DTS_IMX94_PINFUNC_H +#define __DTS_IMX94_PINFUNC_H + +/* Drive Strength */ +#define IMX94_DSE_X1 0x2 +#define IMX94_DSE_X2 0x6 +#define IMX94_DSE_X3 0xe +#define IMX94_DSE_X4 0x1e +#define IMX94_DSE_X5 0x3e +#define IMX94_DSE_X6 0x7e + +/* Slew Rate */ +#define IMX94_FSEL_FAST 0x180 +#define IMX94_FSEL_SLOW 0x100 + +/* Pull Up */ +#define IMX94_PU_ENABLE 0x200 +#define IMX94_PU_DISABLE 0x0 + +/* Pull Down */ +#define IMX94_PD_ENABLE 0x400 +#define IMX94_PD_DISABLE 0x0 + +/* Open Drain */ +#define IMX94_OD_ENABLE 0x800 +#define IMX94_OD_DISABLE 0x0 + +/* Schmitt trigger */ +#define IMX94_HYS_SCHMITT 0x1000 +#define IMX94_HYS_NO_SCHMITT 0x0 + +/* + * The pin function ID is a tuple of + */ +#define IMX94_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0304 0x092c 0x00 0x00 +#define IMX94_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x0304 0x0000 0x01 0x00 +#define IMX94_PAD_DAP_TDI__ECAT_LED_ERR 0x0000 0x0304 0x0000 0x02 0x00 +#define IMX94_PAD_DAP_TDI__CAN2_TX 0x0000 0x0304 0x0000 0x03 0x00 +#define IMX94_PAD_DAP_TDI__SINC_FILTER_GLUE3_BREAK 0x0000 0x0304 0x0000 0x04 0x00 +#define IMX94_PAD_DAP_TDI__GPIO4_IO4 0x0000 0x0304 0x0000 0x05 0x00 +#define IMX94_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0304 0x07bc 0x06 0x00 +#define IMX94_PAD_DAP_TDI__XBAR1_XBAR_INOUT26 0x0000 0x0304 0x0000 0x07 0x00 + +#define IMX94_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0308 0x0930 0x00 0x00 +#define IMX94_PAD_DAP_TMS_SWDIO__CAN5_TX 0x0004 0x0308 0x0000 0x01 0x00 +#define IMX94_PAD_DAP_TMS_SWDIO__GPT_MUX_INOUT10 0x0004 0x0308 0x0000 0x02 0x00 +#define IMX94_PAD_DAP_TMS_SWDIO__LPUART8_TX 0x0004 0x0308 0x07dc 0x03 0x00 +#define IMX94_PAD_DAP_TMS_SWDIO__SINC3_MOD_CLK1 0x0004 0x0308 0x0000 0x04 0x00 +#define IMX94_PAD_DAP_TMS_SWDIO__GPIO4_IO5 0x0004 0x0308 0x0000 0x05 0x00 +#define IMX94_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x0308 0x0000 0x06 0x00 +#define IMX94_PAD_DAP_TMS_SWDIO__XBAR1_XBAR_INOUT27 0x0004 0x0308 0x0000 0x07 0x00 + +#define IMX94_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x030c 0x0928 0x00 0x00 +#define IMX94_PAD_DAP_TCLK_SWCLK__CAN5_RX 0x0008 0x030c 0x0688 0x01 0x00 +#define IMX94_PAD_DAP_TCLK_SWCLK__GPT_MUX_INOUT11 0x0008 0x030c 0x0000 0x02 0x00 +#define IMX94_PAD_DAP_TCLK_SWCLK__LPUART8_RX 0x0008 0x030c 0x07d8 0x03 0x00 +#define IMX94_PAD_DAP_TCLK_SWCLK__SINC3_MOD_CLK0 0x0008 0x030c 0x0000 0x04 0x00 +#define IMX94_PAD_DAP_TCLK_SWCLK__GPIO4_IO6 0x0008 0x030c 0x0000 0x05 0x00 +#define IMX94_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x030c 0x07b8 0x06 0x00 +#define IMX94_PAD_DAP_TCLK_SWCLK__XBAR1_XBAR_INOUT28 0x0008 0x030c 0x0000 0x07 0x00 + +#define IMX94_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x0310 0x0000 0x00 0x00 +#define IMX94_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x0310 0x0000 0x01 0x00 +#define IMX94_PAD_DAP_TDO_TRACESWO__ECAT_RESET_OUT 0x000c 0x0310 0x0000 0x02 0x00 +#define IMX94_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x0310 0x067c 0x03 0x00 +#define IMX94_PAD_DAP_TDO_TRACESWO__SINC3_MOD_CLK2 0x000c 0x0310 0x0000 0x04 0x00 +#define IMX94_PAD_DAP_TDO_TRACESWO__GPIO4_IO7 0x000c 0x0310 0x0000 0x05 0x00 +#define IMX94_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x0310 0x07c0 0x06 0x00 +#define IMX94_PAD_DAP_TDO_TRACESWO__XBAR1_XBAR_INOUT29 0x000c 0x0310 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x0314 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO00__I3C2_PUR 0x0010 0x0314 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO00__XBAR1_XBAR_INOUT39 0x0010 0x0314 0x08d4 0x02 0x00 +#define IMX94_PAD_GPIO_IO00__I3C2_PUR_B 0x0010 0x0314 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x0314 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x0314 0x07c0 0x05 0x01 +#define IMX94_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x0314 0x0740 0x06 0x00 +#define IMX94_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x0314 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x0318 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO01__I3C2_SCL 0x0014 0x0318 0x0720 0x01 0x00 +#define IMX94_PAD_GPIO_IO01__XBAR1_XBAR_INOUT40 0x0014 0x0318 0x08d8 0x02 0x00 +#define IMX94_PAD_GPIO_IO01__EWM_OUT_B 0x0014 0x0318 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x0318 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x0318 0x07bc 0x05 0x01 +#define IMX94_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x0318 0x073c 0x06 0x00 +#define IMX94_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x0318 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x031c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO02__I3C2_SDA 0x0018 0x031c 0x0724 0x01 0x00 +#define IMX94_PAD_GPIO_IO02__XBAR1_XBAR_INOUT41 0x0018 0x031c 0x08dc 0x02 0x00 +#define IMX94_PAD_GPIO_IO02__GPT_MUX_INOUT1 0x0018 0x031c 0x0700 0x03 0x00 +#define IMX94_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x031c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x031c 0x07b8 0x05 0x01 +#define IMX94_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x031c 0x074c 0x06 0x00 +#define IMX94_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x031c 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x0320 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO03__EWM_OUT_B 0x001c 0x0320 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO03__XBAR1_XBAR_INOUT42 0x001c 0x0320 0x08e0 0x02 0x00 +#define IMX94_PAD_GPIO_IO03__GPT_MUX_INOUT4 0x001c 0x0320 0x0708 0x03 0x00 +#define IMX94_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x0320 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x0320 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x0320 0x0748 0x06 0x00 +#define IMX94_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x0320 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x0324 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x0324 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO04__PDM_CLK 0x0020 0x0324 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO04__GPT_MUX_INOUT5 0x0020 0x0324 0x070c 0x03 0x00 +#define IMX94_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x0324 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x0324 0x07cc 0x05 0x00 +#define IMX94_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x0324 0x074c 0x06 0x01 +#define IMX94_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x0324 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x0328 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x0328 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x0328 0x0610 0x02 0x00 +#define IMX94_PAD_GPIO_IO05__GPT_MUX_INOUT7 0x0024 0x0328 0x0714 0x03 0x00 +#define IMX94_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x0328 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x0328 0x07c8 0x05 0x00 +#define IMX94_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x0328 0x0748 0x06 0x01 +#define IMX94_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x0328 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x032c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x032c 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x032c 0x0614 0x02 0x00 +#define IMX94_PAD_GPIO_IO06__GPT_MUX_INOUT8 0x0028 0x032c 0x0718 0x03 0x00 +#define IMX94_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x032c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x032c 0x07c4 0x05 0x00 +#define IMX94_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x032c 0x0754 0x06 0x00 +#define IMX94_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x032c 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x0330 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x0330 0x0768 0x01 0x00 +#define IMX94_PAD_GPIO_IO07__XBAR1_XBAR_INOUT43 0x002c 0x0330 0x08e4 0x02 0x00 +#define IMX94_PAD_GPIO_IO07__GPT_MUX_INOUT3 0x002c 0x0330 0x0704 0x03 0x00 +#define IMX94_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x0330 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x0330 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x0330 0x0750 0x06 0x00 +#define IMX94_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x0330 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x0334 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x0334 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO08__USDHC2_WP 0x0030 0x0334 0x0854 0x02 0x00 +#define IMX94_PAD_GPIO_IO08__GPT_MUX_INOUT2 0x0030 0x0334 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x0334 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x0334 0x07d4 0x05 0x00 +#define IMX94_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x0334 0x0754 0x06 0x01 +#define IMX94_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x0334 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x0338 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x0338 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO09__XBAR1_XBAR_INOUT44 0x0034 0x0338 0x08e8 0x02 0x00 +#define IMX94_PAD_GPIO_IO09__GPT_MUX_INOUT0 0x0034 0x0338 0x06fc 0x03 0x00 +#define IMX94_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x0338 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x0338 0x07d0 0x05 0x00 +#define IMX94_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x0338 0x0750 0x06 0x01 +#define IMX94_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x0338 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x033c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x033c 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO10__XBAR1_XBAR_INOUT45 0x0038 0x033c 0x08ec 0x02 0x00 +#define IMX94_PAD_GPIO_IO10__GPT_MUX_INOUT6 0x0038 0x033c 0x0710 0x03 0x00 +#define IMX94_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x033c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x033c 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x033c 0x075c 0x06 0x00 +#define IMX94_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x033c 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x0340 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x0340 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO11__XBAR1_XBAR_INOUT46 0x003c 0x0340 0x08f0 0x02 0x00 +#define IMX94_PAD_GPIO_IO11__GPT_MUX_INOUT9 0x003c 0x0340 0x071c 0x03 0x00 +#define IMX94_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x0340 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x0340 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x0340 0x0758 0x06 0x00 +#define IMX94_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x0340 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x0344 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x0344 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x0344 0x0618 0x02 0x00 +#define IMX94_PAD_GPIO_IO12__FLEXIO1_FLEXIO12 0x0040 0x0344 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x0344 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x0344 0x07dc 0x05 0x01 +#define IMX94_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x0344 0x075c 0x06 0x01 + +#define IMX94_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x0348 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x0348 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x0348 0x061c 0x02 0x00 +#define IMX94_PAD_GPIO_IO13__XBAR1_XBAR_INOUT47 0x0044 0x0348 0x08f4 0x03 0x00 +#define IMX94_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x0348 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x0348 0x07d8 0x05 0x01 +#define IMX94_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x0348 0x0758 0x06 0x01 +#define IMX94_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x0348 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x034c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO14__LPUART10_CTS_B 0x0048 0x034c 0x078c 0x01 0x00 +#define IMX94_PAD_GPIO_IO14__ECAT_SDA 0x0048 0x034c 0x062c 0x02 0x00 +#define IMX94_PAD_GPIO_IO14__XBAR1_XBAR_INOUT48 0x0048 0x034c 0x08f8 0x03 0x00 +#define IMX94_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x034c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x034c 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x034c 0x07b4 0x06 0x00 +#define IMX94_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x034c 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x0350 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO15__LPUART10_RTS_B 0x004c 0x0350 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO15__ECAT_SCL 0x004c 0x0350 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO15__XBAR1_XBAR_INOUT8 0x004c 0x0350 0x087c 0x03 0x00 +#define IMX94_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x0350 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x0350 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x0350 0x07b0 0x06 0x00 +#define IMX94_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x0350 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0354 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO16__LPI2C3_SDA 0x0050 0x0354 0x0730 0x01 0x00 +#define IMX94_PAD_GPIO_IO16__CAN3_TX 0x0050 0x0354 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO16__EWM_OUT_B 0x0050 0x0354 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO16__LPUART11_TX 0x0050 0x0354 0x079c 0x04 0x00 +#define IMX94_PAD_GPIO_IO16__GPT_MUX_INOUT0 0x0050 0x0354 0x06fc 0x05 0x01 +#define IMX94_PAD_GPIO_IO16__FLEXPWM4_PWMA0 0x0050 0x0354 0x06d4 0x06 0x00 +#define IMX94_PAD_GPIO_IO16__XBAR1_XBAR_INOUT30 0x0050 0x0354 0x08b0 0x07 0x00 + +#define IMX94_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0358 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO17__LPI2C3_SCL 0x0054 0x0358 0x072c 0x01 0x00 +#define IMX94_PAD_GPIO_IO17__CAN3_RX 0x0054 0x0358 0x0680 0x02 0x00 +#define IMX94_PAD_GPIO_IO17__LPI2C6_HREQ 0x0054 0x0358 0x0744 0x03 0x00 +#define IMX94_PAD_GPIO_IO17__LPUART11_RX 0x0054 0x0358 0x0798 0x04 0x00 +#define IMX94_PAD_GPIO_IO17__GPT_MUX_INOUT3 0x0054 0x0358 0x0704 0x05 0x01 +#define IMX94_PAD_GPIO_IO17__FLEXPWM4_PWMB0 0x0054 0x0358 0x06e4 0x06 0x00 +#define IMX94_PAD_GPIO_IO17__XBAR1_XBAR_INOUT31 0x0054 0x0358 0x08b4 0x07 0x00 + +#define IMX94_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x035c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO18__LPI2C4_SDA 0x0058 0x035c 0x0738 0x01 0x00 +#define IMX94_PAD_GPIO_IO18__LPUART10_TX 0x0058 0x035c 0x0794 0x02 0x00 +#define IMX94_PAD_GPIO_IO18__LPI2C7_HREQ 0x0058 0x035c 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO18__LPUART11_CTS_B 0x0058 0x035c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO18__GPT_MUX_INOUT6 0x0058 0x035c 0x0710 0x05 0x01 +#define IMX94_PAD_GPIO_IO18__FLEXPWM4_PWMA1 0x0058 0x035c 0x06d8 0x06 0x00 +#define IMX94_PAD_GPIO_IO18__XBAR1_XBAR_INOUT32 0x0058 0x035c 0x08b8 0x07 0x00 + +#define IMX94_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x0360 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO19__LPI2C4_SCL 0x005c 0x0360 0x0734 0x01 0x00 +#define IMX94_PAD_GPIO_IO19__LPUART10_RX 0x005c 0x0360 0x0790 0x02 0x00 +#define IMX94_PAD_GPIO_IO19__LPI2C8_HREQ 0x005c 0x0360 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO19__LPUART11_RTS_B 0x005c 0x0360 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO19__GPT_MUX_INOUT9 0x005c 0x0360 0x071c 0x05 0x01 +#define IMX94_PAD_GPIO_IO19__FLEXPWM4_PWMB1 0x005c 0x0360 0x06e8 0x06 0x00 +#define IMX94_PAD_GPIO_IO19__XBAR1_XBAR_INOUT33 0x005c 0x0360 0x08bc 0x07 0x00 + +#define IMX94_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0364 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x0060 0x0364 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO20__LPUART6_TX 0x0060 0x0364 0x07cc 0x02 0x01 +#define IMX94_PAD_GPIO_IO20__LPI2C8_SDA 0x0060 0x0364 0x075c 0x03 0x02 +#define IMX94_PAD_GPIO_IO20__LPSPI4_PCS2 0x0060 0x0364 0x076c 0x04 0x00 +#define IMX94_PAD_GPIO_IO20__LPSPI3_PCS1 0x0060 0x0364 0x0768 0x05 0x01 +#define IMX94_PAD_GPIO_IO20__FLEXPWM4_PWMA2 0x0060 0x0364 0x06dc 0x06 0x00 +#define IMX94_PAD_GPIO_IO20__XBAR1_XBAR_INOUT34 0x0060 0x0364 0x08c0 0x07 0x00 + +#define IMX94_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0368 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO21__SAI2_TX_BCLK 0x0064 0x0368 0x07f8 0x01 0x00 +#define IMX94_PAD_GPIO_IO21__LPUART6_RX 0x0064 0x0368 0x07c8 0x02 0x01 +#define IMX94_PAD_GPIO_IO21__LPI2C8_SCL 0x0064 0x0368 0x0758 0x03 0x02 +#define IMX94_PAD_GPIO_IO21__LPSPI4_PCS1 0x0064 0x0368 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO21__LPI2C3_HREQ 0x0064 0x0368 0x0728 0x05 0x00 +#define IMX94_PAD_GPIO_IO21__FLEXPWM4_PWMB2 0x0064 0x0368 0x06ec 0x06 0x00 +#define IMX94_PAD_GPIO_IO21__XBAR1_XBAR_INOUT35 0x0064 0x0368 0x08c4 0x07 0x00 + +#define IMX94_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x036c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO22__SAI2_MCLK 0x0068 0x036c 0x07e8 0x01 0x00 +#define IMX94_PAD_GPIO_IO22__LPUART6_CTS_B 0x0068 0x036c 0x07c4 0x02 0x01 +#define IMX94_PAD_GPIO_IO22__XBAR1_XBAR_INOUT9 0x0068 0x036c 0x0880 0x03 0x00 +#define IMX94_PAD_GPIO_IO22__LPSPI4_PCS0 0x0068 0x036c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO22__FLEXPWM3_PWMA3 0x0068 0x036c 0x06b4 0x05 0x00 +#define IMX94_PAD_GPIO_IO22__FLEXPWM4_PWMA3 0x0068 0x036c 0x06e0 0x06 0x00 +#define IMX94_PAD_GPIO_IO22__SINC4_EMCLK0 0x0068 0x036c 0x082c 0x07 0x00 + +#define IMX94_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x0370 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO23__PCIE2_CLKREQ_B 0x006c 0x0370 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO23__LPUART6_RTS_B 0x006c 0x0370 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO23__XBAR1_XBAR_INOUT10 0x006c 0x0370 0x0884 0x03 0x00 +#define IMX94_PAD_GPIO_IO23__LPSPI4_SIN 0x006c 0x0370 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO23__FLEXPWM3_PWMB3 0x006c 0x0370 0x06c4 0x05 0x00 +#define IMX94_PAD_GPIO_IO23__FLEXPWM4_PWMB3 0x006c 0x0370 0x06f0 0x06 0x00 +#define IMX94_PAD_GPIO_IO23__SINC4_EMBIT0 0x006c 0x0370 0x0820 0x07 0x00 + +#define IMX94_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0374 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO24__SAI2_RX_BCLK 0x0070 0x0374 0x07ec 0x01 0x00 +#define IMX94_PAD_GPIO_IO24__LPUART11_TX 0x0070 0x0374 0x079c 0x02 0x01 +#define IMX94_PAD_GPIO_IO24__LPI2C3_HREQ 0x0070 0x0374 0x0728 0x03 0x01 +#define IMX94_PAD_GPIO_IO24__LPSPI4_SOUT 0x0070 0x0374 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO24__SINC_FILTER_GLUE2_BREAK 0x0070 0x0374 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO24__FLEXPWM4_PWMX0 0x0070 0x0374 0x06f4 0x06 0x00 +#define IMX94_PAD_GPIO_IO24__XBAR1_XBAR_INOUT36 0x0070 0x0374 0x08c8 0x07 0x00 + +#define IMX94_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0378 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO25__SAI2_RX_SYNC 0x0074 0x0378 0x07f4 0x01 0x00 +#define IMX94_PAD_GPIO_IO25__LPUART11_RX 0x0074 0x0378 0x0798 0x02 0x01 +#define IMX94_PAD_GPIO_IO25__LPI2C4_HREQ 0x0074 0x0378 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO25__LPSPI4_SCK 0x0074 0x0378 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO25__SINC_FILTER_GLUE1_BREAK 0x0074 0x0378 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO25__FLEXPWM4_PWMX1 0x0074 0x0378 0x06f8 0x06 0x00 +#define IMX94_PAD_GPIO_IO25__XBAR1_XBAR_INOUT37 0x0074 0x0378 0x08cc 0x07 0x00 + +#define IMX94_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x037c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO26__LPI2C5_SCL 0x0078 0x037c 0x073c 0x01 0x01 +#define IMX94_PAD_GPIO_IO26__LPUART12_TX 0x0078 0x037c 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO26__GPT_MUX_INOUT4 0x0078 0x037c 0x0708 0x03 0x01 +#define IMX94_PAD_GPIO_IO26__FLEXIO1_3_1_FLEXIO0 0x0078 0x037c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO26__SAI2_RX_DATA0 0x0078 0x037c 0x07f0 0x05 0x00 +#define IMX94_PAD_GPIO_IO26__FLEXPWM4_PWMX2 0x0078 0x037c 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO26__XBAR1_XBAR_INOUT38 0x0078 0x037c 0x08d0 0x07 0x00 + +#define IMX94_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x0380 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO27__LPI2C5_SDA 0x007c 0x0380 0x0740 0x01 0x01 +#define IMX94_PAD_GPIO_IO27__LPUART12_RX 0x007c 0x0380 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO27__GPT_MUX_INOUT5 0x007c 0x0380 0x070c 0x03 0x01 +#define IMX94_PAD_GPIO_IO27__FLEXIO1_3_1_FLEXIO1 0x007c 0x0380 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO27__SAI2_TX_DATA0 0x007c 0x0380 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO27__FLEXPWM4_PWMX3 0x007c 0x0380 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO27__SINC4_MOD_CLK0 0x007c 0x0380 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0384 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO28__LPI2C6_SCL 0x0080 0x0384 0x0748 0x01 0x02 +#define IMX94_PAD_GPIO_IO28__LPUART12_CTS_B 0x0080 0x0384 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO28__GPT_MUX_INOUT7 0x0080 0x0384 0x0714 0x03 0x01 +#define IMX94_PAD_GPIO_IO28__FLEXIO1_3_1_FLEXIO2 0x0080 0x0384 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO28__SAI2_TX_SYNC 0x0080 0x0384 0x07fc 0x05 0x00 +#define IMX94_PAD_GPIO_IO28__FLEXPWM1_PWMX2 0x0080 0x0384 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO28__XBAR1_XBAR_INOUT4 0x0080 0x0384 0x086c 0x07 0x00 + +#define IMX94_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0388 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO29__LPI2C6_SDA 0x0084 0x0388 0x074c 0x01 0x02 +#define IMX94_PAD_GPIO_IO29__LPUART12_RTS_B 0x0084 0x0388 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO29__I3C2_SDA 0x0084 0x0388 0x0724 0x03 0x01 +#define IMX94_PAD_GPIO_IO29__FLEXIO1_3_1_FLEXIO3 0x0084 0x0388 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO29__FLEXPWM3_PWMX0 0x0084 0x0388 0x06c8 0x05 0x00 +#define IMX94_PAD_GPIO_IO29__FLEXPWM1_PWMX3 0x0084 0x0388 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO29__XBAR1_XBAR_INOUT5 0x0084 0x0388 0x0870 0x07 0x00 + +#define IMX94_PAD_GPIO_IO30__GPIO2_IO30 0x0088 0x038c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO30__LPIT2_TRIGGER0 0x0088 0x038c 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO30__LPUART3_TX 0x0088 0x038c 0x07a8 0x02 0x00 +#define IMX94_PAD_GPIO_IO30__I3C2_PUR 0x0088 0x038c 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO30__FLEXIO1_3_1_FLEXIO4 0x0088 0x038c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO30__I3C2_PUR_B 0x0088 0x038c 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO30__FLEXPWM2_PWMX2 0x0088 0x038c 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO30__XBAR1_XBAR_INOUT6 0x0088 0x038c 0x0874 0x07 0x00 + +#define IMX94_PAD_GPIO_IO31__GPIO2_IO31 0x008c 0x0390 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO31__LPIT2_TRIGGER1 0x008c 0x0390 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO31__LPUART3_RX 0x008c 0x0390 0x07a4 0x02 0x00 +#define IMX94_PAD_GPIO_IO31__I3C2_SCL 0x008c 0x0390 0x0720 0x03 0x01 +#define IMX94_PAD_GPIO_IO31__FLEXIO1_3_1_FLEXIO5 0x008c 0x0390 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO31__FLEXPWM3_PWMX1 0x008c 0x0390 0x06cc 0x05 0x00 +#define IMX94_PAD_GPIO_IO31__FLEXPWM2_PWMX3 0x008c 0x0390 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO31__XBAR1_XBAR_INOUT7 0x008c 0x0390 0x0878 0x07 0x00 + +#define IMX94_PAD_GPIO_IO32__GPIO3_IO0 0x0090 0x0394 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO32__LPIT3_TRIGGER0 0x0090 0x0394 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO32__LPUART7_TX 0x0090 0x0394 0x07d4 0x02 0x01 +#define IMX94_PAD_GPIO_IO32__GPT_MUX_INOUT8 0x0090 0x0394 0x0718 0x03 0x01 +#define IMX94_PAD_GPIO_IO32__FLEXIO1_3_1_FLEXIO6 0x0090 0x0394 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO32__FLEXPWM3_PWMA0 0x0090 0x0394 0x06a8 0x05 0x00 +#define IMX94_PAD_GPIO_IO32__SINC_FILTER_GLUE2_BREAK 0x0090 0x0394 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO32__XBAR1_XBAR_INOUT8 0x0090 0x0394 0x087c 0x07 0x01 + +#define IMX94_PAD_GPIO_IO33__GPIO3_IO1 0x0094 0x0398 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO33__LPIT3_TRIGGER1 0x0094 0x0398 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO33__LPUART7_RX 0x0094 0x0398 0x07d0 0x02 0x01 +#define IMX94_PAD_GPIO_IO33__GPT_MUX_INOUT1 0x0094 0x0398 0x0700 0x03 0x01 +#define IMX94_PAD_GPIO_IO33__FLEXIO1_3_1_FLEXIO7 0x0094 0x0398 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO33__FLEXPWM3_PWMB0 0x0094 0x0398 0x06b8 0x05 0x00 +#define IMX94_PAD_GPIO_IO33__SINC_FILTER_GLUE1_BREAK 0x0094 0x0398 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO33__XBAR1_XBAR_INOUT9 0x0094 0x0398 0x0880 0x07 0x01 + +#define IMX94_PAD_GPIO_IO34__GPIO3_IO2 0x0098 0x039c 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO34__LPI2C7_SDA 0x0098 0x039c 0x0754 0x01 0x02 +#define IMX94_PAD_GPIO_IO34__CAN2_TX 0x0098 0x039c 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO34__ECAT_SDA 0x0098 0x039c 0x062c 0x03 0x01 +#define IMX94_PAD_GPIO_IO34__FLEXIO1_3_1_FLEXIO8 0x0098 0x039c 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO34__FLEXPWM3_PWMA1 0x0098 0x039c 0x06ac 0x05 0x00 +#define IMX94_PAD_GPIO_IO34__FLEXPWM1_PWMX0 0x0098 0x039c 0x0698 0x06 0x00 +#define IMX94_PAD_GPIO_IO34__XBAR1_XBAR_INOUT10 0x0098 0x039c 0x0884 0x07 0x01 + +#define IMX94_PAD_GPIO_IO35__GPIO3_IO3 0x009c 0x03a0 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO35__LPI2C7_SCL 0x009c 0x03a0 0x0750 0x01 0x02 +#define IMX94_PAD_GPIO_IO35__CAN2_RX 0x009c 0x03a0 0x067c 0x02 0x01 +#define IMX94_PAD_GPIO_IO35__ECAT_SCL 0x009c 0x03a0 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO35__FLEXIO1_3_1_FLEXIO9 0x009c 0x03a0 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO35__FLEXPWM3_PWMB1 0x009c 0x03a0 0x06bc 0x05 0x00 +#define IMX94_PAD_GPIO_IO35__FLEXPWM1_PWMX1 0x009c 0x03a0 0x069c 0x06 0x00 +#define IMX94_PAD_GPIO_IO35__XBAR1_XBAR_INOUT11 0x009c 0x03a0 0x0888 0x07 0x00 + +#define IMX94_PAD_GPIO_IO36__USDHC2_WP 0x00a0 0x03a4 0x0854 0x03 0x01 +#define IMX94_PAD_GPIO_IO36__FLEXIO1_3_1_FLEXIO10 0x00a0 0x03a4 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO36__FLEXPWM3_PWMA2 0x00a0 0x03a4 0x06b0 0x05 0x00 +#define IMX94_PAD_GPIO_IO36__FLEXPWM2_PWMX0 0x00a0 0x03a4 0x06a0 0x06 0x00 +#define IMX94_PAD_GPIO_IO36__XBAR1_XBAR_INOUT12 0x00a0 0x03a4 0x088c 0x07 0x00 +#define IMX94_PAD_GPIO_IO36__GPIO3_IO4 0x00a0 0x03a4 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO36__LPI2C8_SDA 0x00a0 0x03a4 0x075c 0x01 0x03 +#define IMX94_PAD_GPIO_IO36__CAN4_TX 0x00a0 0x03a4 0x0000 0x02 0x00 + +#define IMX94_PAD_GPIO_IO37__GPIO3_IO5 0x00a4 0x03a8 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO37__LPI2C8_SCL 0x00a4 0x03a8 0x0758 0x01 0x03 +#define IMX94_PAD_GPIO_IO37__CAN4_RX 0x00a4 0x03a8 0x0684 0x02 0x00 +#define IMX94_PAD_GPIO_IO37__LPI2C5_HREQ 0x00a4 0x03a8 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO37__FLEXIO1_3_1_FLEXIO11 0x00a4 0x03a8 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO37__FLEXPWM3_PWMB2 0x00a4 0x03a8 0x06c0 0x05 0x00 +#define IMX94_PAD_GPIO_IO37__FLEXPWM2_PWMX1 0x00a4 0x03a8 0x06a4 0x06 0x00 +#define IMX94_PAD_GPIO_IO37__XBAR1_XBAR_INOUT13 0x00a4 0x03a8 0x0890 0x07 0x00 + +#define IMX94_PAD_GPIO_IO38__GPIO3_IO6 0x00a8 0x03ac 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO38__NETC_1588MUX_INOUT0 0x00a8 0x03ac 0x064c 0x01 0x00 +#define IMX94_PAD_GPIO_IO38__LPI2C3_SDA 0x00a8 0x03ac 0x0730 0x02 0x01 +#define IMX94_PAD_GPIO_IO38__LPIT3_TRIGGER2 0x00a8 0x03ac 0x0764 0x03 0x00 +#define IMX94_PAD_GPIO_IO38__FLEXIO1_3_1_FLEXIO12 0x00a8 0x03ac 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO38__LPUART3_CTS_B 0x00a8 0x03ac 0x07a0 0x05 0x00 +#define IMX94_PAD_GPIO_IO38__FLEXPWM3_PWMX0 0x00a8 0x03ac 0x06c8 0x06 0x01 +#define IMX94_PAD_GPIO_IO38__XBAR1_XBAR_INOUT14 0x00a8 0x03ac 0x0894 0x07 0x00 + +#define IMX94_PAD_GPIO_IO39__GPIO3_IO7 0x00ac 0x03b0 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO39__NETC_1588MUX_INOUT1 0x00ac 0x03b0 0x0650 0x01 0x00 +#define IMX94_PAD_GPIO_IO39__LPI2C3_SCL 0x00ac 0x03b0 0x072c 0x02 0x01 +#define IMX94_PAD_GPIO_IO39__LPIT2_TRIGGER2 0x00ac 0x03b0 0x0760 0x03 0x00 +#define IMX94_PAD_GPIO_IO39__FLEXIO1_3_1_FLEXIO13 0x00ac 0x03b0 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO39__LPUART3_RTS_B 0x00ac 0x03b0 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO39__FLEXPWM3_PWMX1 0x00ac 0x03b0 0x06cc 0x06 0x01 +#define IMX94_PAD_GPIO_IO39__XBAR1_XBAR_INOUT15 0x00ac 0x03b0 0x0898 0x07 0x00 + +#define IMX94_PAD_GPIO_IO40__GPIO3_IO8 0x00b0 0x03b4 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO40__NETC_1588MUX_INOUT2 0x00b0 0x03b4 0x0654 0x01 0x00 +#define IMX94_PAD_GPIO_IO40__LPI2C7_SDA 0x00b0 0x03b4 0x0754 0x02 0x03 +#define IMX94_PAD_GPIO_IO40__LPUART4_TX 0x00b0 0x03b4 0x07b4 0x03 0x01 +#define IMX94_PAD_GPIO_IO40__FLEXIO1_3_1_FLEXIO14 0x00b0 0x03b4 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO40__FLEXPWM3_PWMX2 0x00b0 0x03b4 0x06d0 0x05 0x00 +#define IMX94_PAD_GPIO_IO40__FLEXPWM4_PWMX0 0x00b0 0x03b4 0x06f4 0x06 0x01 +#define IMX94_PAD_GPIO_IO40__XBAR1_XBAR_INOUT16 0x00b0 0x03b4 0x089c 0x07 0x00 + +#define IMX94_PAD_GPIO_IO41__GPIO3_IO9 0x00b4 0x03b8 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO41__NETC_1588MUX_INOUT3 0x00b4 0x03b8 0x0658 0x01 0x00 +#define IMX94_PAD_GPIO_IO41__LPI2C7_SCL 0x00b4 0x03b8 0x0750 0x02 0x03 +#define IMX94_PAD_GPIO_IO41__LPUART4_RX 0x00b4 0x03b8 0x07b0 0x03 0x01 +#define IMX94_PAD_GPIO_IO41__FLEXIO1_3_1_FLEXIO15 0x00b4 0x03b8 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO41__LPI2C6_HREQ 0x00b4 0x03b8 0x0744 0x05 0x01 +#define IMX94_PAD_GPIO_IO41__FLEXPWM4_PWMX1 0x00b4 0x03b8 0x06f8 0x06 0x01 +#define IMX94_PAD_GPIO_IO41__XBAR1_XBAR_INOUT17 0x00b4 0x03b8 0x08a0 0x07 0x00 + +#define IMX94_PAD_GPIO_IO42__GPIO3_IO10 0x00b8 0x03bc 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO42__SAI3_TX_BCLK 0x00b8 0x03bc 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO42__PDM_BIT_STREAM2 0x00b8 0x03bc 0x0618 0x02 0x01 +#define IMX94_PAD_GPIO_IO42__XBAR1_XBAR_INOUT11 0x00b8 0x03bc 0x0888 0x03 0x01 +#define IMX94_PAD_GPIO_IO42__LPUART3_TX 0x00b8 0x03bc 0x07a8 0x04 0x01 +#define IMX94_PAD_GPIO_IO42__LPSPI4_PCS2 0x00b8 0x03bc 0x076c 0x05 0x01 +#define IMX94_PAD_GPIO_IO42__LPUART4_CTS_B 0x00b8 0x03bc 0x07ac 0x06 0x00 +#define IMX94_PAD_GPIO_IO42__SINC4_EMCLK1 0x00b8 0x03bc 0x0830 0x07 0x00 + +#define IMX94_PAD_GPIO_IO43__GPIO3_IO11 0x00bc 0x03c0 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO43__SAI3_MCLK 0x00bc 0x03c0 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO43__XBAR1_XBAR_INOUT12 0x00bc 0x03c0 0x088c 0x03 0x01 +#define IMX94_PAD_GPIO_IO43__LPUART3_RX 0x00bc 0x03c0 0x07a4 0x04 0x01 +#define IMX94_PAD_GPIO_IO43__LPSPI3_PCS1 0x00bc 0x03c0 0x0768 0x05 0x02 +#define IMX94_PAD_GPIO_IO43__LPUART4_RTS_B 0x00bc 0x03c0 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO43__SINC4_EMBIT1 0x00bc 0x03c0 0x0824 0x07 0x00 + +#define IMX94_PAD_GPIO_IO44__GPIO3_IO12 0x00c0 0x03c4 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO44__SAI3_RX_BCLK 0x00c0 0x03c4 0x0800 0x01 0x00 +#define IMX94_PAD_GPIO_IO44__PDM_BIT_STREAM1 0x00c0 0x03c4 0x0614 0x02 0x01 +#define IMX94_PAD_GPIO_IO44__LPUART9_TX 0x00c0 0x03c4 0x07e4 0x03 0x00 +#define IMX94_PAD_GPIO_IO44__LPSPI5_PCS0 0x00c0 0x03c4 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO44__LPI2C3_SDA 0x00c0 0x03c4 0x0730 0x05 0x02 +#define IMX94_PAD_GPIO_IO44__TPM5_CH2 0x00c0 0x03c4 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO44__SINC_FILTER_GLUE4_BREAK 0x00c0 0x03c4 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO45__GPIO3_IO13 0x00c4 0x03c8 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO45__SAI3_RX_SYNC 0x00c4 0x03c8 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO45__PDM_BIT_STREAM3 0x00c4 0x03c8 0x061c 0x02 0x01 +#define IMX94_PAD_GPIO_IO45__LPUART9_RX 0x00c4 0x03c8 0x07e0 0x03 0x00 +#define IMX94_PAD_GPIO_IO45__LPSPI5_SIN 0x00c4 0x03c8 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO45__LPI2C3_SCL 0x00c4 0x03c8 0x072c 0x05 0x02 +#define IMX94_PAD_GPIO_IO45__TPM6_CH2 0x00c4 0x03c8 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO45__SAI3_TX_DATA0 0x00c4 0x03c8 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO46__GPIO3_IO14 0x00c8 0x03cc 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO46__SAI3_RX_DATA0 0x00c8 0x03cc 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO46__PDM_BIT_STREAM0 0x00c8 0x03cc 0x0610 0x02 0x01 +#define IMX94_PAD_GPIO_IO46__LPUART9_CTS_B 0x00c8 0x03cc 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO46__LPSPI5_SOUT 0x00c8 0x03cc 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO46__LPI2C4_SDA 0x00c8 0x03cc 0x0738 0x05 0x01 +#define IMX94_PAD_GPIO_IO46__TPM3_CH1 0x00c8 0x03cc 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO46__EWM_OUT_B 0x00c8 0x03cc 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO47__GPIO3_IO15 0x00cc 0x03d0 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0 0x00cc 0x03d0 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO47__PDM_CLK 0x00cc 0x03d0 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO47__LPUART9_RTS_B 0x00cc 0x03d0 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO47__LPSPI5_SCK 0x00cc 0x03d0 0x0000 0x04 0x00 +#define IMX94_PAD_GPIO_IO47__LPI2C4_SCL 0x00cc 0x03d0 0x0734 0x05 0x01 +#define IMX94_PAD_GPIO_IO47__TPM4_CH1 0x00cc 0x03d0 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO47__SAI3_RX_BCLK 0x00cc 0x03d0 0x0800 0x07 0x01 + +#define IMX94_PAD_GPIO_IO48__GPIO3_IO16 0x00d0 0x03d4 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO48__USDHC3_CLK 0x00d0 0x03d4 0x0000 0x01 0x00 +#define IMX94_PAD_GPIO_IO48__CAN5_TX 0x00d0 0x03d4 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO48__LPUART10_TX 0x00d0 0x03d4 0x0794 0x03 0x01 +#define IMX94_PAD_GPIO_IO48__TPM5_CH1 0x00d0 0x03d4 0x0840 0x04 0x00 +#define IMX94_PAD_GPIO_IO48__TPM6_EXTCLK 0x00d0 0x03d4 0x0850 0x05 0x00 +#define IMX94_PAD_GPIO_IO48__LPI2C5_SDA 0x00d0 0x03d4 0x0740 0x06 0x02 +#define IMX94_PAD_GPIO_IO48__SINC4_EMCLK2 0x00d0 0x03d4 0x0834 0x07 0x00 + +#define IMX94_PAD_GPIO_IO49__GPIO3_IO17 0x00d4 0x03d8 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO49__USDHC3_CMD 0x00d4 0x03d8 0x0858 0x01 0x00 +#define IMX94_PAD_GPIO_IO49__CAN5_RX 0x00d4 0x03d8 0x0688 0x02 0x01 +#define IMX94_PAD_GPIO_IO49__LPUART10_RX 0x00d4 0x03d8 0x0790 0x03 0x01 +#define IMX94_PAD_GPIO_IO49__TPM6_CH1 0x00d4 0x03d8 0x0848 0x04 0x00 +#define IMX94_PAD_GPIO_IO49__XBAR1_XBAR_INOUT13 0x00d4 0x03d8 0x0890 0x05 0x01 +#define IMX94_PAD_GPIO_IO49__LPI2C5_SCL 0x00d4 0x03d8 0x073c 0x06 0x02 +#define IMX94_PAD_GPIO_IO49__SINC4_EMBIT2 0x00d4 0x03d8 0x0828 0x07 0x00 + +#define IMX94_PAD_GPIO_IO50__GPIO3_IO18 0x00d8 0x03dc 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO50__USDHC3_DATA0 0x00d8 0x03dc 0x085c 0x01 0x00 +#define IMX94_PAD_GPIO_IO50__XBAR1_XBAR_INOUT14 0x00d8 0x03dc 0x0894 0x02 0x01 +#define IMX94_PAD_GPIO_IO50__LPUART10_CTS_B 0x00d8 0x03dc 0x078c 0x03 0x01 +#define IMX94_PAD_GPIO_IO50__TPM3_CH3 0x00d8 0x03dc 0x0838 0x04 0x00 +#define IMX94_PAD_GPIO_IO50__JTAG_MUX_TDO 0x00d8 0x03dc 0x0000 0x05 0x00 +#define IMX94_PAD_GPIO_IO50__LPSPI6_PCS1 0x00d8 0x03dc 0x0774 0x06 0x00 +#define IMX94_PAD_GPIO_IO50__SINC4_EMCLK3 0x00d8 0x03dc 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO51__GPIO3_IO19 0x00dc 0x03e0 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO51__USDHC3_DATA1 0x00dc 0x03e0 0x0860 0x01 0x00 +#define IMX94_PAD_GPIO_IO51__CAN2_TX 0x00dc 0x03e0 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO51__LPUART10_RTS_B 0x00dc 0x03e0 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO51__TPM4_CH3 0x00dc 0x03e0 0x083c 0x04 0x00 +#define IMX94_PAD_GPIO_IO51__JTAG_MUX_TCK 0x00dc 0x03e0 0x0928 0x05 0x01 +#define IMX94_PAD_GPIO_IO51__LPSPI7_PCS1 0x00dc 0x03e0 0x0778 0x06 0x00 +#define IMX94_PAD_GPIO_IO51__SINC4_EMBIT3 0x00dc 0x03e0 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO52__GPIO3_IO20 0x00e0 0x03e4 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO52__USDHC3_DATA2 0x00e0 0x03e4 0x0864 0x01 0x00 +#define IMX94_PAD_GPIO_IO52__PDM_BIT_STREAM1 0x00e0 0x03e4 0x0614 0x02 0x02 +#define IMX94_PAD_GPIO_IO52__LPSPI4_PCS2 0x00e0 0x03e4 0x076c 0x03 0x02 +#define IMX94_PAD_GPIO_IO52__TPM5_CH3 0x00e0 0x03e4 0x0844 0x04 0x00 +#define IMX94_PAD_GPIO_IO52__JTAG_MUX_TDI 0x00e0 0x03e4 0x092c 0x05 0x01 +#define IMX94_PAD_GPIO_IO52__LPSPI8_PCS1 0x00e0 0x03e4 0x077c 0x06 0x00 +#define IMX94_PAD_GPIO_IO52__SAI3_TX_SYNC 0x00e0 0x03e4 0x0804 0x07 0x00 + +#define IMX94_PAD_GPIO_IO53__GPIO3_IO21 0x00e4 0x03e8 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO53__USDHC3_DATA3 0x00e4 0x03e8 0x0868 0x01 0x00 +#define IMX94_PAD_GPIO_IO53__CAN2_RX 0x00e4 0x03e8 0x067c 0x02 0x02 +#define IMX94_PAD_GPIO_IO53__LPSPI3_PCS1 0x00e4 0x03e8 0x0768 0x03 0x03 +#define IMX94_PAD_GPIO_IO53__TPM6_CH3 0x00e4 0x03e8 0x084c 0x04 0x00 +#define IMX94_PAD_GPIO_IO53__JTAG_MUX_TMS 0x00e4 0x03e8 0x0930 0x05 0x01 +#define IMX94_PAD_GPIO_IO53__LPSPI5_PCS1 0x00e4 0x03e8 0x0770 0x06 0x00 +#define IMX94_PAD_GPIO_IO53__SINC4_MOD_CLK1 0x00e4 0x03e8 0x0000 0x07 0x00 + +#define IMX94_PAD_GPIO_IO54__GPIO3_IO22 0x00e8 0x03ec 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO54__NETC_1588MUX_INOUT4 0x00e8 0x03ec 0x065c 0x01 0x00 +#define IMX94_PAD_GPIO_IO54__CAN4_TX 0x00e8 0x03ec 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO54__LPIT3_TRIGGER2 0x00e8 0x03ec 0x0764 0x03 0x01 +#define IMX94_PAD_GPIO_IO54__LPSPI6_PCS1 0x00e8 0x03ec 0x0774 0x04 0x01 +#define IMX94_PAD_GPIO_IO54__TPM3_CH3 0x00e8 0x03ec 0x0838 0x05 0x01 +#define IMX94_PAD_GPIO_IO54__SINC3_EMCLK0 0x00e8 0x03ec 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO54__XBAR1_XBAR_INOUT18 0x00e8 0x03ec 0x08a4 0x07 0x00 + +#define IMX94_PAD_GPIO_IO55__GPIO3_IO23 0x00ec 0x03f0 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO55__NETC_1588MUX_INOUT5 0x00ec 0x03f0 0x0660 0x01 0x00 +#define IMX94_PAD_GPIO_IO55__CAN4_RX 0x00ec 0x03f0 0x0684 0x02 0x01 +#define IMX94_PAD_GPIO_IO55__LPIT2_TRIGGER2 0x00ec 0x03f0 0x0760 0x03 0x01 +#define IMX94_PAD_GPIO_IO55__LPSPI7_PCS1 0x00ec 0x03f0 0x0778 0x04 0x01 +#define IMX94_PAD_GPIO_IO55__TPM4_CH3 0x00ec 0x03f0 0x083c 0x05 0x01 +#define IMX94_PAD_GPIO_IO55__SINC3_EMBIT0 0x00ec 0x03f0 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO55__XBAR1_XBAR_INOUT19 0x00ec 0x03f0 0x08a8 0x07 0x00 + +#define IMX94_PAD_GPIO_IO56__GPIO3_IO24 0x00f0 0x03f4 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO56__NETC_1588MUX_INOUT6 0x00f0 0x03f4 0x0664 0x01 0x00 +#define IMX94_PAD_GPIO_IO56__CAN5_TX 0x00f0 0x03f4 0x0000 0x02 0x00 +#define IMX94_PAD_GPIO_IO56__LPIT3_TRIGGER3 0x00f0 0x03f4 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO56__LPSPI8_PCS1 0x00f0 0x03f4 0x077c 0x04 0x01 +#define IMX94_PAD_GPIO_IO56__SAI3_TX_SYNC 0x00f0 0x03f4 0x0804 0x05 0x01 +#define IMX94_PAD_GPIO_IO56__SINC3_EMCLK1 0x00f0 0x03f4 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO56__XBAR1_XBAR_INOUT20 0x00f0 0x03f4 0x08ac 0x07 0x00 + +#define IMX94_PAD_GPIO_IO57__GPIO3_IO25 0x00f4 0x03f8 0x0000 0x00 0x00 +#define IMX94_PAD_GPIO_IO57__NETC_1588MUX_INOUT7 0x00f4 0x03f8 0x0668 0x01 0x00 +#define IMX94_PAD_GPIO_IO57__CAN5_RX 0x00f4 0x03f8 0x0688 0x02 0x02 +#define IMX94_PAD_GPIO_IO57__LPIT2_TRIGGER3 0x00f4 0x03f8 0x0000 0x03 0x00 +#define IMX94_PAD_GPIO_IO57__LPSPI5_PCS1 0x00f4 0x03f8 0x0770 0x04 0x01 +#define IMX94_PAD_GPIO_IO57__TPM6_CH3 0x00f4 0x03f8 0x084c 0x05 0x01 +#define IMX94_PAD_GPIO_IO57__SINC3_EMBIT1 0x00f4 0x03f8 0x0000 0x06 0x00 +#define IMX94_PAD_GPIO_IO57__ENET_REF_CLK_ROOT 0x00f4 0x03f8 0x0000 0x07 0x00 + +#define IMX94_PAD_CCM_CLKO1__CLKO_1 0x00f8 0x03fc 0x0000 0x00 0x00 +#define IMX94_PAD_CCM_CLKO1__NETC_1588MUX_INOUT8 0x00f8 0x03fc 0x066c 0x01 0x00 +#define IMX94_PAD_CCM_CLKO1__LPUART9_TX 0x00f8 0x03fc 0x07e4 0x02 0x01 +#define IMX94_PAD_CCM_CLKO1__ECAT_LED_RUN 0x00f8 0x03fc 0x0000 0x03 0x00 +#define IMX94_PAD_CCM_CLKO1__TPM6_EXTCLK 0x00f8 0x03fc 0x0850 0x04 0x01 +#define IMX94_PAD_CCM_CLKO1__GPIO4_IO0 0x00f8 0x03fc 0x0000 0x05 0x00 +#define IMX94_PAD_CCM_CLKO1__SINC3_EMCLK2 0x00f8 0x03fc 0x0000 0x06 0x00 +#define IMX94_PAD_CCM_CLKO1__XBAR1_XBAR_INOUT22 0x00f8 0x03fc 0x0000 0x07 0x00 + +#define IMX94_PAD_CCM_CLKO2__CLKO_2 0x00fc 0x0400 0x0000 0x00 0x00 +#define IMX94_PAD_CCM_CLKO2__NETC_1588MUX_INOUT9 0x00fc 0x0400 0x0670 0x01 0x00 +#define IMX94_PAD_CCM_CLKO2__LPUART9_RX 0x00fc 0x0400 0x07e0 0x02 0x01 +#define IMX94_PAD_CCM_CLKO2__ECAT_LED_ERR 0x00fc 0x0400 0x0000 0x03 0x00 +#define IMX94_PAD_CCM_CLKO2__TPM5_CH1 0x00fc 0x0400 0x0840 0x04 0x01 +#define IMX94_PAD_CCM_CLKO2__GPIO4_IO1 0x00fc 0x0400 0x0000 0x05 0x00 +#define IMX94_PAD_CCM_CLKO2__SINC3_EMBIT2 0x00fc 0x0400 0x0000 0x06 0x00 +#define IMX94_PAD_CCM_CLKO2__XBAR1_XBAR_INOUT23 0x00fc 0x0400 0x0000 0x07 0x00 + +#define IMX94_PAD_CCM_CLKO3__CLKO_3 0x0100 0x0404 0x0000 0x00 0x00 +#define IMX94_PAD_CCM_CLKO3__NETC_1588MUX_INOUT10 0x0100 0x0404 0x0674 0x01 0x00 +#define IMX94_PAD_CCM_CLKO3__CAN3_TX 0x0100 0x0404 0x0000 0x02 0x00 +#define IMX94_PAD_CCM_CLKO3__ECAT_LED_STATE_RUN 0x0100 0x0404 0x0000 0x03 0x00 +#define IMX94_PAD_CCM_CLKO3__TPM6_CH1 0x0100 0x0404 0x0848 0x04 0x01 +#define IMX94_PAD_CCM_CLKO3__GPIO4_IO2 0x0100 0x0404 0x0000 0x05 0x00 +#define IMX94_PAD_CCM_CLKO3__SINC3_EMCLK3 0x0100 0x0404 0x0000 0x06 0x00 +#define IMX94_PAD_CCM_CLKO3__ENET_REF_CLK_ROOT 0x0100 0x0404 0x0000 0x07 0x00 + +#define IMX94_PAD_CCM_CLKO4__CLKO_4 0x0104 0x0408 0x0000 0x00 0x00 +#define IMX94_PAD_CCM_CLKO4__NETC_1588MUX_INOUT11 0x0104 0x0408 0x0000 0x01 0x00 +#define IMX94_PAD_CCM_CLKO4__CAN3_RX 0x0104 0x0408 0x0680 0x02 0x01 +#define IMX94_PAD_CCM_CLKO4__ECAT_RESET_OUT 0x0104 0x0408 0x0000 0x03 0x00 +#define IMX94_PAD_CCM_CLKO4__TPM5_CH3 0x0104 0x0408 0x0844 0x04 0x01 +#define IMX94_PAD_CCM_CLKO4__GPIO4_IO3 0x0104 0x0408 0x0000 0x05 0x00 +#define IMX94_PAD_CCM_CLKO4__SINC3_EMBIT3 0x0104 0x0408 0x0000 0x06 0x00 +#define IMX94_PAD_CCM_CLKO4__XBAR1_XBAR_INOUT25 0x0104 0x0408 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH2_MDC_GPIO1__NETC_EMDC 0x0108 0x040c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_MDC_GPIO1__NETC_ETH2_SLV_MDC 0x0108 0x040c 0x0000 0x01 0x00 +#define IMX94_PAD_ETH2_MDC_GPIO1__I3C2_SCL 0x0108 0x040c 0x0720 0x02 0x02 +#define IMX94_PAD_ETH2_MDC_GPIO1__USB1_OTG_ID 0x0108 0x040c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH2_MDC_GPIO1__FLEXIO2_FLEXIO0 0x0108 0x040c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_MDC_GPIO1__GPIO6_IO0 0x0108 0x040c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_MDC_GPIO1__FLEXPWM2_PWMX0 0x0108 0x040c 0x06a0 0x06 0x01 +#define IMX94_PAD_ETH2_MDC_GPIO1__XBAR1_XBAR_INOUT30 0x0108 0x040c 0x08b0 0x07 0x01 + +#define IMX94_PAD_ETH2_MDIO_GPIO2__NETC_EMDIO 0x010c 0x0410 0x0678 0x00 0x00 +#define IMX94_PAD_ETH2_MDIO_GPIO2__NETC_ETH2_SLV_MDIO 0x010c 0x0410 0x0000 0x01 0x00 +#define IMX94_PAD_ETH2_MDIO_GPIO2__I3C2_SDA 0x010c 0x0410 0x0724 0x02 0x02 +#define IMX94_PAD_ETH2_MDIO_GPIO2__USB1_OTG_PWR 0x010c 0x0410 0x0000 0x03 0x00 +#define IMX94_PAD_ETH2_MDIO_GPIO2__FLEXIO2_FLEXIO1 0x010c 0x0410 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_MDIO_GPIO2__GPIO6_IO1 0x010c 0x0410 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_MDIO_GPIO2__FLEXPWM2_PWMX1 0x010c 0x0410 0x06a4 0x06 0x01 +#define IMX94_PAD_ETH2_MDIO_GPIO2__XBAR1_XBAR_INOUT31 0x010c 0x0410 0x08b4 0x07 0x01 + +#define IMX94_PAD_ETH2_TXD3__NETC_PINMUX_ETH2_TXD3 0x0110 0x0414 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_TXD3__LPUART3_DCD_B 0x0110 0x0414 0x0000 0x01 0x00 +#define IMX94_PAD_ETH2_TXD3__CAN2_TX 0x0110 0x0414 0x0000 0x02 0x00 +#define IMX94_PAD_ETH2_TXD3__USB2_OTG_ID 0x0110 0x0414 0x0000 0x03 0x00 +#define IMX94_PAD_ETH2_TXD3__FLEXIO2_FLEXIO2 0x0110 0x0414 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_TXD3__GPIO6_IO2 0x0110 0x0414 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_TXD3__FLEXPWM2_PWMA0 0x0110 0x0414 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_TXD3__XBAR1_XBAR_INOUT32 0x0110 0x0414 0x08b8 0x07 0x01 + +#define IMX94_PAD_ETH2_TXD2__NETC_PINMUX_ETH2_TXD2 0x0114 0x0418 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_TXD2__ETH2_RMII_REF50_CLK 0x0114 0x0418 0x0000 0x01 0x00 +#define IMX94_PAD_ETH2_TXD2__CAN2_RX 0x0114 0x0418 0x067c 0x02 0x03 +#define IMX94_PAD_ETH2_TXD2__USB2_OTG_OC 0x0114 0x0418 0x0000 0x03 0x00 +#define IMX94_PAD_ETH2_TXD2__FLEXIO2_FLEXIO3 0x0114 0x0418 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_TXD2__GPIO6_IO3 0x0114 0x0418 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_TXD2__FLEXPWM2_PWMB0 0x0114 0x0418 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_TXD2__XBAR1_XBAR_INOUT33 0x0114 0x0418 0x08bc 0x07 0x01 + +#define IMX94_PAD_ETH2_TXD1__NETC_PINMUX_ETH2_TXD1 0x0118 0x041c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_TXD1__LPUART3_RTS_B 0x0118 0x041c 0x0000 0x01 0x00 +#define IMX94_PAD_ETH2_TXD1__ECAT_CLK25 0x0118 0x041c 0x0000 0x02 0x00 +#define IMX94_PAD_ETH2_TXD1__USB1_OTG_OC 0x0118 0x041c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH2_TXD1__FLEXIO2_FLEXIO4 0x0118 0x041c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_TXD1__GPIO6_IO4 0x0118 0x041c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_TXD1__FLEXPWM2_PWMA1 0x0118 0x041c 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_TXD1__XBAR1_XBAR_INOUT34 0x0118 0x041c 0x08c0 0x07 0x01 + +#define IMX94_PAD_ETH2_TXD0__NETC_PINMUX_ETH2_TXD0 0x011c 0x0420 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_TXD0__LPUART3_TX 0x011c 0x0420 0x07a8 0x01 0x02 +#define IMX94_PAD_ETH2_TXD0__I3C2_PUR 0x011c 0x0420 0x0000 0x02 0x00 +#define IMX94_PAD_ETH2_TXD0__I3C2_PUR_B 0x011c 0x0420 0x0000 0x03 0x00 +#define IMX94_PAD_ETH2_TXD0__FLEXIO2_FLEXIO5 0x011c 0x0420 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_TXD0__GPIO6_IO5 0x011c 0x0420 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_TXD0__FLEXPWM2_PWMB1 0x011c 0x0420 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_TXD0__XBAR1_XBAR_INOUT35 0x011c 0x0420 0x08c4 0x07 0x01 + +#define IMX94_PAD_ETH2_TX_CTL__NETC_PINMUX_ETH2_TX_CTL 0x0120 0x0424 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_TX_CTL__LPUART3_DTR_B 0x0120 0x0424 0x0000 0x01 0x00 +#define IMX94_PAD_ETH2_TX_CTL__ECAT_LED_RUN 0x0120 0x0424 0x0000 0x02 0x00 +#define IMX94_PAD_ETH2_TX_CTL__FLEXIO2_FLEXIO6 0x0120 0x0424 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_TX_CTL__GPIO6_IO6 0x0120 0x0424 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_TX_CTL__FLEXPWM2_PWMA2 0x0120 0x0424 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_TX_CTL__XBAR1_XBAR_INOUT36 0x0120 0x0424 0x08c8 0x07 0x01 + +#define IMX94_PAD_ETH2_TX_CLK__NETC_PINMUX_ETH2_TX_CLK 0x0124 0x0428 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_TX_CLK__ECAT_LED_ERR 0x0124 0x0428 0x0000 0x02 0x00 +#define IMX94_PAD_ETH2_TX_CLK__FLEXIO2_FLEXIO7 0x0124 0x0428 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_TX_CLK__GPIO6_IO7 0x0124 0x0428 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_TX_CLK__FLEXPWM2_PWMB2 0x0124 0x0428 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_TX_CLK__XBAR1_XBAR_INOUT37 0x0124 0x0428 0x08cc 0x07 0x01 + +#define IMX94_PAD_ETH2_RX_CTL__NETC_PINMUX_ETH2_RX_CTL 0x0128 0x042c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_RX_CTL__LPUART3_DSR_B 0x0128 0x042c 0x0000 0x01 0x00 +#define IMX94_PAD_ETH2_RX_CTL__ECAT_LED_STATE_RUN 0x0128 0x042c 0x0000 0x02 0x00 +#define IMX94_PAD_ETH2_RX_CTL__USB2_OTG_PWR 0x0128 0x042c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH2_RX_CTL__FLEXIO2_FLEXIO8 0x0128 0x042c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_RX_CTL__GPIO6_IO8 0x0128 0x042c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_RX_CTL__FLEXPWM2_PWMA3 0x0128 0x042c 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_RX_CTL__SINC4_EMCLK0 0x0128 0x042c 0x082c 0x07 0x01 + +#define IMX94_PAD_ETH2_RX_CLK__NETC_PINMUX_ETH2_RX_CLK 0x012c 0x0430 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_RX_CLK__LPUART3_RIN_B 0x012c 0x0430 0x0000 0x01 0x00 +#define IMX94_PAD_ETH2_RX_CLK__ECAT_RESET_OUT 0x012c 0x0430 0x0000 0x02 0x00 +#define IMX94_PAD_ETH2_RX_CLK__XBAR1_XBAR_INOUT38 0x012c 0x0430 0x08d0 0x03 0x01 +#define IMX94_PAD_ETH2_RX_CLK__FLEXIO2_FLEXIO9 0x012c 0x0430 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_RX_CLK__GPIO6_IO9 0x012c 0x0430 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_RX_CLK__FLEXPWM2_PWMB3 0x012c 0x0430 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_RX_CLK__SINC4_EMBIT0 0x012c 0x0430 0x0820 0x07 0x01 + +#define IMX94_PAD_ETH2_RXD0__NETC_PINMUX_ETH2_RXD0 0x0130 0x0434 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_RXD0__LPUART3_RX 0x0130 0x0434 0x07a4 0x01 0x02 +#define IMX94_PAD_ETH2_RXD0__FLEXIO2_FLEXIO10 0x0130 0x0434 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_RXD0__GPIO6_IO10 0x0130 0x0434 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_RXD0__DIG_ENCODER2_DATA_EN 0x0130 0x0434 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_RXD0__XBAR1_XBAR_INOUT39 0x0130 0x0434 0x08d4 0x07 0x01 + +#define IMX94_PAD_ETH2_RXD1__NETC_PINMUX_ETH2_RXD1 0x0134 0x0438 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_RXD1__LPUART3_CTS_B 0x0134 0x0438 0x07a0 0x01 0x01 +#define IMX94_PAD_ETH2_RXD1__LPTMR2_ALT0 0x0134 0x0438 0x0780 0x03 0x00 +#define IMX94_PAD_ETH2_RXD1__FLEXIO2_FLEXIO11 0x0134 0x0438 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_RXD1__GPIO6_IO11 0x0134 0x0438 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_RXD1__DIG_ENCODER2_DATA_CLK 0x0134 0x0438 0x068c 0x06 0x00 +#define IMX94_PAD_ETH2_RXD1__XBAR1_XBAR_INOUT40 0x0134 0x0438 0x08d8 0x07 0x01 + +#define IMX94_PAD_ETH2_RXD2__NETC_PINMUX_ETH2_RXD2 0x0138 0x043c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_RXD2__LPTMR2_ALT1 0x0138 0x043c 0x0784 0x03 0x00 +#define IMX94_PAD_ETH2_RXD2__FLEXIO2_FLEXIO12 0x0138 0x043c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_RXD2__GPIO6_IO12 0x0138 0x043c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_RXD2__DIG_ENCODER2_DATA_OUT 0x0138 0x043c 0x0000 0x06 0x00 +#define IMX94_PAD_ETH2_RXD2__XBAR1_XBAR_INOUT41 0x0138 0x043c 0x08dc 0x07 0x01 + +#define IMX94_PAD_ETH2_RXD3__NETC_PINMUX_ETH2_RXD3 0x013c 0x0440 0x0000 0x00 0x00 +#define IMX94_PAD_ETH2_RXD3__LPTMR2_ALT2 0x013c 0x0440 0x0788 0x03 0x00 +#define IMX94_PAD_ETH2_RXD3__FLEXIO2_FLEXIO13 0x013c 0x0440 0x0000 0x04 0x00 +#define IMX94_PAD_ETH2_RXD3__GPIO6_IO13 0x013c 0x0440 0x0000 0x05 0x00 +#define IMX94_PAD_ETH2_RXD3__DIG_ENCODER2_DATA_IN 0x013c 0x0440 0x0690 0x06 0x00 +#define IMX94_PAD_ETH2_RXD3__XBAR1_XBAR_INOUT42 0x013c 0x0440 0x08e0 0x07 0x01 + +#define IMX94_PAD_ETH3_MDC_GPIO1__NETC_EMDC 0x0140 0x0444 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_MDC_GPIO1__LPUART4_DCD_B 0x0140 0x0444 0x0000 0x01 0x00 +#define IMX94_PAD_ETH3_MDC_GPIO1__NETC_ETH3_SLV_MDC 0x0140 0x0444 0x0000 0x02 0x00 +#define IMX94_PAD_ETH3_MDC_GPIO1__SAI4_TX_SYNC 0x0140 0x0444 0x081c 0x03 0x00 +#define IMX94_PAD_ETH3_MDC_GPIO1__FLEXIO2_FLEXIO14 0x0140 0x0444 0x0000 0x04 0x00 +#define IMX94_PAD_ETH3_MDC_GPIO1__GPIO6_IO14 0x0140 0x0444 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_MDC_GPIO1__FLEXPWM1_PWMX0 0x0140 0x0444 0x0698 0x06 0x01 +#define IMX94_PAD_ETH3_MDC_GPIO1__SINC4_MOD_CLK0 0x0140 0x0444 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH3_MDIO_GPIO2__NETC_EMDIO 0x0144 0x0448 0x0678 0x00 0x01 +#define IMX94_PAD_ETH3_MDIO_GPIO2__LPUART4_RIN_B 0x0144 0x0448 0x0000 0x01 0x00 +#define IMX94_PAD_ETH3_MDIO_GPIO2__NETC_ETH3_SLV_MDIO 0x0144 0x0448 0x0000 0x02 0x00 +#define IMX94_PAD_ETH3_MDIO_GPIO2__SAI4_TX_BCLK 0x0144 0x0448 0x0818 0x03 0x00 +#define IMX94_PAD_ETH3_MDIO_GPIO2__FLEXIO2_FLEXIO15 0x0144 0x0448 0x0000 0x04 0x00 +#define IMX94_PAD_ETH3_MDIO_GPIO2__GPIO6_IO15 0x0144 0x0448 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_MDIO_GPIO2__FLEXPWM1_PWMX1 0x0144 0x0448 0x069c 0x06 0x01 +#define IMX94_PAD_ETH3_MDIO_GPIO2__SINC4_MOD_CLK1 0x0144 0x0448 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3 0x0148 0x044c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_TXD3__XSPI_SLV_DATA7 0x0148 0x044c 0x0924 0x02 0x00 +#define IMX94_PAD_ETH3_TXD3__SAI4_TX_DATA0 0x0148 0x044c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH3_TXD3__LPUART3_TX 0x0148 0x044c 0x07a8 0x04 0x03 +#define IMX94_PAD_ETH3_TXD3__GPIO6_IO16 0x0148 0x044c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_TXD3__FLEXPWM1_PWMA0 0x0148 0x044c 0x0000 0x06 0x00 + +#define IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2 0x014c 0x0450 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_TXD2__ETH3_RMII_REF50_CLK 0x014c 0x0450 0x0000 0x01 0x00 +#define IMX94_PAD_ETH3_TXD2__XSPI_SLV_DATA6 0x014c 0x0450 0x0920 0x02 0x00 +#define IMX94_PAD_ETH3_TXD2__SAI4_RX_SYNC 0x014c 0x0450 0x0814 0x03 0x00 +#define IMX94_PAD_ETH3_TXD2__GPIO6_IO17 0x014c 0x0450 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_TXD2__FLEXPWM1_PWMB0 0x014c 0x0450 0x0000 0x06 0x00 + +#define IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1 0x0150 0x0454 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_TXD1__LPUART4_RTS_B 0x0150 0x0454 0x0000 0x01 0x00 +#define IMX94_PAD_ETH3_TXD1__XSPI_SLV_DATA5 0x0150 0x0454 0x091c 0x02 0x00 +#define IMX94_PAD_ETH3_TXD1__SAI4_RX_BCLK 0x0150 0x0454 0x080c 0x03 0x00 +#define IMX94_PAD_ETH3_TXD1__GPIO6_IO18 0x0150 0x0454 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_TXD1__FLEXPWM1_PWMA1 0x0150 0x0454 0x0000 0x06 0x00 + +#define IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0 0x0154 0x0458 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_TXD0__LPUART4_TX 0x0154 0x0458 0x07b4 0x01 0x02 +#define IMX94_PAD_ETH3_TXD0__XSPI_SLV_DATA4 0x0154 0x0458 0x0918 0x02 0x00 +#define IMX94_PAD_ETH3_TXD0__SAI4_RX_DATA0 0x0154 0x0458 0x0810 0x03 0x00 +#define IMX94_PAD_ETH3_TXD0__GPIO6_IO19 0x0154 0x0458 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_TXD0__FLEXPWM1_PWMB1 0x0154 0x0458 0x0000 0x06 0x00 + +#define IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL 0x0158 0x045c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_TX_CTL__LPUART4_DTR_B 0x0158 0x045c 0x0000 0x01 0x00 +#define IMX94_PAD_ETH3_TX_CTL__XSPI_SLV_DQS 0x0158 0x045c 0x0900 0x02 0x00 +#define IMX94_PAD_ETH3_TX_CTL__SAI4_MCLK 0x0158 0x045c 0x0808 0x03 0x00 +#define IMX94_PAD_ETH3_TX_CTL__LPUART3_RX 0x0158 0x045c 0x07a4 0x04 0x03 +#define IMX94_PAD_ETH3_TX_CTL__GPIO6_IO20 0x0158 0x045c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_TX_CTL__FLEXPWM1_PWMA2 0x0158 0x045c 0x0000 0x06 0x00 + +#define IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK 0x015c 0x0460 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_TX_CLK__XSPI_SLV_CLK 0x015c 0x0460 0x0904 0x02 0x00 +#define IMX94_PAD_ETH3_TX_CLK__SAI2_TX_SYNC 0x015c 0x0460 0x07fc 0x03 0x01 +#define IMX94_PAD_ETH3_TX_CLK__LPUART3_CTS_B 0x015c 0x0460 0x07a0 0x04 0x02 +#define IMX94_PAD_ETH3_TX_CLK__GPIO6_IO21 0x015c 0x0460 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_TX_CLK__FLEXPWM1_PWMB2 0x015c 0x0460 0x0000 0x06 0x00 + +#define IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL 0x0160 0x0464 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_RX_CTL__LPUART4_DSR_B 0x0160 0x0464 0x0000 0x01 0x00 +#define IMX94_PAD_ETH3_RX_CTL__XSPI_SLV_CS 0x0160 0x0464 0x08fc 0x02 0x00 +#define IMX94_PAD_ETH3_RX_CTL__SAI2_TX_BCLK 0x0160 0x0464 0x07f8 0x03 0x01 +#define IMX94_PAD_ETH3_RX_CTL__XBAR1_XBAR_INOUT43 0x0160 0x0464 0x08e4 0x04 0x01 +#define IMX94_PAD_ETH3_RX_CTL__GPIO6_IO22 0x0160 0x0464 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_RX_CTL__FLEXPWM1_PWMA3 0x0160 0x0464 0x0000 0x06 0x00 +#define IMX94_PAD_ETH3_RX_CTL__SINC4_EMCLK1 0x0160 0x0464 0x0830 0x07 0x01 + +#define IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK 0x0164 0x0468 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_RX_CLK__LPUART4_CTS_B 0x0164 0x0468 0x07ac 0x01 0x01 +#define IMX94_PAD_ETH3_RX_CLK__XSPI_SLV_DATA3 0x0164 0x0468 0x0914 0x02 0x00 +#define IMX94_PAD_ETH3_RX_CLK__SAI2_TX_DATA0 0x0164 0x0468 0x0000 0x03 0x00 +#define IMX94_PAD_ETH3_RX_CLK__XBAR1_XBAR_INOUT44 0x0164 0x0468 0x08e8 0x04 0x01 +#define IMX94_PAD_ETH3_RX_CLK__GPIO6_IO23 0x0164 0x0468 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_RX_CLK__FLEXPWM1_PWMB3 0x0164 0x0468 0x0000 0x06 0x00 +#define IMX94_PAD_ETH3_RX_CLK__SINC4_EMBIT1 0x0164 0x0468 0x0824 0x07 0x01 + +#define IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0 0x0168 0x046c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_RXD0__LPUART4_RX 0x0168 0x046c 0x07b0 0x01 0x02 +#define IMX94_PAD_ETH3_RXD0__XSPI_SLV_DATA2 0x0168 0x046c 0x0910 0x02 0x00 +#define IMX94_PAD_ETH3_RXD0__SAI2_RX_SYNC 0x0168 0x046c 0x07f4 0x03 0x01 +#define IMX94_PAD_ETH3_RXD0__GPIO6_IO24 0x0168 0x046c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_RXD0__DIG_ENCODER1_DATA_EN 0x0168 0x046c 0x0000 0x06 0x00 +#define IMX94_PAD_ETH3_RXD0__XBAR1_XBAR_INOUT45 0x0168 0x046c 0x08ec 0x07 0x01 + +#define IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1 0x016c 0x0470 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_RXD1__XSPI_SLV_DATA1 0x016c 0x0470 0x090c 0x02 0x00 +#define IMX94_PAD_ETH3_RXD1__SAI2_RX_BCLK 0x016c 0x0470 0x07ec 0x03 0x01 +#define IMX94_PAD_ETH3_RXD1__LPUART3_RTS_B 0x016c 0x0470 0x0000 0x04 0x00 +#define IMX94_PAD_ETH3_RXD1__GPIO6_IO25 0x016c 0x0470 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_RXD1__DIG_ENCODER1_DATA_CLK 0x016c 0x0470 0x0000 0x06 0x00 +#define IMX94_PAD_ETH3_RXD1__XBAR1_XBAR_INOUT46 0x016c 0x0470 0x08f0 0x07 0x01 + +#define IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2 0x0170 0x0474 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_RXD2__MQS2_RIGHT 0x0170 0x0474 0x0000 0x01 0x00 +#define IMX94_PAD_ETH3_RXD2__XSPI_SLV_DATA0 0x0170 0x0474 0x0908 0x02 0x00 +#define IMX94_PAD_ETH3_RXD2__SAI2_RX_DATA0 0x0170 0x0474 0x07f0 0x03 0x01 +#define IMX94_PAD_ETH3_RXD2__GPIO6_IO26 0x0170 0x0474 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_RXD2__DIG_ENCODER1_DATA_OUT 0x0170 0x0474 0x0000 0x06 0x00 +#define IMX94_PAD_ETH3_RXD2__XBAR1_XBAR_INOUT47 0x0170 0x0474 0x08f4 0x07 0x01 + +#define IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3 0x0174 0x0478 0x0000 0x00 0x00 +#define IMX94_PAD_ETH3_RXD3__MQS2_LEFT 0x0174 0x0478 0x0000 0x01 0x00 +#define IMX94_PAD_ETH3_RXD3__SAI2_MCLK 0x0174 0x0478 0x07e8 0x03 0x01 +#define IMX94_PAD_ETH3_RXD3__GPIO6_IO27 0x0174 0x0478 0x0000 0x05 0x00 +#define IMX94_PAD_ETH3_RXD3__DIG_ENCODER1_DATA_IN 0x0174 0x0478 0x0000 0x06 0x00 +#define IMX94_PAD_ETH3_RXD3__XBAR1_XBAR_INOUT48 0x0174 0x0478 0x08f8 0x07 0x01 + +#define IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC 0x0178 0x047c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH4_MDC_GPIO1__ECAT_MDC 0x0178 0x047c 0x0000 0x01 0x00 +#define IMX94_PAD_ETH4_MDC_GPIO1__ECAT_CLK25 0x0178 0x047c 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_MDC_GPIO1__NETC_ETH4_SLV_MDC 0x0178 0x047c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_MDC_GPIO1__FLEXIO1_3_2_FLEXIO12 0x0178 0x047c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_MDC_GPIO1__GPIO6_IO28 0x0178 0x047c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_MDC_GPIO1__FLEXPWM4_PWMX0 0x0178 0x047c 0x06f4 0x06 0x02 +#define IMX94_PAD_ETH4_MDC_GPIO1__SINC4_MOD_CLK2 0x0178 0x047c 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO 0x017c 0x0480 0x0678 0x00 0x02 +#define IMX94_PAD_ETH4_MDIO_GPIO2__ECAT_MDIO 0x017c 0x0480 0x0628 0x01 0x00 +#define IMX94_PAD_ETH4_MDIO_GPIO2__ENET_REF_CLK_ROOT 0x017c 0x0480 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_MDIO_GPIO2__NETC_ETH4_SLV_MDIO 0x017c 0x0480 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_MDIO_GPIO2__FLEXIO1_3_2_FLEXIO13 0x017c 0x0480 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_MDIO_GPIO2__GPIO6_IO29 0x017c 0x0480 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_MDIO_GPIO2__FLEXPWM4_PWMX1 0x017c 0x0480 0x06f8 0x06 0x02 +#define IMX94_PAD_ETH4_MDIO_GPIO2__SINC_FILTER_GLUE4_BREAK 0x017c 0x0480 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x0180 0x0484 0x0648 0x00 0x00 +#define IMX94_PAD_ETH4_TX_CLK__USDHC3_CLK 0x0180 0x0484 0x0000 0x01 0x00 +#define IMX94_PAD_ETH4_TX_CLK__XSPI2_A_SCLK 0x0180 0x0484 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_TX_CLK__ECAT_LED_ERR 0x0180 0x0484 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_TX_CLK__FLEXIO1_3_2_FLEXIO0 0x0180 0x0484 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_TX_CLK__GPIO6_IO30 0x0180 0x0484 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_TX_CLK__FLEXPWM4_PWMA0 0x0180 0x0484 0x06d4 0x06 0x01 +#define IMX94_PAD_ETH4_TX_CLK__XBAR1_XBAR_INOUT30 0x0180 0x0484 0x08b0 0x07 0x02 + +#define IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL 0x0184 0x0488 0x0000 0x00 0x00 +#define IMX94_PAD_ETH4_TX_CTL__USDHC3_CMD 0x0184 0x0488 0x0858 0x01 0x01 +#define IMX94_PAD_ETH4_TX_CTL__XSPI2_A_SS0_B 0x0184 0x0488 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_TX_CTL__ECAT_RESET_OUT 0x0184 0x0488 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_TX_CTL__FLEXIO1_3_2_FLEXIO1 0x0184 0x0488 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_TX_CTL__GPIO6_IO31 0x0184 0x0488 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_TX_CTL__FLEXPWM4_PWMB0 0x0184 0x0488 0x06e4 0x06 0x01 +#define IMX94_PAD_ETH4_TX_CTL__XBAR1_XBAR_INOUT31 0x0184 0x0488 0x08b4 0x07 0x02 + +#define IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0 0x0188 0x048c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH4_TXD0__USDHC3_DATA0 0x0188 0x048c 0x085c 0x01 0x01 +#define IMX94_PAD_ETH4_TXD0__XSPI2_A_DATA0 0x0188 0x048c 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_TXD0__ECAT_LED_RUN 0x0188 0x048c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_TXD0__FLEXIO1_3_2_FLEXIO2 0x0188 0x048c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_TXD0__GPIO7_IO0 0x0188 0x048c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_TXD0__FLEXPWM4_PWMA1 0x0188 0x048c 0x06d8 0x06 0x01 +#define IMX94_PAD_ETH4_TXD0__XBAR1_XBAR_INOUT32 0x0188 0x048c 0x08b8 0x07 0x02 + +#define IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1 0x018c 0x0490 0x0000 0x00 0x00 +#define IMX94_PAD_ETH4_TXD1__USDHC3_DATA1 0x018c 0x0490 0x0860 0x01 0x01 +#define IMX94_PAD_ETH4_TXD1__XSPI2_A_DATA1 0x018c 0x0490 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_TXD1__ECAT_LED_STATE_RUN 0x018c 0x0490 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_TXD1__FLEXIO1_3_2_FLEXIO3 0x018c 0x0490 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_TXD1__GPIO7_IO1 0x018c 0x0490 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_TXD1__FLEXPWM4_PWMB1 0x018c 0x0490 0x06e8 0x06 0x01 +#define IMX94_PAD_ETH4_TXD1__XBAR1_XBAR_INOUT33 0x018c 0x0490 0x08bc 0x07 0x02 + +#define IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2 0x0190 0x0494 0x0000 0x00 0x00 +#define IMX94_PAD_ETH4_TXD2__USDHC3_DATA2 0x0190 0x0494 0x0864 0x01 0x01 +#define IMX94_PAD_ETH4_TXD2__XSPI2_A_DATA2 0x0190 0x0494 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_TXD2__ECAT_CLK25 0x0190 0x0494 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_TXD2__FLEXIO1_3_2_FLEXIO4 0x0190 0x0494 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_TXD2__GPIO7_IO2 0x0190 0x0494 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_TXD2__FLEXPWM4_PWMA2 0x0190 0x0494 0x06dc 0x06 0x01 +#define IMX94_PAD_ETH4_TXD2__ETH4_RMII_REF50_CLK 0x0190 0x0494 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x0194 0x0498 0x0000 0x00 0x00 +#define IMX94_PAD_ETH4_TXD3__USDHC3_DATA3 0x0194 0x0498 0x0868 0x01 0x01 +#define IMX94_PAD_ETH4_TXD3__XSPI2_A_DATA3 0x0194 0x0498 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_TXD3__FLEXIO1_3_2_FLEXIO5 0x0194 0x0498 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_TXD3__GPIO7_IO3 0x0194 0x0498 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_TXD3__FLEXPWM4_PWMB2 0x0194 0x0498 0x06ec 0x06 0x01 +#define IMX94_PAD_ETH4_TXD3__XBAR1_XBAR_INOUT35 0x0194 0x0498 0x08c4 0x07 0x02 + +#define IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0 0x0198 0x049c 0x0638 0x00 0x00 +#define IMX94_PAD_ETH4_RXD0__XSPI2_A_DATA4 0x0198 0x049c 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_RXD0__FLEXIO1_3_2_FLEXIO6 0x0198 0x049c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_RXD0__GPIO7_IO4 0x0198 0x049c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_RXD0__FLEXPWM4_PWMA3 0x0198 0x049c 0x06e0 0x06 0x01 +#define IMX94_PAD_ETH4_RXD0__SINC4_EMCLK2 0x0198 0x049c 0x0834 0x07 0x01 + +#define IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1 0x019c 0x04a0 0x063c 0x00 0x00 +#define IMX94_PAD_ETH4_RXD1__XSPI2_A_DATA5 0x019c 0x04a0 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_RXD1__FLEXIO2_4_1_FLEXIO11 0x019c 0x04a0 0x0694 0x03 0x00 +#define IMX94_PAD_ETH4_RXD1__FLEXIO1_3_2_FLEXIO7 0x019c 0x04a0 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_RXD1__GPIO7_IO5 0x019c 0x04a0 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_RXD1__FLEXPWM4_PWMB3 0x019c 0x04a0 0x06f0 0x06 0x01 +#define IMX94_PAD_ETH4_RXD1__SINC4_EMBIT2 0x019c 0x04a0 0x0828 0x07 0x01 + +#define IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2 0x01a0 0x04a4 0x0640 0x00 0x00 +#define IMX94_PAD_ETH4_RXD2__XSPI2_A_DATA6 0x01a0 0x04a4 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_RXD2__FLEXIO2_4_1_FLEXIO12 0x01a0 0x04a4 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_RXD2__FLEXIO1_3_2_FLEXIO8 0x01a0 0x04a4 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_RXD2__GPIO7_IO6 0x01a0 0x04a4 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_RXD2__DIG_ENCODER2_DATA_EN 0x01a0 0x04a4 0x0000 0x06 0x00 +#define IMX94_PAD_ETH4_RXD2__XBAR1_XBAR_INOUT4 0x01a0 0x04a4 0x086c 0x07 0x01 + +#define IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x01a4 0x04a8 0x0644 0x00 0x00 +#define IMX94_PAD_ETH4_RXD3__ENET_REF_CLK_ROOT 0x01a4 0x04a8 0x0000 0x01 0x00 +#define IMX94_PAD_ETH4_RXD3__XSPI2_A_DATA7 0x01a4 0x04a8 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_RXD3__FLEXIO2_4_1_FLEXIO13 0x01a4 0x04a8 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_RXD3__FLEXIO1_3_2_FLEXIO9 0x01a4 0x04a8 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_RXD3__GPIO7_IO7 0x01a4 0x04a8 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_RXD3__DIG_ENCODER2_DATA_CLK 0x01a4 0x04a8 0x068c 0x06 0x01 +#define IMX94_PAD_ETH4_RXD3__XBAR1_XBAR_INOUT5 0x01a4 0x04a8 0x0870 0x07 0x01 + +#define IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL 0x01a8 0x04ac 0x0634 0x00 0x00 +#define IMX94_PAD_ETH4_RX_CTL__XSPI2_A_SS1_B 0x01a8 0x04ac 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_RX_CTL__FLEXIO2_4_1_FLEXIO14 0x01a8 0x04ac 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_RX_CTL__FLEXIO1_3_2_FLEXIO10 0x01a8 0x04ac 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_RX_CTL__GPIO7_IO8 0x01a8 0x04ac 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_RX_CTL__DIG_ENCODER2_DATA_OUT 0x01a8 0x04ac 0x0000 0x06 0x00 +#define IMX94_PAD_ETH4_RX_CTL__XBAR1_XBAR_INOUT6 0x01a8 0x04ac 0x0874 0x07 0x01 + +#define IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x01ac 0x04b0 0x0630 0x00 0x00 +#define IMX94_PAD_ETH4_RX_CLK__XSPI2_A_DQS 0x01ac 0x04b0 0x0000 0x02 0x00 +#define IMX94_PAD_ETH4_RX_CLK__FLEXIO2_4_1_FLEXIO15 0x01ac 0x04b0 0x0000 0x03 0x00 +#define IMX94_PAD_ETH4_RX_CLK__FLEXIO1_3_2_FLEXIO11 0x01ac 0x04b0 0x0000 0x04 0x00 +#define IMX94_PAD_ETH4_RX_CLK__GPIO7_IO9 0x01ac 0x04b0 0x0000 0x05 0x00 +#define IMX94_PAD_ETH4_RX_CLK__DIG_ENCODER2_DATA_IN 0x01ac 0x04b0 0x0690 0x06 0x01 +#define IMX94_PAD_ETH4_RX_CLK__XBAR1_XBAR_INOUT7 0x01ac 0x04b0 0x0878 0x07 0x01 + +#define IMX94_PAD_ETH0_TXD0__NETC_PINMUX_ETH0_TXD0 0x01b0 0x04b4 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_TXD0__ECAT_PT0_TXD0 0x01b0 0x04b4 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_TXD0__FLEXIO4_FLEXIO0 0x01b0 0x04b4 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_TXD0__GPIO5_IO0 0x01b0 0x04b4 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_TXD1__NETC_PINMUX_ETH0_TXD1 0x01b4 0x04b8 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_TXD1__ECAT_PT0_TXD1 0x01b4 0x04b8 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_TXD1__FLEXIO4_FLEXIO1 0x01b4 0x04b8 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_TXD1__GPIO5_IO1 0x01b4 0x04b8 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_TX_EN__NETC_PINMUX_ETH0_TX_EN 0x01b8 0x04bc 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_TX_EN__ECAT_PT0_TX_EN 0x01b8 0x04bc 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_TX_EN__FLEXIO4_FLEXIO2 0x01b8 0x04bc 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_TX_EN__GPIO5_IO2 0x01b8 0x04bc 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_TX_CLK__NETC_PINMUX_ETH0_TX_CLK 0x01bc 0x04c0 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_TX_CLK__ECAT_PT0_TX_CLK 0x01bc 0x04c0 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_TX_CLK__FLEXIO4_FLEXIO3 0x01bc 0x04c0 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_TX_CLK__GPIO5_IO3 0x01bc 0x04c0 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_RXD0__NETC_PINMUX_ETH0_RXD0 0x01c0 0x04c4 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_RXD0__ECAT_PT0_RXD0 0x01c0 0x04c4 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_RXD0__FLEXIO4_FLEXIO4 0x01c0 0x04c4 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_RXD0__GPIO5_IO4 0x01c0 0x04c4 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_RXD1__NETC_PINMUX_ETH0_RXD1 0x01c4 0x04c8 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_RXD1__ECAT_PT0_RXD1 0x01c4 0x04c8 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_RXD1__FLEXIO4_FLEXIO5 0x01c4 0x04c8 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_RXD1__GPIO5_IO5 0x01c4 0x04c8 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_RX_DV__NETC_PINMUX_ETH0_RX_DV 0x01c8 0x04cc 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_RX_DV__ECAT_PT0_RX_DV 0x01c8 0x04cc 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_RX_DV__FLEXIO4_FLEXIO6 0x01c8 0x04cc 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_RX_DV__GPIO5_IO6 0x01c8 0x04cc 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_TXD2__NETC_PINMUX_ETH0_TXD2 0x01cc 0x04d0 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_TXD2__ECAT_PT0_TXD2 0x01cc 0x04d0 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_TXD2__ETH0_RMII_REF50_CLK 0x01cc 0x04d0 0x0000 0x02 0x00 +#define IMX94_PAD_ETH0_TXD2__FLEXIO4_FLEXIO7 0x01cc 0x04d0 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_TXD2__GPIO5_IO7 0x01cc 0x04d0 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_TXD3__NETC_PINMUX_ETH0_TXD3 0x01d0 0x04d4 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_TXD3__ECAT_PT0_TXD3 0x01d0 0x04d4 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_TXD3__FLEXIO4_FLEXIO8 0x01d0 0x04d4 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_TXD3__GPIO5_IO8 0x01d0 0x04d4 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_RXD2__NETC_PINMUX_ETH0_RXD2 0x01d4 0x04d8 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_RXD2__ECAT_PT0_RXD2 0x01d4 0x04d8 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_RXD2__FLEXIO4_FLEXIO9 0x01d4 0x04d8 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_RXD2__GPIO5_IO9 0x01d4 0x04d8 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_RXD3__NETC_PINMUX_ETH0_RXD3 0x01d8 0x04dc 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_RXD3__ECAT_PT0_RXD3 0x01d8 0x04dc 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_RXD3__FLEXIO4_FLEXIO10 0x01d8 0x04dc 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_RXD3__GPIO5_IO10 0x01d8 0x04dc 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_RX_CLK__NETC_PINMUX_ETH0_RX_CLK 0x01dc 0x04e0 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_RX_CLK__ECAT_PT0_RX_CLK 0x01dc 0x04e0 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_RX_CLK__FLEXIO4_FLEXIO11 0x01dc 0x04e0 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_RX_CLK__GPIO5_IO11 0x01dc 0x04e0 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_RX_ER__NETC_PINMUX_ETH0_RX_ER 0x01e0 0x04e4 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_RX_ER__ECAT_PT0_RX_ER 0x01e0 0x04e4 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_RX_ER__FLEXIO4_FLEXIO12 0x01e0 0x04e4 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_RX_ER__GPIO5_IO12 0x01e0 0x04e4 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_TX_ER__NETC_PINMUX_ETH0_TX_ER 0x01e4 0x04e8 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_TX_ER__ECAT_LINK_ACT0 0x01e4 0x04e8 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_TX_ER__FLEXIO4_FLEXIO13 0x01e4 0x04e8 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_TX_ER__GPIO5_IO13 0x01e4 0x04e8 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH0_CRS__NETC_PINMUX_ETH0_CRS 0x01e8 0x04ec 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_CRS__ECAT_LINK0 0x01e8 0x04ec 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_CRS__NETC_EMDC 0x01e8 0x04ec 0x0000 0x02 0x00 +#define IMX94_PAD_ETH0_CRS__FLEXIO4_FLEXIO14 0x01e8 0x04ec 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_CRS__GPIO5_IO14 0x01e8 0x04ec 0x0000 0x05 0x00 +#define IMX94_PAD_ETH0_CRS__XBAR1_XBAR_INOUT8 0x01e8 0x04ec 0x087c 0x06 0x02 +#define IMX94_PAD_ETH0_CRS__SINC_FILTER_GLUE2_BREAK 0x01e8 0x04ec 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH0_COL__NETC_PINMUX_ETH0_COL 0x01ec 0x04f0 0x0000 0x00 0x00 +#define IMX94_PAD_ETH0_COL__ECAT_LINK1 0x01ec 0x04f0 0x0000 0x01 0x00 +#define IMX94_PAD_ETH0_COL__NETC_EMDIO 0x01ec 0x04f0 0x0678 0x02 0x03 +#define IMX94_PAD_ETH0_COL__FLEXIO4_FLEXIO15 0x01ec 0x04f0 0x0000 0x04 0x00 +#define IMX94_PAD_ETH0_COL__GPIO5_IO15 0x01ec 0x04f0 0x0000 0x05 0x00 +#define IMX94_PAD_ETH0_COL__XBAR1_XBAR_INOUT9 0x01ec 0x04f0 0x0880 0x06 0x02 +#define IMX94_PAD_ETH0_COL__SINC_FILTER_GLUE1_BREAK 0x01ec 0x04f0 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH1_TXD0__NETC_PINMUX_ETH1_TXD0 0x01f0 0x04f4 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_TXD0__ECAT_PT1_TXD0 0x01f0 0x04f4 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_TXD0__ENCODER_DIAG0 0x01f0 0x04f4 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_TXD0__FLEXIO3_FLEXIO0 0x01f0 0x04f4 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_TXD0__GPIO5_IO16 0x01f0 0x04f4 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_TXD1__NETC_PINMUX_ETH1_TXD1 0x01f4 0x04f8 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_TXD1__ECAT_PT1_TXD1 0x01f4 0x04f8 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_TXD1__ENCODER_DIAG1 0x01f4 0x04f8 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_TXD1__FLEXIO3_FLEXIO1 0x01f4 0x04f8 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_TXD1__GPIO5_IO17 0x01f4 0x04f8 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_TX_EN__NETC_PINMUX_ETH1_TX_EN 0x01f8 0x04fc 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_TX_EN__ECAT_PT1_TX_EN 0x01f8 0x04fc 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_TX_EN__ENCODER_DIAG2 0x01f8 0x04fc 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_TX_EN__FLEXIO3_FLEXIO2 0x01f8 0x04fc 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_TX_EN__GPIO5_IO18 0x01f8 0x04fc 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_TX_CLK__NETC_PINMUX_ETH1_TX_CLK 0x01fc 0x0500 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_TX_CLK__ECAT_PT1_TX_CLK 0x01fc 0x0500 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_TX_CLK__ENCODER_DIAG3 0x01fc 0x0500 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_TX_CLK__FLEXIO3_FLEXIO3 0x01fc 0x0500 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_TX_CLK__GPIO5_IO19 0x01fc 0x0500 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_RXD0__NETC_PINMUX_ETH1_RXD0 0x0200 0x0504 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_RXD0__ECAT_PT1_RXD0 0x0200 0x0504 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_RXD0__ENCODER_DIAG4 0x0200 0x0504 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_RXD0__FLEXIO3_FLEXIO4 0x0200 0x0504 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_RXD0__GPIO5_IO20 0x0200 0x0504 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_RXD1__NETC_PINMUX_ETH1_RXD1 0x0204 0x0508 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_RXD1__ECAT_PT1_RXD1 0x0204 0x0508 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_RXD1__ENCODER_DIAG5 0x0204 0x0508 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_RXD1__FLEXIO3_FLEXIO5 0x0204 0x0508 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_RXD1__GPIO5_IO21 0x0204 0x0508 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_RX_DV__NETC_PINMUX_ETH1_RX_DV 0x0208 0x050c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_RX_DV__ECAT_PT1_RX_DV 0x0208 0x050c 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_RX_DV__ENCODER_DIAG6 0x0208 0x050c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_RX_DV__FLEXIO3_FLEXIO6 0x0208 0x050c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_RX_DV__GPIO5_IO22 0x0208 0x050c 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_TXD2__NETC_PINMUX_ETH1_TXD2 0x020c 0x0510 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_TXD2__ECAT_PT1_TXD2 0x020c 0x0510 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_TXD2__ETH1_RMII_REF50_CLK 0x020c 0x0510 0x0000 0x02 0x00 +#define IMX94_PAD_ETH1_TXD2__ENCODER_DIAG7 0x020c 0x0510 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_TXD2__FLEXIO3_FLEXIO7 0x020c 0x0510 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_TXD2__GPIO5_IO23 0x020c 0x0510 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_TXD3__NETC_PINMUX_ETH1_TXD3 0x0210 0x0514 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_TXD3__ECAT_PT1_TXD3 0x0210 0x0514 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_TXD3__ENCODER_DIAG8 0x0210 0x0514 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_TXD3__FLEXIO3_FLEXIO8 0x0210 0x0514 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_TXD3__GPIO5_IO24 0x0210 0x0514 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_RXD2__NETC_PINMUX_ETH1_RXD2 0x0214 0x0518 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_RXD2__ECAT_PT1_RXD2 0x0214 0x0518 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_RXD2__ENCODER_DIAG9 0x0214 0x0518 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_RXD2__FLEXIO3_FLEXIO9 0x0214 0x0518 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_RXD2__GPIO5_IO25 0x0214 0x0518 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_RXD3__NETC_PINMUX_ETH1_RXD3 0x0218 0x051c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_RXD3__ECAT_PT1_RXD3 0x0218 0x051c 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_RXD3__ENCODER_DIAG10 0x0218 0x051c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_RXD3__FLEXIO3_FLEXIO10 0x0218 0x051c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_RXD3__GPIO5_IO26 0x0218 0x051c 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_RX_CLK__NETC_PINMUX_ETH1_RX_CLK 0x021c 0x0520 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_RX_CLK__ECAT_PT1_RX_CLK 0x021c 0x0520 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_RX_CLK__ENCODER_DIAG11 0x021c 0x0520 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_RX_CLK__FLEXIO3_FLEXIO11 0x021c 0x0520 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_RX_CLK__GPIO5_IO27 0x021c 0x0520 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_RX_ER__NETC_PINMUX_ETH1_RX_ER 0x0220 0x0524 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_RX_ER__ECAT_PT1_RX_ER 0x0220 0x0524 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_RX_ER__ENCODER_DIAG12 0x0220 0x0524 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_RX_ER__FLEXIO3_FLEXIO12 0x0220 0x0524 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_RX_ER__GPIO5_IO28 0x0220 0x0524 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_TX_ER__NETC_PINMUX_ETH1_TX_ER 0x0224 0x0528 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_TX_ER__ECAT_LINK_ACT1 0x0224 0x0528 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_TX_ER__ENCODER_DIAG13 0x0224 0x0528 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_TX_ER__FLEXIO3_FLEXIO13 0x0224 0x0528 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_TX_ER__GPIO5_IO29 0x0224 0x0528 0x0000 0x05 0x00 + +#define IMX94_PAD_ETH1_CRS__NETC_PINMUX_ETH1_CRS 0x0228 0x052c 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_CRS__ECAT_MDC 0x0228 0x052c 0x0000 0x01 0x00 +#define IMX94_PAD_ETH1_CRS__NETC_EMDC 0x0228 0x052c 0x0000 0x02 0x00 +#define IMX94_PAD_ETH1_CRS__ENCODER_DIAG14 0x0228 0x052c 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_CRS__FLEXIO3_FLEXIO14 0x0228 0x052c 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_CRS__GPIO5_IO30 0x0228 0x052c 0x0000 0x05 0x00 +#define IMX94_PAD_ETH1_CRS__XBAR1_XBAR_INOUT10 0x0228 0x052c 0x0884 0x06 0x02 +#define IMX94_PAD_ETH1_CRS__SINC_FILTER_GLUE1_BREAK 0x0228 0x052c 0x0000 0x07 0x00 + +#define IMX94_PAD_ETH1_COL__NETC_PINMUX_ETH1_COL 0x022c 0x0530 0x0000 0x00 0x00 +#define IMX94_PAD_ETH1_COL__ECAT_MDIO 0x022c 0x0530 0x0628 0x01 0x01 +#define IMX94_PAD_ETH1_COL__NETC_EMDIO 0x022c 0x0530 0x0678 0x02 0x04 +#define IMX94_PAD_ETH1_COL__ENCODER_DIAG15 0x022c 0x0530 0x0000 0x03 0x00 +#define IMX94_PAD_ETH1_COL__FLEXIO3_FLEXIO15 0x022c 0x0530 0x0000 0x04 0x00 +#define IMX94_PAD_ETH1_COL__GPIO5_IO31 0x022c 0x0530 0x0000 0x05 0x00 +#define IMX94_PAD_ETH1_COL__XBAR1_XBAR_INOUT11 0x022c 0x0530 0x0888 0x06 0x02 +#define IMX94_PAD_ETH1_COL__SINC_FILTER_GLUE2_BREAK 0x022c 0x0530 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_CLK__USDHC1_CLK 0x0230 0x0534 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_CLK__SAI4_TX_BCLK 0x0230 0x0534 0x0818 0x01 0x01 +#define IMX94_PAD_SD1_CLK__CAN4_TX 0x0230 0x0534 0x0000 0x02 0x00 +#define IMX94_PAD_SD1_CLK__NETC_1588MUX_INOUT0 0x0230 0x0534 0x064c 0x03 0x01 +#define IMX94_PAD_SD1_CLK__FLEXIO2_4_1_FLEXIO0 0x0230 0x0534 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_CLK__GPIO4_IO8 0x0230 0x0534 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_CLK__FLEXPWM3_PWMX0 0x0230 0x0534 0x06c8 0x06 0x02 +#define IMX94_PAD_SD1_CLK__SINC1_EMCLK0 0x0230 0x0534 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_CMD__USDHC1_CMD 0x0234 0x0538 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_CMD__SAI4_RX_BCLK 0x0234 0x0538 0x080c 0x01 0x01 +#define IMX94_PAD_SD1_CMD__CAN4_RX 0x0234 0x0538 0x0684 0x02 0x02 +#define IMX94_PAD_SD1_CMD__NETC_1588MUX_INOUT1 0x0234 0x0538 0x0650 0x03 0x01 +#define IMX94_PAD_SD1_CMD__FLEXIO2_4_1_FLEXIO1 0x0234 0x0538 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_CMD__GPIO4_IO9 0x0234 0x0538 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_CMD__FLEXPWM3_PWMX1 0x0234 0x0538 0x06cc 0x06 0x02 +#define IMX94_PAD_SD1_CMD__SINC1_EMBIT0 0x0234 0x0538 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x0238 0x053c 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_DATA0__SAI4_RX_SYNC 0x0238 0x053c 0x0814 0x01 0x01 +#define IMX94_PAD_SD1_DATA0__CAN5_TX 0x0238 0x053c 0x0000 0x02 0x00 +#define IMX94_PAD_SD1_DATA0__NETC_1588MUX_INOUT2 0x0238 0x053c 0x0654 0x03 0x01 +#define IMX94_PAD_SD1_DATA0__FLEXIO2_4_1_FLEXIO2 0x0238 0x053c 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_DATA0__GPIO4_IO10 0x0238 0x053c 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_DATA0__FLEXPWM3_PWMX2 0x0238 0x053c 0x06d0 0x06 0x01 +#define IMX94_PAD_SD1_DATA0__SINC1_EMCLK1 0x0238 0x053c 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x023c 0x0540 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_DATA1__SAI4_TX_SYNC 0x023c 0x0540 0x081c 0x01 0x01 +#define IMX94_PAD_SD1_DATA1__CAN5_RX 0x023c 0x0540 0x0688 0x02 0x03 +#define IMX94_PAD_SD1_DATA1__NETC_1588MUX_INOUT3 0x023c 0x0540 0x0658 0x03 0x01 +#define IMX94_PAD_SD1_DATA1__FLEXIO2_4_1_FLEXIO3 0x023c 0x0540 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_DATA1__GPIO4_IO11 0x023c 0x0540 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_DATA1__FLEXPWM3_PWMA3 0x023c 0x0540 0x06b4 0x06 0x01 +#define IMX94_PAD_SD1_DATA1__SINC1_EMBIT1 0x023c 0x0540 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x0240 0x0544 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_DATA2__SAI4_TX_DATA0 0x0240 0x0544 0x0000 0x01 0x00 +#define IMX94_PAD_SD1_DATA2__PMIC_READY 0x0240 0x0544 0x0000 0x02 0x00 +#define IMX94_PAD_SD1_DATA2__NETC_1588MUX_INOUT4 0x0240 0x0544 0x065c 0x03 0x01 +#define IMX94_PAD_SD1_DATA2__FLEXIO2_4_1_FLEXIO4 0x0240 0x0544 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_DATA2__GPIO4_IO12 0x0240 0x0544 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_DATA2__FLEXPWM3_PWMB3 0x0240 0x0544 0x06c4 0x06 0x01 +#define IMX94_PAD_SD1_DATA2__SINC1_EMCLK2 0x0240 0x0544 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x0244 0x0548 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_DATA3__SAI4_RX_DATA0 0x0244 0x0548 0x0810 0x01 0x01 +#define IMX94_PAD_SD1_DATA3__NETC_1588MUX_INOUT5 0x0244 0x0548 0x0660 0x03 0x01 +#define IMX94_PAD_SD1_DATA3__FLEXIO2_4_1_FLEXIO5 0x0244 0x0548 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_DATA3__GPIO4_IO13 0x0244 0x0548 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_DATA3__FLEXPWM3_PWMA2 0x0244 0x0548 0x06b0 0x06 0x01 +#define IMX94_PAD_SD1_DATA3__SINC1_EMBIT2 0x0244 0x0548 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x0248 0x054c 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_DATA4__SAI2_RX_DATA0 0x0248 0x054c 0x07f0 0x01 0x02 +#define IMX94_PAD_SD1_DATA4__NETC_1588MUX_INOUT6 0x0248 0x054c 0x0664 0x03 0x01 +#define IMX94_PAD_SD1_DATA4__FLEXIO2_4_1_FLEXIO6 0x0248 0x054c 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_DATA4__GPIO4_IO14 0x0248 0x054c 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_DATA4__FLEXPWM3_PWMB2 0x0248 0x054c 0x06c0 0x06 0x01 +#define IMX94_PAD_SD1_DATA4__SINC1_EMCLK3 0x0248 0x054c 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x024c 0x0550 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_DATA5__SAI2_TX_DATA0 0x024c 0x0550 0x0000 0x01 0x00 +#define IMX94_PAD_SD1_DATA5__USDHC1_RESET_B 0x024c 0x0550 0x0000 0x02 0x00 +#define IMX94_PAD_SD1_DATA5__NETC_1588MUX_INOUT7 0x024c 0x0550 0x0668 0x03 0x01 +#define IMX94_PAD_SD1_DATA5__FLEXIO2_4_1_FLEXIO7 0x024c 0x0550 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_DATA5__GPIO4_IO15 0x024c 0x0550 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_DATA5__FLEXPWM3_PWMA1 0x024c 0x0550 0x06ac 0x06 0x01 +#define IMX94_PAD_SD1_DATA5__SINC1_EMBIT3 0x024c 0x0550 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x0250 0x0554 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_DATA6__SAI2_TX_BCLK 0x0250 0x0554 0x07f8 0x01 0x02 +#define IMX94_PAD_SD1_DATA6__USDHC1_CD_B 0x0250 0x0554 0x0000 0x02 0x00 +#define IMX94_PAD_SD1_DATA6__NETC_1588MUX_INOUT8 0x0250 0x0554 0x066c 0x03 0x01 +#define IMX94_PAD_SD1_DATA6__FLEXIO2_4_1_FLEXIO8 0x0250 0x0554 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_DATA6__GPIO4_IO16 0x0250 0x0554 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_DATA6__FLEXPWM3_PWMB1 0x0250 0x0554 0x06bc 0x06 0x01 +#define IMX94_PAD_SD1_DATA6__SINC1_MOD_CLK0 0x0250 0x0554 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x0254 0x0558 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_DATA7__SAI2_RX_SYNC 0x0254 0x0558 0x07f4 0x01 0x02 +#define IMX94_PAD_SD1_DATA7__USDHC1_WP 0x0254 0x0558 0x0000 0x02 0x00 +#define IMX94_PAD_SD1_DATA7__NETC_1588MUX_INOUT9 0x0254 0x0558 0x0670 0x03 0x01 +#define IMX94_PAD_SD1_DATA7__FLEXIO2_4_1_FLEXIO9 0x0254 0x0558 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_DATA7__GPIO4_IO17 0x0254 0x0558 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_DATA7__FLEXPWM3_PWMA0 0x0254 0x0558 0x06a8 0x06 0x01 +#define IMX94_PAD_SD1_DATA7__SINC1_MOD_CLK1 0x0254 0x0558 0x0000 0x07 0x00 + +#define IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x0258 0x055c 0x0000 0x00 0x00 +#define IMX94_PAD_SD1_STROBE__SAI2_TX_SYNC 0x0258 0x055c 0x07fc 0x01 0x02 +#define IMX94_PAD_SD1_STROBE__NETC_1588MUX_INOUT10 0x0258 0x055c 0x0674 0x03 0x01 +#define IMX94_PAD_SD1_STROBE__FLEXIO2_4_1_FLEXIO10 0x0258 0x055c 0x0000 0x04 0x00 +#define IMX94_PAD_SD1_STROBE__GPIO4_IO18 0x0258 0x055c 0x0000 0x05 0x00 +#define IMX94_PAD_SD1_STROBE__FLEXPWM3_PWMB0 0x0258 0x055c 0x06b8 0x06 0x01 +#define IMX94_PAD_SD1_STROBE__SINC1_MOD_CLK2 0x0258 0x055c 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x025c 0x0560 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_VSELECT__SAI4_MCLK 0x025c 0x0560 0x0808 0x01 0x01 +#define IMX94_PAD_SD2_VSELECT__USDHC2_WP 0x025c 0x0560 0x0854 0x02 0x02 +#define IMX94_PAD_SD2_VSELECT__NETC_1588MUX_INOUT10 0x025c 0x0560 0x0674 0x03 0x02 +#define IMX94_PAD_SD2_VSELECT__FLEXIO2_4_1_FLEXIO11 0x025c 0x0560 0x0694 0x04 0x01 +#define IMX94_PAD_SD2_VSELECT__GPIO4_IO19 0x025c 0x0560 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_VSELECT__EXT_CLK1 0x025c 0x0560 0x0624 0x06 0x01 +#define IMX94_PAD_SD2_VSELECT__XBAR1_XBAR_INOUT12 0x025c 0x0560 0x088c 0x07 0x02 + +#define IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0 0x0260 0x0564 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DATA0__SAI2_RX_SYNC 0x0260 0x0564 0x07f4 0x01 0x03 +#define IMX94_PAD_XSPI1_DATA0__XSPI_SLV_DATA0 0x0260 0x0564 0x0908 0x03 0x01 +#define IMX94_PAD_XSPI1_DATA0__FLEXIO1_3_3_FLEXIO0 0x0260 0x0564 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DATA0__GPIO7_IO16 0x0260 0x0564 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1 0x0264 0x0568 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DATA1__SAI2_TX_SYNC 0x0264 0x0568 0x07fc 0x01 0x03 +#define IMX94_PAD_XSPI1_DATA1__XSPI_SLV_DATA1 0x0264 0x0568 0x090c 0x03 0x01 +#define IMX94_PAD_XSPI1_DATA1__FLEXIO1_3_3_FLEXIO1 0x0264 0x0568 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DATA1__GPIO7_IO17 0x0264 0x0568 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2 0x0268 0x056c 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DATA2__SAI2_TX_DATA0 0x0268 0x056c 0x0000 0x01 0x00 +#define IMX94_PAD_XSPI1_DATA2__XSPI_SLV_DATA2 0x0268 0x056c 0x0910 0x03 0x01 +#define IMX94_PAD_XSPI1_DATA2__FLEXIO1_3_3_FLEXIO2 0x0268 0x056c 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DATA2__GPIO7_IO18 0x0268 0x056c 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3 0x026c 0x0570 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DATA3__SAI2_RX_DATA0 0x026c 0x0570 0x07f0 0x01 0x03 +#define IMX94_PAD_XSPI1_DATA3__SAI2_MCLK 0x026c 0x0570 0x07e8 0x02 0x02 +#define IMX94_PAD_XSPI1_DATA3__XSPI_SLV_DATA3 0x026c 0x0570 0x0914 0x03 0x01 +#define IMX94_PAD_XSPI1_DATA3__FLEXIO1_3_3_FLEXIO3 0x026c 0x0570 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DATA3__GPIO7_IO19 0x026c 0x0570 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4 0x0270 0x0574 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DATA4__SAI4_RX_SYNC 0x0270 0x0574 0x0814 0x01 0x02 +#define IMX94_PAD_XSPI1_DATA4__XSPI_SLV_DATA4 0x0270 0x0574 0x0918 0x03 0x01 +#define IMX94_PAD_XSPI1_DATA4__FLEXIO1_3_3_FLEXIO4 0x0270 0x0574 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DATA4__GPIO7_IO20 0x0270 0x0574 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5 0x0274 0x0578 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DATA5__SAI4_TX_SYNC 0x0274 0x0578 0x081c 0x01 0x02 +#define IMX94_PAD_XSPI1_DATA5__XSPI_SLV_DATA5 0x0274 0x0578 0x091c 0x03 0x01 +#define IMX94_PAD_XSPI1_DATA5__FLEXIO1_3_3_FLEXIO5 0x0274 0x0578 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DATA5__GPIO7_IO21 0x0274 0x0578 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6 0x0278 0x057c 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DATA6__SAI4_TX_DATA0 0x0278 0x057c 0x0000 0x01 0x00 +#define IMX94_PAD_XSPI1_DATA6__XSPI_SLV_DATA6 0x0278 0x057c 0x0920 0x03 0x01 +#define IMX94_PAD_XSPI1_DATA6__FLEXIO1_3_3_FLEXIO6 0x0278 0x057c 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DATA6__GPIO7_IO22 0x0278 0x057c 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7 0x027c 0x0580 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DATA7__SAI4_RX_DATA0 0x027c 0x0580 0x0810 0x01 0x02 +#define IMX94_PAD_XSPI1_DATA7__SAI4_MCLK 0x027c 0x0580 0x0808 0x02 0x02 +#define IMX94_PAD_XSPI1_DATA7__XSPI_SLV_DATA7 0x027c 0x0580 0x0924 0x03 0x01 +#define IMX94_PAD_XSPI1_DATA7__FLEXIO1_3_3_FLEXIO7 0x027c 0x0580 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DATA7__GPIO7_IO23 0x027c 0x0580 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x0280 0x0584 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_DQS__SAI2_TX_BCLK 0x0280 0x0584 0x07f8 0x01 0x03 +#define IMX94_PAD_XSPI1_DQS__XSPI_SLV_DQS 0x0280 0x0584 0x0900 0x03 0x01 +#define IMX94_PAD_XSPI1_DQS__FLEXIO1_3_3_FLEXIO8 0x0280 0x0584 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_DQS__GPIO7_IO24 0x0280 0x0584 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x0284 0x0588 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_SCLK__SAI4_TX_BCLK 0x0284 0x0588 0x0818 0x01 0x02 +#define IMX94_PAD_XSPI1_SCLK__XSPI_SLV_CLK 0x0284 0x0588 0x0904 0x03 0x01 +#define IMX94_PAD_XSPI1_SCLK__FLEXIO1_3_3_FLEXIO9 0x0284 0x0588 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_SCLK__GPIO7_IO25 0x0284 0x0588 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B 0x0288 0x058c 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 0x0288 0x058c 0x080c 0x01 0x02 +#define IMX94_PAD_XSPI1_SS0_B__XSPI_SLV_CS 0x0288 0x058c 0x08fc 0x03 0x01 +#define IMX94_PAD_XSPI1_SS0_B__FLEXIO1_3_3_FLEXIO10 0x0288 0x058c 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_SS0_B__GPIO7_IO26 0x0288 0x058c 0x0000 0x05 0x00 + +#define IMX94_PAD_XSPI1_SS1_B__XSPI1_A_SS1_B 0x028c 0x0590 0x0000 0x00 0x00 +#define IMX94_PAD_XSPI1_SS1_B__SAI2_RX_BCLK 0x028c 0x0590 0x07ec 0x01 0x02 +#define IMX94_PAD_XSPI1_SS1_B__FLEXPWM3_PWMX3 0x028c 0x0590 0x0000 0x03 0x00 +#define IMX94_PAD_XSPI1_SS1_B__FLEXIO1_3_3_FLEXIO11 0x028c 0x0590 0x0000 0x04 0x00 +#define IMX94_PAD_XSPI1_SS1_B__GPIO7_IO27 0x028c 0x0590 0x0000 0x05 0x00 +#define IMX94_PAD_XSPI1_SS1_B__SINC1_MOD_CLK0 0x028c 0x0590 0x0000 0x06 0x00 +#define IMX94_PAD_XSPI1_SS1_B__SINC_FILTER_GLUE1_BREAK 0x028c 0x0590 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_CD_B__USDHC2_CD_B 0x0290 0x0594 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_CD_B__NETC_PINMUX_ETH4_RX_CTL 0x0290 0x0594 0x0634 0x01 0x01 +#define IMX94_PAD_SD2_CD_B__I3C2_SCL 0x0290 0x0594 0x0720 0x02 0x03 +#define IMX94_PAD_SD2_CD_B__NETC_1588MUX_INOUT9 0x0290 0x0594 0x0670 0x03 0x02 +#define IMX94_PAD_SD2_CD_B__FLEXIO2_4_2_FLEXIO0 0x0290 0x0594 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_CD_B__GPIO4_IO20 0x0290 0x0594 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_CD_B__XBAR1_XBAR_INOUT13 0x0290 0x0594 0x0890 0x06 0x02 +#define IMX94_PAD_SD2_CD_B__SINC2_EMCLK0 0x0290 0x0594 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_CLK__USDHC2_CLK 0x0294 0x0598 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_CLK__NETC_PINMUX_ETH4_TX_CLK 0x0294 0x0598 0x0648 0x01 0x01 +#define IMX94_PAD_SD2_CLK__I3C2_SDA 0x0294 0x0598 0x0724 0x02 0x03 +#define IMX94_PAD_SD2_CLK__NETC_1588MUX_INOUT8 0x0294 0x0598 0x066c 0x03 0x02 +#define IMX94_PAD_SD2_CLK__FLEXIO2_4_2_FLEXIO1 0x0294 0x0598 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_CLK__GPIO4_IO21 0x0294 0x0598 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_CLK__OBSERVE0 0x0294 0x0598 0x0000 0x06 0x00 +#define IMX94_PAD_SD2_CLK__SINC2_EMBIT0 0x0294 0x0598 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_CMD__USDHC2_CMD 0x0298 0x059c 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_CMD__NETC_PINMUX_ETH4_TX_CTL 0x0298 0x059c 0x0000 0x01 0x00 +#define IMX94_PAD_SD2_CMD__I3C2_PUR 0x0298 0x059c 0x0000 0x02 0x00 +#define IMX94_PAD_SD2_CMD__I3C2_PUR_B 0x0298 0x059c 0x0000 0x03 0x00 +#define IMX94_PAD_SD2_CMD__FLEXIO2_4_2_FLEXIO2 0x0298 0x059c 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_CMD__GPIO4_IO22 0x0298 0x059c 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_CMD__OBSERVE1 0x0298 0x059c 0x0000 0x06 0x00 +#define IMX94_PAD_SD2_CMD__SINC2_EMCLK1 0x0298 0x059c 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x029c 0x05a0 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_DATA0__NETC_PINMUX_ETH4_TXD0 0x029c 0x05a0 0x0000 0x01 0x00 +#define IMX94_PAD_SD2_DATA0__CAN2_TX 0x029c 0x05a0 0x0000 0x02 0x00 +#define IMX94_PAD_SD2_DATA0__NETC_1588MUX_INOUT7 0x029c 0x05a0 0x0668 0x03 0x02 +#define IMX94_PAD_SD2_DATA0__FLEXIO2_4_2_FLEXIO3 0x029c 0x05a0 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_DATA0__GPIO4_IO23 0x029c 0x05a0 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_DATA0__OBSERVE2 0x029c 0x05a0 0x0000 0x06 0x00 +#define IMX94_PAD_SD2_DATA0__SINC2_EMBIT1 0x029c 0x05a0 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x02a0 0x05a4 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_DATA1__NETC_PINMUX_ETH4_TXD1 0x02a0 0x05a4 0x0000 0x01 0x00 +#define IMX94_PAD_SD2_DATA1__CAN2_RX 0x02a0 0x05a4 0x067c 0x02 0x04 +#define IMX94_PAD_SD2_DATA1__NETC_1588MUX_INOUT6 0x02a0 0x05a4 0x0664 0x03 0x02 +#define IMX94_PAD_SD2_DATA1__FLEXIO2_4_2_FLEXIO4 0x02a0 0x05a4 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_DATA1__GPIO4_IO24 0x02a0 0x05a4 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_DATA1__XBAR1_XBAR_INOUT14 0x02a0 0x05a4 0x0894 0x06 0x02 +#define IMX94_PAD_SD2_DATA1__SINC2_EMCLK2 0x02a0 0x05a4 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x02a4 0x05a8 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_DATA2__NETC_PINMUX_ETH4_TXD2 0x02a4 0x05a8 0x0000 0x01 0x00 +#define IMX94_PAD_SD2_DATA2__MQS2_RIGHT 0x02a4 0x05a8 0x0000 0x02 0x00 +#define IMX94_PAD_SD2_DATA2__NETC_1588MUX_INOUT5 0x02a4 0x05a8 0x0660 0x03 0x02 +#define IMX94_PAD_SD2_DATA2__FLEXIO2_4_2_FLEXIO5 0x02a4 0x05a8 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_DATA2__GPIO4_IO25 0x02a4 0x05a8 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_DATA2__XBAR1_XBAR_INOUT15 0x02a4 0x05a8 0x0898 0x06 0x01 +#define IMX94_PAD_SD2_DATA2__SINC2_EMBIT2 0x02a4 0x05a8 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x02a8 0x05ac 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_DATA3__NETC_PINMUX_ETH4_TXD3 0x02a8 0x05ac 0x0000 0x01 0x00 +#define IMX94_PAD_SD2_DATA3__MQS2_LEFT 0x02a8 0x05ac 0x0000 0x02 0x00 +#define IMX94_PAD_SD2_DATA3__LPTMR2_ALT0 0x02a8 0x05ac 0x0780 0x03 0x01 +#define IMX94_PAD_SD2_DATA3__FLEXIO2_4_2_FLEXIO6 0x02a8 0x05ac 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_DATA3__GPIO4_IO26 0x02a8 0x05ac 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_DATA3__XBAR1_XBAR_INOUT16 0x02a8 0x05ac 0x089c 0x06 0x01 +#define IMX94_PAD_SD2_DATA3__SINC2_EMCLK3 0x02a8 0x05ac 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_RESET_B__USDHC2_RESET_B 0x02ac 0x05b0 0x0000 0x00 0x00 +#define IMX94_PAD_SD2_RESET_B__NETC_PINMUX_ETH4_RXD0 0x02ac 0x05b0 0x0638 0x01 0x01 +#define IMX94_PAD_SD2_RESET_B__NETC_1588MUX_INOUT4 0x02ac 0x05b0 0x065c 0x02 0x02 +#define IMX94_PAD_SD2_RESET_B__LPTMR2_ALT1 0x02ac 0x05b0 0x0784 0x03 0x01 +#define IMX94_PAD_SD2_RESET_B__FLEXIO2_4_2_FLEXIO7 0x02ac 0x05b0 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x02ac 0x05b0 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_RESET_B__XBAR1_XBAR_INOUT17 0x02ac 0x05b0 0x08a0 0x06 0x01 +#define IMX94_PAD_SD2_RESET_B__SINC2_EMBIT3 0x02ac 0x05b0 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_GPIO0__USDHC2_WP 0x02b0 0x05b4 0x0854 0x00 0x03 +#define IMX94_PAD_SD2_GPIO0__NETC_PINMUX_ETH4_RXD1 0x02b0 0x05b4 0x063c 0x01 0x01 +#define IMX94_PAD_SD2_GPIO0__NETC_1588MUX_INOUT3 0x02b0 0x05b4 0x0658 0x03 0x02 +#define IMX94_PAD_SD2_GPIO0__FLEXIO2_4_2_FLEXIO8 0x02b0 0x05b4 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_GPIO0__GPIO4_IO28 0x02b0 0x05b4 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_GPIO0__XBAR1_XBAR_INOUT18 0x02b0 0x05b4 0x08a4 0x06 0x01 +#define IMX94_PAD_SD2_GPIO0__SINC2_MOD_CLK1 0x02b0 0x05b4 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_GPIO1__LPTMR2_ALT2 0x02b4 0x05b8 0x0788 0x00 0x01 +#define IMX94_PAD_SD2_GPIO1__NETC_PINMUX_ETH4_RXD2 0x02b4 0x05b8 0x0640 0x01 0x01 +#define IMX94_PAD_SD2_GPIO1__ECAT_CLK25 0x02b4 0x05b8 0x0000 0x02 0x00 +#define IMX94_PAD_SD2_GPIO1__NETC_1588MUX_INOUT2 0x02b4 0x05b8 0x0654 0x03 0x02 +#define IMX94_PAD_SD2_GPIO1__FLEXIO2_4_2_FLEXIO9 0x02b4 0x05b8 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_GPIO1__GPIO4_IO29 0x02b4 0x05b8 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_GPIO1__XBAR1_XBAR_INOUT19 0x02b4 0x05b8 0x08a8 0x06 0x01 +#define IMX94_PAD_SD2_GPIO1__SINC2_MOD_CLK0 0x02b4 0x05b8 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_GPIO2__NETC_PINMUX_ETH4_RXD3 0x02b8 0x05bc 0x0644 0x01 0x01 +#define IMX94_PAD_SD2_GPIO2__CAN5_TX 0x02b8 0x05bc 0x0000 0x02 0x00 +#define IMX94_PAD_SD2_GPIO2__NETC_1588MUX_INOUT1 0x02b8 0x05bc 0x0650 0x03 0x02 +#define IMX94_PAD_SD2_GPIO2__FLEXIO2_4_2_FLEXIO10 0x02b8 0x05bc 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_GPIO2__GPIO4_IO30 0x02b8 0x05bc 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_GPIO2__XBAR1_XBAR_INOUT20 0x02b8 0x05bc 0x08ac 0x06 0x01 +#define IMX94_PAD_SD2_GPIO2__SINC2_MOD_CLK2 0x02b8 0x05bc 0x0000 0x07 0x00 + +#define IMX94_PAD_SD2_GPIO3__NETC_PINMUX_ETH4_RX_CLK 0x02bc 0x05c0 0x0630 0x01 0x01 +#define IMX94_PAD_SD2_GPIO3__CAN5_RX 0x02bc 0x05c0 0x0688 0x02 0x04 +#define IMX94_PAD_SD2_GPIO3__NETC_1588MUX_INOUT0 0x02bc 0x05c0 0x064c 0x03 0x02 +#define IMX94_PAD_SD2_GPIO3__FLEXIO2_4_2_FLEXIO11 0x02bc 0x05c0 0x0000 0x04 0x00 +#define IMX94_PAD_SD2_GPIO3__GPIO4_IO31 0x02bc 0x05c0 0x0000 0x05 0x00 +#define IMX94_PAD_SD2_GPIO3__XBAR1_XBAR_INOUT21 0x02bc 0x05c0 0x0000 0x06 0x00 +#define IMX94_PAD_SD2_GPIO3__SINC_FILTER_GLUE2_BREAK 0x02bc 0x05c0 0x0000 0x07 0x00 + +#define IMX94_PAD_I2C1_SCL__LPI2C1_SCL 0x02c0 0x05c4 0x0000 0x00 0x00 +#define IMX94_PAD_I2C1_SCL__I3C1_SCL 0x02c0 0x05c4 0x0000 0x01 0x00 +#define IMX94_PAD_I2C1_SCL__LPUART1_DCD_B 0x02c0 0x05c4 0x0000 0x02 0x00 +#define IMX94_PAD_I2C1_SCL__TPM2_CH0 0x02c0 0x05c4 0x0000 0x03 0x00 +#define IMX94_PAD_I2C1_SCL__SAI1_RX_SYNC 0x02c0 0x05c4 0x0000 0x04 0x00 +#define IMX94_PAD_I2C1_SCL__GPIO1_IO0 0x02c0 0x05c4 0x0000 0x05 0x00 + +#define IMX94_PAD_I2C1_SDA__LPI2C1_SDA 0x02c4 0x05c8 0x0000 0x00 0x00 +#define IMX94_PAD_I2C1_SDA__I3C1_SDA 0x02c4 0x05c8 0x0000 0x01 0x00 +#define IMX94_PAD_I2C1_SDA__LPUART1_RIN_B 0x02c4 0x05c8 0x0000 0x02 0x00 +#define IMX94_PAD_I2C1_SDA__TPM2_CH1 0x02c4 0x05c8 0x0000 0x03 0x00 +#define IMX94_PAD_I2C1_SDA__SAI1_RX_BCLK 0x02c4 0x05c8 0x0000 0x04 0x00 +#define IMX94_PAD_I2C1_SDA__GPIO1_IO1 0x02c4 0x05c8 0x0000 0x05 0x00 + +#define IMX94_PAD_I2C2_SCL__LPI2C2_SCL 0x02c8 0x05cc 0x0000 0x00 0x00 +#define IMX94_PAD_I2C2_SCL__I3C1_PUR 0x02c8 0x05cc 0x0000 0x01 0x00 +#define IMX94_PAD_I2C2_SCL__LPUART2_DCD_B 0x02c8 0x05cc 0x0000 0x02 0x00 +#define IMX94_PAD_I2C2_SCL__TPM2_CH2 0x02c8 0x05cc 0x0000 0x03 0x00 +#define IMX94_PAD_I2C2_SCL__GPT1_CLK 0x02c8 0x05cc 0x060c 0x04 0x00 +#define IMX94_PAD_I2C2_SCL__GPIO1_IO2 0x02c8 0x05cc 0x0000 0x05 0x00 +#define IMX94_PAD_I2C2_SCL__I3C1_PUR_B 0x02c8 0x05cc 0x0000 0x06 0x00 +#define IMX94_PAD_I2C2_SCL__LPIT1_TRIGGER0 0x02c8 0x05cc 0x0000 0x07 0x00 + +#define IMX94_PAD_I2C2_SDA__LPI2C2_SDA 0x02cc 0x05d0 0x0000 0x00 0x00 +#define IMX94_PAD_I2C2_SDA__LPI2C1_HREQ 0x02cc 0x05d0 0x0000 0x01 0x00 +#define IMX94_PAD_I2C2_SDA__LPUART2_RIN_B 0x02cc 0x05d0 0x0000 0x02 0x00 +#define IMX94_PAD_I2C2_SDA__TPM2_CH3 0x02cc 0x05d0 0x0000 0x03 0x00 +#define IMX94_PAD_I2C2_SDA__SAI1_MCLK 0x02cc 0x05d0 0x0620 0x04 0x00 +#define IMX94_PAD_I2C2_SDA__GPIO1_IO3 0x02cc 0x05d0 0x0000 0x05 0x00 +#define IMX94_PAD_I2C2_SDA__EWM_OUT_B 0x02cc 0x05d0 0x0000 0x06 0x00 +#define IMX94_PAD_I2C2_SDA__LPIT1_TRIGGER1 0x02cc 0x05d0 0x0000 0x07 0x00 + +#define IMX94_PAD_UART1_RXD__LPUART1_RX 0x02d0 0x05d4 0x0000 0x00 0x00 +#define IMX94_PAD_UART1_RXD__S400_UART_RX 0x02d0 0x05d4 0x0000 0x01 0x00 +#define IMX94_PAD_UART1_RXD__LPSPI2_SIN 0x02d0 0x05d4 0x0000 0x02 0x00 +#define IMX94_PAD_UART1_RXD__TPM1_CH0 0x02d0 0x05d4 0x0000 0x03 0x00 +#define IMX94_PAD_UART1_RXD__GPT1_CAPTURE1 0x02d0 0x05d4 0x0000 0x04 0x00 +#define IMX94_PAD_UART1_RXD__GPIO1_IO4 0x02d0 0x05d4 0x0000 0x05 0x00 + +#define IMX94_PAD_UART1_TXD__LPUART1_TX 0x02d4 0x05d8 0x0000 0x00 0x00 +#define IMX94_PAD_UART1_TXD__S400_UART_TX 0x02d4 0x05d8 0x0000 0x01 0x00 +#define IMX94_PAD_UART1_TXD__LPSPI2_PCS0 0x02d4 0x05d8 0x0000 0x02 0x00 +#define IMX94_PAD_UART1_TXD__TPM1_CH1 0x02d4 0x05d8 0x0000 0x03 0x00 +#define IMX94_PAD_UART1_TXD__GPT1_COMPARE1 0x02d4 0x05d8 0x0000 0x04 0x00 +#define IMX94_PAD_UART1_TXD__GPIO1_IO5 0x02d4 0x05d8 0x0000 0x05 0x00 + +#define IMX94_PAD_UART2_RXD__LPUART2_RX 0x02d8 0x05dc 0x0000 0x00 0x00 +#define IMX94_PAD_UART2_RXD__LPUART1_CTS_B 0x02d8 0x05dc 0x0000 0x01 0x00 +#define IMX94_PAD_UART2_RXD__LPSPI2_SOUT 0x02d8 0x05dc 0x0000 0x02 0x00 +#define IMX94_PAD_UART2_RXD__TPM1_CH2 0x02d8 0x05dc 0x0000 0x03 0x00 +#define IMX94_PAD_UART2_RXD__SAI1_MCLK 0x02d8 0x05dc 0x0620 0x04 0x01 +#define IMX94_PAD_UART2_RXD__GPIO1_IO6 0x02d8 0x05dc 0x0000 0x05 0x00 +#define IMX94_PAD_UART2_RXD__GPT1_CLK 0x02d8 0x05dc 0x060c 0x06 0x01 +#define IMX94_PAD_UART2_RXD__LPIT1_TRIGGER2 0x02d8 0x05dc 0x0000 0x07 0x00 + +#define IMX94_PAD_UART2_TXD__LPUART2_TX 0x02dc 0x05e0 0x0000 0x00 0x00 +#define IMX94_PAD_UART2_TXD__LPUART1_RTS_B 0x02dc 0x05e0 0x0000 0x01 0x00 +#define IMX94_PAD_UART2_TXD__LPSPI2_SCK 0x02dc 0x05e0 0x0000 0x02 0x00 +#define IMX94_PAD_UART2_TXD__TPM1_CH3 0x02dc 0x05e0 0x0000 0x03 0x00 +#define IMX94_PAD_UART2_TXD__GPIO1_IO7 0x02dc 0x05e0 0x0000 0x05 0x00 + +#define IMX94_PAD_PDM_CLK__PDM_CLK 0x02e0 0x05e4 0x0000 0x00 0x00 +#define IMX94_PAD_PDM_CLK__MQS1_LEFT 0x02e0 0x05e4 0x0000 0x01 0x00 +#define IMX94_PAD_PDM_CLK__LPTMR1_ALT0 0x02e0 0x05e4 0x0000 0x04 0x00 +#define IMX94_PAD_PDM_CLK__GPIO1_IO8 0x02e0 0x05e4 0x0000 0x05 0x00 +#define IMX94_PAD_PDM_CLK__CAN1_TX 0x02e0 0x05e4 0x0000 0x06 0x00 +#define IMX94_PAD_PDM_CLK__EWM_OUT_B 0x02e0 0x05e4 0x0000 0x07 0x00 + +#define IMX94_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x02e4 0x05e8 0x0610 0x00 0x02 +#define IMX94_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x02e4 0x05e8 0x0000 0x01 0x00 +#define IMX94_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x02e4 0x05e8 0x0000 0x02 0x00 +#define IMX94_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x02e4 0x05e8 0x0000 0x03 0x00 +#define IMX94_PAD_PDM_BIT_STREAM0__LPTMR1_ALT1 0x02e4 0x05e8 0x0000 0x04 0x00 +#define IMX94_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x02e4 0x05e8 0x0000 0x05 0x00 +#define IMX94_PAD_PDM_BIT_STREAM0__CAN1_RX 0x02e4 0x05e8 0x0608 0x06 0x00 + +#define IMX94_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x02e8 0x05ec 0x0614 0x00 0x03 +#define IMX94_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x02e8 0x05ec 0x0000 0x01 0x00 +#define IMX94_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x02e8 0x05ec 0x0000 0x02 0x00 +#define IMX94_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x02e8 0x05ec 0x0000 0x03 0x00 +#define IMX94_PAD_PDM_BIT_STREAM1__LPTMR1_ALT2 0x02e8 0x05ec 0x0000 0x04 0x00 +#define IMX94_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x02e8 0x05ec 0x0000 0x05 0x00 +#define IMX94_PAD_PDM_BIT_STREAM1__EXT_CLK1 0x02e8 0x05ec 0x0624 0x06 0x00 + +#define IMX94_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x02ec 0x05f0 0x0000 0x00 0x00 +#define IMX94_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x02ec 0x05f0 0x0000 0x01 0x00 +#define IMX94_PAD_SAI1_TXFS__LPSPI1_PCS0 0x02ec 0x05f0 0x0000 0x02 0x00 +#define IMX94_PAD_SAI1_TXFS__LPUART2_DTR_B 0x02ec 0x05f0 0x0000 0x03 0x00 +#define IMX94_PAD_SAI1_TXFS__MQS1_LEFT 0x02ec 0x05f0 0x0000 0x04 0x00 +#define IMX94_PAD_SAI1_TXFS__GPIO1_IO11 0x02ec 0x05f0 0x0000 0x05 0x00 +#define IMX94_PAD_SAI1_TXFS__EWM_OUT_B 0x02ec 0x05f0 0x0000 0x06 0x00 + +#define IMX94_PAD_SAI1_TXC__SAI1_TX_BCLK 0x02f0 0x05f4 0x0000 0x00 0x00 +#define IMX94_PAD_SAI1_TXC__LPUART2_CTS_B 0x02f0 0x05f4 0x0000 0x01 0x00 +#define IMX94_PAD_SAI1_TXC__LPSPI1_SIN 0x02f0 0x05f4 0x0000 0x02 0x00 +#define IMX94_PAD_SAI1_TXC__LPUART1_DSR_B 0x02f0 0x05f4 0x0000 0x03 0x00 +#define IMX94_PAD_SAI1_TXC__CAN1_RX 0x02f0 0x05f4 0x0608 0x04 0x01 +#define IMX94_PAD_SAI1_TXC__GPIO1_IO12 0x02f0 0x05f4 0x0000 0x05 0x00 + +#define IMX94_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x02f4 0x05f8 0x0000 0x00 0x00 +#define IMX94_PAD_SAI1_TXD0__LPUART2_RTS_B 0x02f4 0x05f8 0x0000 0x01 0x00 +#define IMX94_PAD_SAI1_TXD0__LPSPI1_SCK 0x02f4 0x05f8 0x0000 0x02 0x00 +#define IMX94_PAD_SAI1_TXD0__LPUART1_DTR_B 0x02f4 0x05f8 0x0000 0x03 0x00 +#define IMX94_PAD_SAI1_TXD0__CAN1_TX 0x02f4 0x05f8 0x0000 0x04 0x00 +#define IMX94_PAD_SAI1_TXD0__GPIO1_IO13 0x02f4 0x05f8 0x0000 0x05 0x00 + +#define IMX94_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x02f8 0x05fc 0x0000 0x00 0x00 +#define IMX94_PAD_SAI1_RXD0__SAI1_MCLK 0x02f8 0x05fc 0x0620 0x01 0x02 +#define IMX94_PAD_SAI1_RXD0__LPSPI1_SOUT 0x02f8 0x05fc 0x0000 0x02 0x00 +#define IMX94_PAD_SAI1_RXD0__LPUART2_DSR_B 0x02f8 0x05fc 0x0000 0x03 0x00 +#define IMX94_PAD_SAI1_RXD0__MQS1_RIGHT 0x02f8 0x05fc 0x0000 0x04 0x00 +#define IMX94_PAD_SAI1_RXD0__GPIO1_IO14 0x02f8 0x05fc 0x0000 0x05 0x00 +#define IMX94_PAD_SAI1_RXD0__LPIT1_TRIGGER3 0x02f8 0x05fc 0x0000 0x07 0x00 + +#define IMX94_PAD_WDOG_ANY__WDOG_ANY 0x02fc 0x0600 0x0000 0x00 0x00 +#define IMX94_PAD_WDOG_ANY__FCCU_EOUT1 0x02fc 0x0600 0x0000 0x01 0x00 +#define IMX94_PAD_WDOG_ANY__GPIO1_IO15 0x02fc 0x0600 0x0000 0x05 0x00 +#endif /* __DTS_IMX94_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx94-power.h b/arch/arm64/boot/dts/freescale/imx94-power.h new file mode 100644 index 000000000000..5209afed60ed --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx94-power.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2024-2025 NXP + */ + +#ifndef __IMX94_POWER_H +#define __IMX94_POWER_H + +#define IMX94_PD_ANA 0 +#define IMX94_PD_AON 1 +#define IMX94_PD_BBSM 2 +#define IMX94_PD_M71 3 +#define IMX94_PD_CCMSRCGPC 4 +#define IMX94_PD_A55C0 5 +#define IMX94_PD_A55C1 6 +#define IMX94_PD_A55C2 7 +#define IMX94_PD_A55C3 8 +#define IMX94_PD_A55P 9 +#define IMX94_PD_DDR 10 +#define IMX94_PD_DISPLAY 11 +#define IMX94_PD_M70 12 +#define IMX94_PD_HSIO_TOP 13 +#define IMX94_PD_HSIO_WAON 14 +#define IMX94_PD_NETC 15 +#define IMX94_PD_NOC 16 +#define IMX94_PD_NPU 17 +#define IMX94_PD_WAKEUP 18 + +#define IMX94_PERF_M33 0 +#define IMX94_PERF_M33S 1 +#define IMX94_PERF_WAKEUP 2 +#define IMX94_PERF_M70 3 +#define IMX94_PERF_M71 4 +#define IMX94_PERF_DRAM 5 +#define IMX94_PERF_HSIO 6 +#define IMX94_PERF_NPU 7 +#define IMX94_PERF_NOC 8 +#define IMX94_PERF_A55 9 +#define IMX94_PERF_DISP 10 + +#endif /* __IMX94_POWER_H */ diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi new file mode 100644 index 000000000000..3661ea48d7d2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -0,0 +1,1148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024-2025 NXP + */ + +#include +#include +#include +#include + +#include "imx94-clock.h" +#include "imx94-pinfunc.h" +#include "imx94-power.h" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + osc_24m: clock-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + sai1_mclk: clock-sai1-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai1_mclk"; + }; + + sai2_mclk: clock-sai2-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai2_mclk"; + }; + + sai3_mclk: clock-sai3-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai3_mclk"; + }; + + sai4_mclk: clock-sai4-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai4_mclk"; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + #address-cells = <1>; + #size-cells = <0>; + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; + shmem = <&scmi_buf0>, <&scmi_buf1>; + arm,max-rx-timeout-ms = <5000>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_sys_power: protocol@12 { + reg = <0x12>; + }; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_iomuxc: protocol@19 { + reg = <0x19>; + }; + + scmi_bbm: protocol@81 { + reg = <0x81>; + }; + + scmi_misc: protocol@84 { + reg = <0x84>; + }; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + interrupt-parent = <&gic>; + arm,no-tick-in-suspend; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + interrupt-parent = <&gic>; + + its: msi-controller@48040000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x48040000 0 0x20000>; + #msi-cells = <1>; + dma-noncoherent; + msi-controller; + }; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x42000000 0x0 0x800000>; + ranges = <0x42000000 0x0 0x42000000 0x8000000>; + #address-cells = <1>; + #size-cells = <1>; + + edma2: dma-controller@42000000 { + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; + reg = <0x42000000 0x210000>; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <64>; + interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer 1>, + <&a55_irqsteer 2>, <&a55_irqsteer 3>, + <&a55_irqsteer 4>, <&a55_irqsteer 5>, + <&a55_irqsteer 6>, <&a55_irqsteer 7>, + <&a55_irqsteer 8>, <&a55_irqsteer 9>, + <&a55_irqsteer 10>, <&a55_irqsteer 11>, + <&a55_irqsteer 12>, <&a55_irqsteer 13>, + <&a55_irqsteer 14>, <&a55_irqsteer 15>, + <&a55_irqsteer 16>, <&a55_irqsteer 17>, + <&a55_irqsteer 18>, <&a55_irqsteer 19>, + <&a55_irqsteer 20>, <&a55_irqsteer 21>, + <&a55_irqsteer 22>, <&a55_irqsteer 23>, + <&a55_irqsteer 24>, <&a55_irqsteer 25>, + <&a55_irqsteer 26>, <&a55_irqsteer 27>, + <&a55_irqsteer 28>, <&a55_irqsteer 29>, + <&a55_irqsteer 30>, <&a55_irqsteer 31>, + <&a55_irqsteer 64>, <&a55_irqsteer 65>, + <&a55_irqsteer 66>, <&a55_irqsteer 67>, + <&a55_irqsteer 68>, <&a55_irqsteer 69>, + <&a55_irqsteer 70>, <&a55_irqsteer 71>, + <&a55_irqsteer 72>, <&a55_irqsteer 73>, + <&a55_irqsteer 74>, <&a55_irqsteer 75>, + <&a55_irqsteer 76>, <&a55_irqsteer 77>, + <&a55_irqsteer 78>, <&a55_irqsteer 79>, + <&a55_irqsteer 80>, <&a55_irqsteer 81>, + <&a55_irqsteer 82>, <&a55_irqsteer 83>, + <&a55_irqsteer 84>, <&a55_irqsteer 85>, + <&a55_irqsteer 86>, <&a55_irqsteer 87>, + <&a55_irqsteer 88>, <&a55_irqsteer 89>, + <&a55_irqsteer 90>, <&a55_irqsteer 91>, + <&a55_irqsteer 92>, <&a55_irqsteer 93>, + <&a55_irqsteer 94>, <&a55_irqsteer 95>; + }; + + mu10: mailbox@42430000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x42430000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + i3c2: i3c@42520000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42520000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, + <&scmi_clk IMX94_CLK_I3C2SLOW>, + <&dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPI2C3>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 5 0 0>, <&edma2 6 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPI2C4>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma4 4 0 0>, <&edma4 5 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPSPI3>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 7 0 0>, <&edma2 8 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPSPI4>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma4 6 0 0>, <&edma4 7 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART3>; + clock-names = "ipg"; + dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 9 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART4>; + clock-names = "ipg"; + dmas = <&edma4 10 0 FSL_EDMA_RX>, <&edma4 9 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART5>; + clock-names = "ipg"; + dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 11 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART6>; + clock-names = "ipg"; + dmas = <&edma4 12 0 FSL_EDMA_RX>, <&edma4 11 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan2: can@425b0000 { + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; + reg = <0x425b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, + <&scmi_clk IMX94_CLK_CAN2>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <80000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan3: can@425e0000 { + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; + reg = <0x425e0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, + <&scmi_clk IMX94_CLK_CAN3>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <80000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan4: can@425f0000 { + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; + reg = <0x425f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, + <&scmi_clk IMX94_CLK_CAN4>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <80000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan5: can@42600000 { + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; + reg = <0x42600000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, + <&scmi_clk IMX94_CLK_CAN5>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <80000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + sai2: sai@42650000 { + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; + reg = <0x42650000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, + <&scmi_clk IMX94_CLK_SAI2>, <&dummy>, <&dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 30 0 FSL_EDMA_RX>, <&edma2 29 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai3: sai@42660000 { + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; + reg = <0x42660000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, + <&scmi_clk IMX94_CLK_SAI3>, <&dummy>, <&dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 32 0 FSL_EDMA_RX>, <&edma2 31 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai4: sai@42670000 { + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; + reg = <0x42670000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, + <&scmi_clk IMX94_CLK_SAI4>, <&dummy>, <&dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 36 0 FSL_EDMA_RX>, <&edma2 35 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART7>; + clock-names = "ipg"; + dmas = <&edma2 46 0 FSL_EDMA_RX>, <&edma2 45 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART8>; + clock-names = "ipg"; + dmas = <&edma4 39 0 FSL_EDMA_RX>, <&edma4 38 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPI2C5>, + <&scmi_clk IMX94_CLK_BUSAON>; + clock-names = "per", "ipg"; + dmas = <&edma2 37 0 0>, <&edma2 38 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPI2C6>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma4 30 0 0>, <&edma4 31 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPI2C7>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 39 0 0>, <&edma2 40 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPI2C8>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma4 32 0 0>, <&edma4 33 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPSPI5>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 41 0 0>, <&edma2 42 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPSPI6>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma4 34 0 0>, <&edma4 35 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPSPI7>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 43 0 0>, <&edma2 44 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPSPI8>, + <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma4 36 0 0>, <&edma4 37 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mu11: mailbox@42730000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x42730000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + edma4: dma-controller@42df0000 { + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; + reg = <0x42df0000 0x210000>; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <64>; + interrupts-extended = <&a55_irqsteer 128>, <&a55_irqsteer 129>, + <&a55_irqsteer 130>, <&a55_irqsteer 131>, + <&a55_irqsteer 132>, <&a55_irqsteer 133>, + <&a55_irqsteer 134>, <&a55_irqsteer 135>, + <&a55_irqsteer 136>, <&a55_irqsteer 137>, + <&a55_irqsteer 138>, <&a55_irqsteer 139>, + <&a55_irqsteer 140>, <&a55_irqsteer 141>, + <&a55_irqsteer 142>, <&a55_irqsteer 143>, + <&a55_irqsteer 144>, <&a55_irqsteer 145>, + <&a55_irqsteer 146>, <&a55_irqsteer 147>, + <&a55_irqsteer 148>, <&a55_irqsteer 149>, + <&a55_irqsteer 150>, <&a55_irqsteer 151>, + <&a55_irqsteer 152>, <&a55_irqsteer 153>, + <&a55_irqsteer 154>, <&a55_irqsteer 155>, + <&a55_irqsteer 156>, <&a55_irqsteer 157>, + <&a55_irqsteer 158>, <&a55_irqsteer 159>, + <&a55_irqsteer 192>, <&a55_irqsteer 193>, + <&a55_irqsteer 194>, <&a55_irqsteer 195>, + <&a55_irqsteer 196>, <&a55_irqsteer 197>, + <&a55_irqsteer 198>, <&a55_irqsteer 199>, + <&a55_irqsteer 200>, <&a55_irqsteer 201>, + <&a55_irqsteer 202>, <&a55_irqsteer 203>, + <&a55_irqsteer 204>, <&a55_irqsteer 205>, + <&a55_irqsteer 206>, <&a55_irqsteer 207>, + <&a55_irqsteer 208>, <&a55_irqsteer 209>, + <&a55_irqsteer 210>, <&a55_irqsteer 211>, + <&a55_irqsteer 212>, <&a55_irqsteer 213>, + <&a55_irqsteer 214>, <&a55_irqsteer 215>, + <&a55_irqsteer 216>, <&a55_irqsteer 217>, + <&a55_irqsteer 218>, <&a55_irqsteer 219>, + <&a55_irqsteer 220>, <&a55_irqsteer 221>, + <&a55_irqsteer 222>, <&a55_irqsteer 223>; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x42800000 0 0x800000>; + ranges = <0x42800000 0x0 0x42800000 0x800000>, + <0x28000000 0x0 0x28000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, + <&scmi_clk IMX94_CLK_WAKEUPAXI>, + <&scmi_clk IMX94_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, + <&scmi_clk IMX94_CLK_WAKEUPAXI>, + <&scmi_clk IMX94_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + usdhc3: mmc@42880000 { + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42880000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, + <&scmi_clk IMX94_CLK_WAKEUPAXI>, + <&scmi_clk IMX94_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + lpuart9: serial@42a50000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42a50000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART10>; + clock-names = "ipg"; + dmas = <&edma2 51 0 FSL_EDMA_RX>, <&edma2 50 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart10: serial@42a60000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42a60000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART10>; + clock-names = "ipg"; + dmas = <&edma4 47 0 FSL_EDMA_RX>, <&edma4 46 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart11: serial@42a70000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42a70000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART11>; + clock-names = "ipg"; + dmas = <&edma2 53 0 FSL_EDMA_RX>, <&edma2 52 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart12: serial@42a80000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42a80000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART12>; + clock-names = "ipg"; + dmas = <&edma4 49 0 FSL_EDMA_RX>, <&edma4 48 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mu12: mailbox@42ac0000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x42ac0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu13: mailbox@42ae0000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x42ae0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu14: mailbox@42b00000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x42b00000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu15: mailbox@42b20000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x42b20000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu16: mailbox@42b40000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x42b40000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu17: mailbox@42b60000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x42b60000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43810000 0x0 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&scmi_iomuxc 0 4 32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43820000 0x0 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&scmi_iomuxc 0 36 26>; + }; + + gpio4: gpio@43840000 { + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43840000 0x0 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>, + <&scmi_iomuxc 8 140 12>, <&scmi_iomuxc 20 164 12>; + }; + + gpio5: gpio@43850000 { + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43850000 0x0 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&scmi_iomuxc 0 108 32>; + }; + + gpio6: gpio@43860000 { + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43860000 0x0 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&scmi_iomuxc 0 66 32>; + }; + + gpio7: gpio@43870000 { + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43870000 0x0 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 12>; + }; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x44000000 0x0 0x800000>; + ranges = <0x44000000 0x0 0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + edma1: dma-controller@44000000 { + compatible = "fsl,imx94-edma3", "fsl,imx93-edma3"; + reg = <0x44000000 0x210000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk IMX94_CLK_BUSAON>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <32>; + }; + + mu1: mailbox@44220000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x44220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@44290000 { + compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = ; + clocks = <&osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + + tpm1: pwm@44310000 { + compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; + reg = <0x44310000 0x1000>; + clocks = <&scmi_clk IMX94_CLK_BUSAON>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm2: pwm@44320000 { + compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x1000>; + clocks = <&scmi_clk IMX94_CLK_TPM2>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_BUSAON>, + <&scmi_clk IMX94_CLK_I3C1SLOW>, + <&dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPI2C1>, + <&scmi_clk IMX94_CLK_BUSAON>; + clock-names = "per", "ipg"; + dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPI2C2>, + <&scmi_clk IMX94_CLK_BUSAON>; + clock-names = "per", "ipg"; + dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPSPI2>, + <&scmi_clk IMX94_CLK_BUSAON>; + clock-names = "per", "ipg"; + dmas = <&edma1 16 0 0>, <&edma1 17 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LPSPI2>, + <&scmi_clk IMX94_CLK_BUSAON>; + clock-names = "per", "ipg"; + dmas = <&edma1 18 0 0>, <&edma1 19 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART1>; + clock-names = "ipg"; + dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_LPUART2>; + clock-names = "ipg"; + dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + sai1: sai@443b0000 { + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; + reg = <0x443b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSAON>, <&dummy>, + <&scmi_clk IMX94_CLK_SAI1>, <&dummy>, + <&dummy>, <&dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx94-adc", "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + ; + clocks = <&scmi_clk IMX94_CLK_ADC>; + clock-names = "ipg"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x445b0000 0x1000>; + ranges; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram0: sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + }; + + mu3: mailbox@445d0000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x445d0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x445f0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu6: mailbox@44630000 { + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; + reg = <0x44630000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + a55_irqsteer: interrupt-controller@446a0000 { + compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer"; + reg = <0x446a0000 0x1000>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = , + , + , + , + , + ; + clocks = <&scmi_clk IMX94_CLK_BUSAON>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <960>; + }; + }; + + aips4: bus@49000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x49000000 0x0 0x800000>; + ranges = <0x49000000 0x0 0x49000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + wdog3: watchdog@49220000 { + compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; + reg = <0x49220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + timeout-sec = <40>; + fsl,ext-reset-output; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi new file mode 100644 index 000000000000..45b8da758e87 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include "imx94.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_perf IMX94_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_perf IMX94_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x200>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_perf IMX94_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x300>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_perf IMX94_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <3>; + cache-unified; + }; + }; +}; From 771e874ef202775b254d92c74ac460ae5a25950d Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 21 Apr 2025 14:51:39 +0800 Subject: [PATCH 60/71] arm64: dts: freescale: Add minimal dts support for imx943 evk Add the minimal board dts support for i.MX943 EVK. Only the console uart, SD & eMMC are enabled for linux basic boot. Signed-off-by: Jacky Bai Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx943-evk.dts | 195 +++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx943-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index d63000efdf27..45f1f91dff5a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -319,6 +319,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts new file mode 100644 index 000000000000..cc8f3e6a1789 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024-2025 NXP + */ + +/dts-v1/; + +#include "imx943.dtsi" + +/ { + compatible = "fsl,imx943-evk", "fsl,imx94"; + model = "NXP i.MX943 EVK board"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_SD2_3V3"; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + device_type = "memory"; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e + IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX94_PAD_SD2_CD_B__GPIO4_IO20 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp { + fsl,pins = < + IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e + >; + }; +}; + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + bus-width = <4>; + no-mmc; + no-sdio; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; From 2f67c5c4dc22deb3fe8979a650a3708879e9e69c Mon Sep 17 00:00:00 2001 From: Martin Schmiedel Date: Fri, 9 May 2025 22:00:51 +0800 Subject: [PATCH 61/71] arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: Add LVDS device tree overlay This adds an overlay for the supported LVDS display tianma tm070jvhg33. The LVDS interface is the same as for MBa8MPxL so the already existing overlay can be reused on this platform. Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 45f1f91dff5a..5509826dcaec 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -261,8 +261,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo +imx8mp-tqma8mpql-mba8mp-ras314-lvds-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo From 6c2df49628c15ea8bca9d04b84fdf70549152da1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 9 May 2025 22:03:24 +0800 Subject: [PATCH 62/71] arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: Add Raspberry Pi Camera V2 overlay This overlay configures IMX219 MIPI-CSI-2 camera attached to ISP1. Also add additional overlay both using LVDS display and camera. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 4 + ...imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso | 107 ++++++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 5509826dcaec..deaa04254086 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -261,10 +261,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo +imx8mp-tqma8mpql-mba8mp-ras314-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo imx8mp-tqma8mpql-mba8mp-ras314-lvds-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo +imx8mp-tqma8mpql-mba8mp-ras314-lvds-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-imx219.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso new file mode 100644 index 000000000000..e5a2b3780215 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ +/dts-v1/; +/plugin/; + +#include +#include + +#include "imx8mp-pinfunc.h" + +&{/} { + /* + * The three camera regulators are controlled by a single GPIO. Declare + * a single regulator for the three supplies. + */ + reg_cam: regulator-cam { + compatible = "regulator-fixed"; + regulator-name = "reg_cam"; + /* pad muxing already done in gpio2grp */ + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vcc_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + cam24m: clock-cam24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cam24m"; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + camera@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cam24m>; + VANA-supply = <®_cam>; + VDIG-supply = <®_cam>; + VDDL-supply = <®_cam>; + orientation = <2>; + rotation = <0>; + + port { + sony_imx219: endpoint { + remote-endpoint = <&imx8mp_mipi_csi_in>; + clock-lanes = <0>; + clock-noncontinuous; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&isi_0 { + status = "disabled"; + + ports { + port@0 { + /delete-node/ endpoint; + }; + }; +}; + +&isp_0 { + status = "okay"; + + ports { + port@1 { + isp0_in: endpoint { + bus-type = ; + remote-endpoint = <&mipi_csi_0_out>; + }; + }; + }; +}; + +&mipi_csi_0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + imx8mp_mipi_csi_in: endpoint { + remote-endpoint = <&sony_imx219>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi_csi_0_out { + remote-endpoint = <&isp0_in>; +}; From ed93f6f48e22413c7cd2be56a1ba3254888abc13 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 9 May 2025 22:15:42 +0800 Subject: [PATCH 63/71] arm64: dts: freescale: add initial device tree for TQMa8XxS This adds support for TQMa8XQPS and TQMa8XDPS modules on MB-SMARC-2 board. As the only difference is the mounted SoC, both module and baseboard files are shared. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- MAINTAINERS | 1 + arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8dxp-tqma8xdps-mb-smarc-2.dts | 16 + .../boot/dts/freescale/imx8dxp-tqma8xdps.dtsi | 24 + .../imx8qxp-tqma8xqps-mb-smarc-2.dts | 16 + .../boot/dts/freescale/imx8qxp-tqma8xqps.dtsi | 14 + .../dts/freescale/tqma8xxs-mb-smarc-2.dtsi | 194 +++++ arch/arm64/boot/dts/freescale/tqma8xxs.dtsi | 768 ++++++++++++++++++ 8 files changed, 1035 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi create mode 100644 arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi create mode 100644 arch/arm64/boot/dts/freescale/tqma8xxs.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 96b827049501..225fec10fc73 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24492,6 +24492,7 @@ F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts* F: arch/arm64/boot/dts/freescale/imx*mba*.dts* F: arch/arm64/boot/dts/freescale/imx*tqma*.dts* F: arch/arm64/boot/dts/freescale/mba*.dtsi +F: arch/arm64/boot/dts/freescale/tqma8*.dtsi F: arch/arm64/boot/dts/freescale/tqml*.dts* F: drivers/gpio/gpio-tqmx86.c F: drivers/mfd/tqmx86.c diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index deaa04254086..1bc30bf05999 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -109,6 +109,7 @@ imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb @@ -311,6 +312,7 @@ imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts new file mode 100644 index 000000000000..331787df2fe4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2021-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "imx8dxp-tqma8xdps.dtsi" +#include "tqma8xxs-mb-smarc-2.dtsi" + +/ { + model = "TQ-Systems i.MX8DXP TQMa8XDPS on MB-SMARC-2"; + compatible = "tq,imx8dxp-tqma8xdps-mb-smarc-2", "tq,imx8dxp-tqma8xdps", "fsl,imx8dxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi new file mode 100644 index 000000000000..a97286fe7e0d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2021-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "imx8dxp.dtsi" +#include "tqma8xxs.dtsi" + +/ { + model = "TQ-Systems i.MX8DXP TQMa8XDPS"; + compatible = "tq,imx8dxp-tqma8xdps", "fsl,imx8dxp"; +}; + +&pmic0_thermal { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts new file mode 100644 index 000000000000..3fa9b5aee2c3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "imx8qxp-tqma8xqps.dtsi" +#include "tqma8xxs-mb-smarc-2.dtsi" + +/ { + model = "TQ-Systems i.MX8QXP TQMa8XQPS on MB-SMARC-2"; + compatible = "tq,imx8qxp-tqma8xqps-mb-smarc-2", "tq,imx8qxp-tqma8xqps", "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi new file mode 100644 index 000000000000..f008b7a34505 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "imx8qxp.dtsi" +#include "tqma8xxs.dtsi" + +/ { + model = "TQ-Systems i.MX8QXP TQMa8XQPS"; + compatible = "tq,imx8qxp-tqma8xqps", "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi new file mode 100644 index 000000000000..478cc8ede05e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/ { + aliases { + rtc0 = &rtc1; + rtc1 = &rtc; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds0>; + /* PWM support still missing */ + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds1>; + /* PWM support still missing */ + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = &lpuart0; + }; + + panel_lvds0: panel-lvds0 { + /* + * Display is not fixed, so compatible has to be added from + * DT + */ + backlight = <&backlight_lvds0>; + power-supply = <®_lvds0>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + }; + }; + }; + + panel_lvds1: panel-lvds1 { + /* + * Display is not fixed, so compatible has to be added from + * DT + */ + backlight = <&backlight_lvds1>; + power-supply = <®_lvds1>; + status = "disabled"; + + port { + panel_in_lvds1: endpoint { + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic3x04>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&flexcan2 { + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan3 { + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&i2c0 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + }; + + eeprom2: eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; +}; + +&lpspi1 { + status = "okay"; +}; + +&lpuart0 { + status = "okay"; +}; + +&lpuart3 { + status = "okay"; +}; + +®_sdvmmc { + off-on-delay-us = <200000>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usdhc2 { + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sdvmmc>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi new file mode 100644 index 000000000000..2d0a329c2fa5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include + +/delete-node/ &encoder_rpc; + +/ { + memory@80000000 { + device_type = "memory"; + /* + * DRAM base addr, minimal size : 1024 MiB DRAM + * should be corrected by bootloader + */ + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + reg_tqma8xxs_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_lvds0: regulator-lvds0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + regulator-name = "LCD0_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds1: regulator-lvds1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1>; + regulator-name = "LCD1_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sdvmmc: regulator-sdvmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdvmmc>; + regulator-name = "SD1_VMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "MMC0_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vqmmc: regulator-vqmmc { + compatible = "regulator-fixed"; + regulator-name = "MMC0_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * global autoconfigured region for contiguous allocations + * must not exceed memory size and region + */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x20000000>; + alloc-ranges = <0 0x96000000 0 0x30000000>; + linux,cma-default; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + m4_reserved: m4@88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + status = "disabled"; + }; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + status = "disabled"; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + status = "disabled"; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + status = "disabled"; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + status = "disabled"; + }; + + rsc_table: rsc-table@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + status = "disabled"; + }; + + vdevbuffer: vdevbuffer@90400000 { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + status = "disabled"; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + + encoder_rpc: encoder-rpc@92100000 { + reg = <0 0x92100000 0 0x700000>; + no-map; + }; + }; + +}; + +/* TQMa8XxS only uses industrial grade, reduce trip points accordingly */ +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <100000>; +}; +/* end of temperature grade adjustments */ + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + mac-address = [ 00 00 00 00 00 00 ]; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&lsio_gpio3 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy1>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&lsio_gpio0 24 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + fsl,magic-packet; + mac-address = [ 00 00 00 00 00 00 ]; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <66000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&lsio_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_smarc_fangpio>, <&pinctrl_smarc_mngtpio>; + + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "LID", "SLEEP", "CHARGING#", "CHGPRSNT#", + "BATLOW#", "", "", "", + "", "SMARC_GPIO6", "SMARC_GPIO5", "", + "PHY3 RST#", "", "", "SPI0_CS0", + "", "SPI0_CS1", "", ""; +}; + +&lsio_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_smarc_gpio>; + + gpio-line-names = "LCD1_BLKT_EN", "LCD1_VDD_EN", "LCD0_BLKT_EN", "LCD0_VDD_EN", + "SMARC_GPIO0", "SMARC_GPIO1", "SMARC_GPIO2", "", + "SMARC_GPIO3", "SMARC_GPIO8", "SMARC_GPIO7", "SMARC_GPIO10", + "SMARC_GPIO9", "SMARC_GPIO4", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&lsio_gpio2 { + gpio-line-names = "RTC_INT#", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&lsio_gpio3 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "PHY0_RST#", "", + "", "", "", "", + "", "", "", ""; +}; + +&lsio_gpio4 { + gpio-line-names = "PCIE_PERST#", "", "PCIE_WAKE#", "USB_OTG1_PWR", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "SDIO_PWR_EN", + "", "SDIO_WP", "SDIO_CD#", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c0>; + pinctrl-1 = <&pinctrl_lpi2c0_gpio>; + scl-gpios = <&lsio_gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* NXP SE97BTP with temperature sensor + eeprom */ + sensor0: temperature-sensor@1b { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_tqma8xxs_3v3>; + }; + + rtc1: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + quartz-load-femtofarads = <7000>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + vcc-supply = <®_tqma8xxs_3v3>; + }; + + pcieclk: clock-generator@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; +}; + +&lpspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +&mu_m0 { + status = "okay"; +}; + +&mu1_m0 { + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&thermal_zones { + pmic0_thermal: pmic0-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_vmmc>; + vqmmc-supply = <®_vqmmc>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + /* NOTE: CD / WP and VMMC support depends on mainboard */ +}; + +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight_lvds0: backlight-lvds0grp { + fsl,pins = ; + }; + + pinctrl_backlight_lvds1: backlight-lvds1grp { + fsl,pins = ; + }; + + pinctrl_can1: can1grp { + fsl,pins = , + ; + }; + + pinctrl_can2: can2grp { + fsl,pins = , + ; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = , + ; + }; + + pinctrl_ethphy1: ethphy1grp { + fsl,pins = , + ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_smarc_gpio: smarcgpiogrp { + fsl,pins = /* SMARC_GPIO0 / CAM0_PWR# */ + , + /* SMARC_GPIO1 / CAM1_PWR# */ + , + /* SMARC_GPIO2 / CAM0_RST# */ + , + /* SMARC_GPIO3 / CAM1_RST# */ + , + /* SMARC_GPIO4 / HDA_RST# */ + , + /* SMARC_GPIO7 */ + , + /* SMARC_GPIO8 */ + , + /* SMARC_GPIO9 */ + , + /* SMARC_GPIO10 */ + ; + }; + + pinctrl_smarc_fangpio: smarcfangpiogrp { + fsl,pins = /* SMARC_GPIO5 */ + , + /* SMARC_GPIO6 */ + ; + }; + + pinctrl_smarc_mngtpio: smarcmngtgpiogrp { + fsl,pins = /* SMARC BATLOW# */ + , + /* SMARC SLEEP */ + , + /* SMARC CHGPRSNT# */ + , + /* SMARC CHARGING# */ + , + /* SMARC LID */ + ; + }; + + pinctrl_lvds0: lbdpanel0grp { + fsl,pins = /* LCD PWR */ + ; + }; + + pinctrl_lvds1: lbdpanel1grp { + fsl,pins = /* LCD PWR */ + ; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c0_gpio: lpi2c0gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c0_mipi_lvds0: mipi-lvds0-i2c0grp { + fsl,pins = , + ; + }; + + pinctrl_i2c0_gpio_mipi_lvds0: mipi-lvds0-i2c0-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcieb: pcieagrp { + fsl,pins = , + , + ; + }; + + pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp { + fsl,pins = ; + }; + + pinctrl_pwm_mipi_lvds1: mipi-lvds1-pwmgrp { + fsl,pins = ; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_sdvmmc: sdvmmcgrp { + fsl,pins = ; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = /* PD + PDRV Low + INOUT - MEK has 0x0600004c */ + , + , + , + , + ; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; +}; From 88e62ced85fe302cb0d27e372dd29d0c4982c119 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Apr 2025 10:47:59 +0200 Subject: [PATCH 64/71] arm64: dts: imx: Align wifi node name with bindings Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: imx8mm-var-som-symphony.dtb: bcrmf@1: $nodename:0: 'bcrmf@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index c7a8f2a6fe90..21bcd82fd092 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -278,7 +278,7 @@ &usdhc1 { mmc-pwrseq = <&usdhc1_pwrseq>; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index cdfacbc35db5..190bde4edcd7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -306,7 +306,7 @@ &usdhc1 { keep-power-in-suspend; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 987c14d3af9d..67a99383a632 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -289,7 +289,7 @@ &usdhc1 { mmc-pwrseq = <&usdhc1_pwrseq>; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi index bbb07c650da9..d20393c2d901 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -265,7 +265,7 @@ &usdhc2 { non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { compatible = "brcm,bcm4329-fmac"; reg = <1>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index b364307868f2..38ef9e4fdf07 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -300,7 +300,7 @@ &usdhc1 { keep-power-in-suspend; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index a90e28c07e3f..7f754e0a5d69 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -590,7 +590,7 @@ &usdhc1 { #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { /* muRata 2AE */ + brcmf: wifi@1 { /* muRata 2AE */ reg = <1>; compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; /* From 91d1ff322c476005957183f6611315099d3ef16c Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 28 Apr 2025 15:59:09 +0200 Subject: [PATCH 65/71] arm64: dt: imx95: Add TQMa95xxSA Add initial support for TQMa95xxSA module compatible to SMARC-2. There is a common device tree for all variants with e.g. reduced CPU count. It supports LPUART7 for console, CAN, PCIe I2C, SPI, USB3.0, USB2.0, Audio, SDHC1/2 and QSPI as storage. [1] https://www.tq-group.com/en/products/tq-embedded/arm-architecture/tqma95xxsa/ Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx95-tqma9596sa-mb-smarc-2.dts | 324 ++++++++ .../boot/dts/freescale/imx95-tqma9596sa.dtsi | 698 ++++++++++++++++++ 3 files changed, 1023 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 1bc30bf05999..763c111e73ae 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -331,6 +331,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts new file mode 100644 index 000000000000..5b6b2bb80b28 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include "imx95-tqma9596sa.dtsi" + +/ { + model = "TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2"; + compatible = "tq,imx95-tqma9596sa-mb-smarc-2", "tq,imx95-tqma9596sa", "fsl,imx95"; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &scmi_bbm; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + }; + + chosen { + stdout-path = &lpuart7; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&tpm3 0 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pwms = <&tpm4 0 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + panel_lvds0: panel-lvds0 { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + backlight = <&backlight_lvds0>; + power-supply = <®_lvds0>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + /* TODO: LVDS0 out */ + }; + }; + }; + + panel_lvds1: panel-lvds1 { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + backlight = <&backlight_lvds1>; + power-supply = <®_lvds1>; + status = "disabled"; + + port { + panel_in_lvds1: endpoint { + /* TODO: LVDS1 out */ + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_lvds0: regulator-lvds0 { + compatible = "regulator-fixed"; + regulator-name = "LCD0_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds1: regulator-lvds1 { + compatible = "regulator-fixed"; + regulator-name = "LCD1_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander2 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + audio-codec = <&tlv320aic3x04>; + audio-cpu = <&sai3>; + }; +}; + +&enetc_port0 { + status = "okay"; +}; + +&enetc_port1 { + status = "okay"; +}; + +&expander2 { + pcie1-clk-en-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE1_CLK_EN"; + }; + + pcie2-clk-en-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE2_CLK_EN"; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&lpi2c1 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + }; + + eeprom2: eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; +}; + +&lpspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* SER0 */ +&lpuart1 { + status = "disabled"; +}; + +/* SER3 */ +&lpuart5 { + status = "okay"; +}; + +/* SER1 */ +&lpuart7 { + status = "okay"; +}; + +/* SER2 */ +&lpuart8 { + status = "okay"; +}; + +/* X44 mPCIe */ +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&pcieclk 1>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* X22 PCIe x1 socket */ +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&pcieclk 0>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +®_sdvmmc { + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI5>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; +}; + +/* X4 */ +&usb2 { + srp-disable; + hnp-disable; + adp-disable; + /* DR not yet supported */ + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + + +/* X16 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2>; + vmmc-supply = <®_sdvmmc>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + no-mmc; + no-sdio; + disable-wp; + bus-width = <4>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi new file mode 100644 index 000000000000..180124cc5bce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi @@ -0,0 +1,698 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include +#include +#include "imx95.dtsi" + +/ { + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + }; + + memory@80000000 { + device_type = "memory"; + /* + * DRAM base addr, size : 2048 MiB DRAM + * should be corrected by bootloader + */ + reg = <0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x80000000 0 0x80000000>; + linux,cma-default; + }; + + vpu_boot: vpu_boot@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + clk_dp: clk-dp { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* Controlled by system manager */ + reg_sdvmmc: regulator-sdvmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdvmmc>; + regulator-name = "SDIO_PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; +}; + +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; + phy-handle = <ðphy3>; + phy-mode = "rgmii-id"; +}; + +&netc_timer { + status = "okay"; +}; + +&flexspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-1 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <®_1v8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "GPIO7", "GPIO8", + "", "GPIO9", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "SLEEP", "GPIO5", + "", "", "GPIO6", "", + "", "", "", "", + "", "", "", ""; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + tmp1075: temperature-sensor@4a { + compatible = "ti,tmp1075"; + reg = <0x4a>; + vs-supply = <®_1v8>; + }; + + eeprom_smarc: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_1v8>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio2>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + }; + + m24c64: eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <®_1v8>; + }; + + /* protectable identification memory (part of M24C64-D @50) */ + eeprom@58 { + compatible = "atmel,24c64d-wl"; + reg = <0x58>; + vcc-supply = <®_1v8>; + }; + + /* protectable identification memory (part of M24C64-D @54) */ + eeprom@5c { + compatible = "atmel,24c64d-wl"; + reg = <0x5c>; + vcc-supply = <®_1v8>; + }; + + pcieclk: clock-generator@6a { + compatible = "renesas,9fgv0441"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; + + imu@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; + }; + + /* D23 */ + expander2: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + vcc-supply = <®_1v8>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO4", "LCD0_BLKT_EN", "LCD0_VDD_EN", "LCD1_BLKT_EN", + "LCD1_VDD_EN", "ENET1_RESET#", "ENET2_RESET#", "GBE0_SDP_DIR", + "GBE1_SDP_DIR", "PCIE1_RST#", "PCIE2_RST#", "DP_BRIDGE_EN", + "HUB_RST#", "QSPI_RESET#", "PCIE1_CLK_EN", "PCIE2_CLK_EN"; + }; + + /* D21 */ + expander1: gpio@75 { + compatible = "ti,tca9539"; + reg = <0x75>; + vcc-supply = <®_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + gpio-line-names = "GPIO10", "GPIO11", "GPIO12", "GPIO13", + "CHG_PRSNT#", "CHARGING", "LID", "BATLOW#", + "TEMP_EVENT#", "PGOOD_ARM", "PGOOD_SOC", "PCIE_WAKE#_1V8", + "GPIO0", "GPIO1", "GPIO2", "GPIO3"; + }; +}; + +/* I2C_CAM0 */ +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + dp_bridge: dp-bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + clock-names = "ref"; + clocks = <&clk_dp>; + reset-gpios = <&expander2 11 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio2>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + toshiba,hpd-pin = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp_dsi_in: endpoint { + /* TODO: DSI out */ + data-lanes = <1 2 3 4>; + }; + }; + }; + }; +}; + +/* I2C_CAM1 */ +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; +}; + +/* I2C_LCD */ +&lpi2c6 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c6>; + pinctrl-1 = <&pinctrl_lpi2c6>; + status = "okay"; +}; + +/* SER0 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* SER3 */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart5>; +}; + +/* SER1 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart7>; +}; + +/* SER2 */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart8>; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>; + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy0>; + reset-gpios = <&expander2 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio5>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy3>; + reset-gpios = <&expander2 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; +}; + +&scmi_bbm { + linux,code = ; +}; + +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm3>; +}; + +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm4>; +}; + +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usb3_phy { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_ethphy0: ethphy0grp { + fsl,pins = ; + }; + + pinctrl_ethphy3: ethphy3grp { + fsl,pins = ; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_expander1: expander1grp { + fsl,pins = ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , + ; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = , + ; + }; + + pinctrl_flexspi1: flexspi1grp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = , + , + ; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = , + , + ; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = , + ; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart8: lpuart8grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = ; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = ; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_sdvmmc: sdvmmcgrp { + fsl,pins = ; + }; + + pinctrl_tc9595: tc9595grp { + fsl,pins = ; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = ; + }; + + pinctrl_tpm4: tpm4grp { + fsl,pins = ; + }; + + pinctrl_tpm5: tpm4grp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + ; + }; +}; From 21faf8f8e01bfd72845343f5ed345ae6a42a44dc Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Wed, 30 Apr 2025 10:18:48 +0200 Subject: [PATCH 66/71] arm64: dts: imx93-tqma9352-mba91xxca: disable Open Drain for MDIO Using the MDIO pins with Open Drain causes spec violations of the signals. Revert the changes. This is similar to commit 14e66e4b13221 ("Revert "arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIO"") Fixes: e5bc07026f94 ("arm64: add initial device tree for TQMa93xx/MBa91xxCA") Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts index 7b78faa4bfd0..9dbf41cf394b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts @@ -571,7 +571,7 @@ pinctrl_eqos: eqosgrp { fsl,pins = /* PD | FSEL_2 | DSE X4 */ , /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - , + , /* HYS | FSEL_0 | DSE no drive */ , , @@ -599,7 +599,7 @@ pinctrl_fec: fecgrp { fsl,pins = /* PD | FSEL_2 | DSE X4 */ , /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - , + , /* HYS | FSEL_0 | DSE no drive */ , , From 8c7432dc2ab0e0106124b0416a6a21613b294655 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 30 Apr 2025 11:41:47 +0200 Subject: [PATCH 67/71] arm64: dts: freescale: imx8mp-toradex-smarc: add fan PWM configuration Configure correctly the FAN pwm output (inverted). Reviewed-by: Peng Fan Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-toradex-smarc-dev.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts index 581f221323b7..55b8c5c14fb4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts @@ -3,6 +3,8 @@ /dts-v1/; +#include + #include "imx8mp-toradex-smarc.dtsi" / { @@ -205,9 +207,14 @@ &i2c6 { status = "okay"; /* Fan controller */ - fan@18 { + fan_controller: fan@18 { compatible = "ti,amc6821"; reg = <0x18>; + #pwm-cells = <2>; + + fan { + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; }; /* Current measurement into module VDD */ From e40201b454788f12aa3808d648ed7d4ef7e2da01 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Wed, 30 Apr 2025 11:41:48 +0200 Subject: [PATCH 68/71] arm64: dts: freescale: imx8mp-toradex-smarc: add embedded controller Add the embedded controller node to the device tree, this is required for reset and power-off functionalities. Reviewed-by: Peng Fan Signed-off-by: Emanuele Ghidoli Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi index 0a8b9eee5ed9..c4ca01ce60d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi @@ -534,6 +534,11 @@ reg_sd_3v3_1v8: LDO5 { }; }; + embedded-controller@28 { + compatible = "toradex,smarc-imx8mp-ec", "toradex,smarc-ec"; + reg = <0x28>; + }; + rtc_i2c: rtc@32 { compatible = "epson,rx8130"; reg = <0x32>; From 8161827fb80c7f6f6ac8abffedcfdd3a42e13d2b Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Wed, 30 Apr 2025 11:41:49 +0200 Subject: [PATCH 69/71] arm64: dts: freescale: imx8mp-toradex-smarc: add gpio expander Add gpio expander node to the device tree and the related nodes. Reviewed-by: Peng Fan Signed-off-by: Emanuele Ghidoli Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-toradex-smarc.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi index c4ca01ce60d0..0cd04c3c96bb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi @@ -54,6 +54,13 @@ smarc_key_sleep: key-sleep { wakeup-source; linux,code = ; }; + + smarc_switch_lid: switch-lid { + gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>; + label = "SMARC_LID#"; + linux,code = ; + linux,input-type = ; + }; }; reg_usb0_vbus: regulator-usb0-vbus { @@ -539,6 +546,24 @@ embedded-controller@28 { reg = <0x28>; }; + som_ec_gpio_expander: gpio@29 { + compatible = "toradex,ecgpiol16", "nxp,pcal6416"; + reg = <0x29>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_int>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "SMARC_CHARGER_PRSNT#", + "SMARC_CHARGING#", + "SMARC_LID#", + "SMARC_BATLOW#"; + }; + rtc_i2c: rtc@32 { compatible = "epson,rx8130"; reg = <0x32>; From 707bf92e4bc2b036d5f4c57cd1025872c9533c7e Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 30 Apr 2025 11:41:50 +0200 Subject: [PATCH 70/71] arm64: dts: freescale: imx8mp-toradex-smarc: use generic gpio node name Use generic node name for the SoM GPIO expander, following the Devicetree Specification generic node names recommendation. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi index 0cd04c3c96bb..22f6daabdb90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi @@ -434,7 +434,7 @@ &i2c1 { single-master; status = "okay"; - som_gpio_expander: gpio-expander@21 { + som_gpio_expander: gpio@21 { compatible = "nxp,pcal6408"; reg = <0x21>; pinctrl-names = "default"; From 1f6c8626527257db05c09022e94a5cd4e162c45d Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Mon, 5 May 2025 09:51:07 +0200 Subject: [PATCH 71/71] arm64: dts: freescale: Add PHYTEC phyBOARD-Nash-i.MX93 support Add initial support for PHYTEC phyBOARD-Nash-i.MX93 board [1] based on the PHYTEC phyCORE-i.MX93 SoM (System-on-Module) [2]. Supported board features: * ADC * CAN * Ethernet * EEPROM * RTC * RS-232/RS-485 * SD-card * TPM 2.0 * USB For more details see the product pages for the development kit and the SoM: [1] https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ [2] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ Signed-off-by: Primoz Fiser Reviewed-by: Wadim Egorov Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-phyboard-nash.dts | 317 ++++++++++++++++++ 2 files changed, 318 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 763c111e73ae..0b473a23d120 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -322,6 +322,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts new file mode 100644 index 000000000000..7e9d031a2f0e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + * + * Product homepage: + * https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ + */ + +/dts-v1/; + +#include +#include "imx93-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Nash-i.MX93"; + compatible = "phytec,imx93-phyboard-nash", "phytec,imx93-phycore-som", + "fsl,imx93"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + rtc0 = &i2c_rtc; + rtc1 = &bbnsm_rtc; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan1_tc: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <8000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_tc>; + standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VCC_SD"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + reg_vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "VREF_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +/* ADC */ +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +/* CAN */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + phys = <&flexcan1_tc>; + status = "okay"; +}; + +/* I2C2 */ +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + /* RTC */ + i2c_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + trickle-resistor-ohms = <3000>; + wakeup-source; + }; + + /* EEPROM */ + eeprom@54 { + compatible = "atmel,24c32"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <®_vcc_1v8>; + }; +}; + +/* SPI6 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* TPM */ + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + spi-max-frequency = <10000000>; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* RS-232/RS-485 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x50e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x50e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1002 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX93_PAD_PDM_CLK__CAN1_TX 0x1382 + >; + }; + + pinctrl_flexcan1_tc: flexcan1tcgrp { + fsl,pins = < + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpspi6: lpspi6grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386 + MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe + MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x386 + MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x386 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX93_PAD_GPIO_IO17__GPIO2_IO17 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__LPUART7_TX 0x30e + MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e + MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e + MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013be + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +};