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net: atlantic: fix AQC113 HW init: ART, L2 filter slot, MAC address
Fix initialization issues in hw_atl2 to correctly support AQC113: - hw_atl2_hw_reset: replace unconditional priv memset with selective field clears so that l3l4_filters[].l3_index and l4_index can be initialized to -1 (not allocated) rather than 0; 0 is a valid filter index and would incorrectly appear as an occupied slot after a reset. - hw_atl2_hw_init_new_rx_filters: use firmware-reported ART section base and count (clamped to 16) instead of hardcoded 0xFFFF mask; enable simultaneous IPv4/IPv6 L3 filter mode (rpf_l3_v6_v4_select); tag the UC MAC slot using firmware-supplied l2_filters_base_index instead of hardcoded HW_ATL2_MAC_UC. - hw_atl2_hw_init_rx_path: enable only the firmware-assigned MAC slot (priv->l2_filters_base_index) instead of always slot 0. - Add hw_atl2_hw_mac_addr_set() that programs the MAC address into the firmware-assigned L2 filter slot. Wire into hw_atl2_ops replacing the A1 hw_atl_b0_hw_mac_addr_set; call it from hw_init. - Wire .hw_get_regs into hw_atl2_ops. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-7-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Sukhdeep Singh
Jakub Kicinski
parent
4428d3b994
commit
6c1ca112a6
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@ -11,6 +11,7 @@
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#include "hw_atl/hw_atl_utils.h"
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#include "hw_atl/hw_atl_llh.h"
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#include "hw_atl/hw_atl_llh_internal.h"
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#include "hw_atl2.h"
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#include "hw_atl2_utils.h"
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#include "hw_atl2_llh.h"
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#include "hw_atl2_internal.h"
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@ -95,12 +96,21 @@ static int hw_atl2_hw_reset(struct aq_hw_s *self)
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{
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struct hw_atl2_priv *priv = self->priv;
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int err;
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int i;
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err = hw_atl2_utils_soft_reset(self);
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if (err)
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return err;
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memset(priv, 0, sizeof(*priv));
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memset(&priv->last_stats, 0, sizeof(priv->last_stats));
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memset(priv->l3_v4_filters, 0, sizeof(priv->l3_v4_filters));
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memset(priv->l3_v6_filters, 0, sizeof(priv->l3_v6_filters));
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memset(priv->l4_filters, 0, sizeof(priv->l4_filters));
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memset(priv->etype_policy, 0, sizeof(priv->etype_policy));
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for (i = 0; i < HW_ATL2_RPF_L3L4_FILTERS; i++) {
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priv->l3l4_filters[i].l3_index = -1;
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priv->l3l4_filters[i].l4_index = -1;
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}
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self->aq_fw_ops->set_state(self, MPI_RESET);
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@ -380,6 +390,9 @@ static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self)
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{
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u8 *prio_tc_map = self->aq_nic_cfg->prio_tc_map;
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struct hw_atl2_priv *priv = self->priv;
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u32 art_first_sec, art_last_sec;
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u32 art_sections;
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u32 art_mask;
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u16 action;
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u8 index;
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int i;
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@ -394,9 +407,20 @@ static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self)
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* REC entry is used for further processing. If multiple entries match,
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* the lowest REC entry, Action field will be selected.
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*/
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hw_atl2_rpf_act_rslvr_section_en_set(self, 0xFFFF);
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art_last_sec = min_t(u32,
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priv->art_base_index / 8 + priv->art_count / 8,
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16U);
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art_first_sec = min_t(u32, priv->art_base_index / 8, 16U);
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art_mask = (BIT(art_last_sec) - 1) - (BIT(art_first_sec) - 1);
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if (!art_mask) {
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/* ART base index is out of range, enabling all sections */
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art_mask = 0xFFFF;
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}
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art_sections = hw_atl2_rpf_act_rslvr_section_en_get(self) | art_mask;
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hw_atl2_rpf_act_rslvr_section_en_set(self, art_sections);
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hw_atl2_rpf_l3_v6_v4_select_set(self, 1);
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hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC,
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HW_ATL2_MAC_UC);
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priv->l2_filters_base_index);
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hw_atl2_rpfl2_bc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC);
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/* FW reserves the beginning of ART, thus all driver entries must
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@ -484,6 +508,7 @@ static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location,
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static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self)
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{
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struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
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struct hw_atl2_priv *priv = self->priv;
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int i;
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/* Rx TC/RSS number config */
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@ -499,7 +524,9 @@ static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self)
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/* Multicast filters */
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for (i = HW_ATL2_MAC_MAX; i--;) {
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hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
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hw_atl_rpfl2_uc_flr_en_set(self,
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(i == priv->l2_filters_base_index) ?
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1U : 0U, i);
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hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
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}
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@ -530,6 +557,35 @@ static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self)
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return aq_hw_err_from_flags(self);
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}
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static int hw_atl2_hw_mac_addr_set(struct aq_hw_s *self, const u8 *mac_addr)
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{
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struct hw_atl2_priv *priv = self->priv;
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u32 location = priv->l2_filters_base_index;
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unsigned int h;
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unsigned int l;
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int err;
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if (!mac_addr) {
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err = -EINVAL;
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goto err_exit;
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}
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h = (mac_addr[0] << 8) | (mac_addr[1]);
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l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
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(mac_addr[4] << 8) | mac_addr[5];
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hw_atl_rpfl2_uc_flr_en_set(self, 0U, location);
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hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, location);
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hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, location);
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hw_atl_rpfl2unicast_flr_act_set(self, 1U, location);
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hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC, location);
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hw_atl_rpfl2_uc_flr_en_set(self, 1U, location);
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err = aq_hw_err_from_flags(self);
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err_exit:
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return err;
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}
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static int hw_atl2_hw_init(struct aq_hw_s *self, const u8 *mac_addr)
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{
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static u32 aq_hw_atl2_igcr_table_[4][2] = {
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@ -547,7 +603,7 @@ static int hw_atl2_hw_init(struct aq_hw_s *self, const u8 *mac_addr)
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hw_atl2_hw_init_tx_path(self);
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hw_atl2_hw_init_rx_path(self);
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hw_atl_b0_hw_mac_addr_set(self, mac_addr);
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hw_atl2_hw_mac_addr_set(self, mac_addr);
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self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
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self->aq_fw_ops->set_state(self, MPI_INIT);
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@ -619,6 +675,8 @@ static int hw_atl2_hw_multicast_list_set(struct aq_hw_s *self,
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[ETH_ALEN],
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u32 count)
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{
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struct hw_atl2_priv *priv = self->priv;
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u32 base_location = priv->l2_filters_base_index + 1;
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struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
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int err = 0;
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@ -634,18 +692,18 @@ static int hw_atl2_hw_multicast_list_set(struct aq_hw_s *self,
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u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
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(ar_mac[i][4] << 8) | ar_mac[i][5];
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hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL2_MAC_MIN + i);
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hw_atl_rpfl2_uc_flr_en_set(self, 0U, base_location + i);
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hw_atl_rpfl2unicast_dest_addresslsw_set(self, l,
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HW_ATL2_MAC_MIN + i);
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base_location + i);
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hw_atl_rpfl2unicast_dest_addressmsw_set(self, h,
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HW_ATL2_MAC_MIN + i);
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base_location + i);
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hw_atl2_rpfl2_uc_flr_tag_set(self, 1, HW_ATL2_MAC_MIN + i);
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hw_atl2_rpfl2_uc_flr_tag_set(self, 1, base_location + i);
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hw_atl_rpfl2_uc_flr_en_set(self, (cfg->is_mc_list_enabled),
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HW_ATL2_MAC_MIN + i);
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base_location + i);
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}
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err = aq_hw_err_from_flags(self);
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@ -816,7 +874,7 @@ static int hw_atl2_hw_vlan_ctrl(struct aq_hw_s *self, bool enable)
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const struct aq_hw_ops hw_atl2_ops = {
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.hw_soft_reset = hw_atl2_utils_soft_reset,
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.hw_prepare = hw_atl2_utils_initfw,
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.hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
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.hw_set_mac_address = hw_atl2_hw_mac_addr_set,
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.hw_init = hw_atl2_hw_init,
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.hw_reset = hw_atl2_hw_reset,
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.hw_start = hw_atl_b0_hw_start,
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@ -846,6 +904,7 @@ const struct aq_hw_ops hw_atl2_ops = {
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.hw_rss_set = hw_atl2_hw_rss_set,
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.hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
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.hw_tc_rate_limit_set = hw_atl2_hw_init_tx_tc_rate_limit,
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.hw_get_regs = hw_atl2_utils_hw_get_regs,
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.hw_get_hw_stats = hw_atl2_utils_get_hw_stats,
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.hw_get_fw_version = hw_atl2_utils_get_fw_version,
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.hw_set_offload = hw_atl_b0_hw_offload_set,
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@ -626,6 +626,8 @@ int hw_atl2_utils_get_filter_caps(struct aq_hw_s *self)
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if (priv->art_count == 0)
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priv->art_count = HW_ATL2_ART_TOTAL_ENTRIES;
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priv->l2_filters_base_index = filter_caps.l2_filters_base_index;
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if (priv->l2_filters_base_index >= HW_ATL2_MAC_MAX)
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priv->l2_filters_base_index = HW_ATL2_MAC_UC;
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priv->l2_filter_count = filter_caps.l2_filter_count;
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priv->etype_filter_base_index = filter_caps.ethertype_filter_base_index;
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priv->etype_filter_count = filter_caps.ethertype_filter_count;
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