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ARM: dts: dra7: Fix up unaligned access setting for PCIe EP

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commit 6d0af44a82 upstream.

Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.

Fixes: d23f3839fe ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Vignesh R 2018-09-25 10:51:51 +05:30 committed by Greg Kroah-Hartman
parent 51819131ed
commit 6be746c4ef
1 changed files with 1 additions and 1 deletions
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2
arch/arm/boot/dts/dra7.dtsi
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@ -354,7 +354,7 @@ pcie1_ep: pcie_ep@51000000 {
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
status = "disabled";
};
};