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SoCFPGA Clock updates for v6.16, version 2

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- Optimize local variables for clocks
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Merge tag 'socfpga_clk_updates_for_6.16_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into clk-socfpga

Pull SoCFPGA clk driver updates from Dinh Nguyen:

 - Optimize local variables for clocks

* tag 'socfpga_clk_updates_for_6.16_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  clk: socfpga: stratix10: Optimize local variables
  clk: socfpga: clk-pll: Optimize local variables
This commit is contained in:
Stephen Boyd 2025-05-06 20:51:31 -07:00
commit 6bbc69e58a
2 changed files with 5 additions and 5 deletions
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6
drivers/clk/socfpga/clk-pll-s10.c
View File

@ -83,9 +83,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
unsigned long mdiv;
unsigned long refdiv;
unsigned long reg;
u32 mdiv;
u32 refdiv;
u32 reg;
unsigned long long vco_freq;
/* read VCO1 reg for numerator and denominator */

4
drivers/clk/socfpga/clk-pll.c
View File

@ -39,9 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
unsigned long divf, divq, reg;
u32 divf, divq, reg;
unsigned long long vco_freq;
unsigned long bypass;
u32 bypass;
reg = readl(socfpgaclk->hw.reg);
bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);