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spi: spi-qpic-snand: remove 'clr*status' members of struct 'qpic_ecc'

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In the qcom_spi_ecc_init_ctx_pipelined() function, the 'clrflashstatus'
and the 'clrreadstatus' members of the ECC context gets initialized with
constant values. Then these values are used by several functions to set
the corresponding members in the register cache.

Because the values are never modified, change the code to set the those
directly in the register cache by the qcom_spi_ecc_init_ctx_pipelined()
function, and remove the repetitive code from the other functions to
reduce code duplication.

Also, remove the respective members from the 'qpic_ecc' structure as
those became unused due to the change.

No functional changes intended.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://patch.msgid.link/20250810-qpic-snand-qpic_ecc-cleanup-v1-2-33a6b2bcbc67@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Gabor Juhos 2025-08-10 16:38:51 +02:00 committed by Mark Brown
parent fbec18dc99
commit 6b7e2aa50b
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 2 additions and 14 deletions
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16
drivers/spi/spi-qpic-snand.c
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@ -94,8 +94,6 @@ struct qpic_ecc {
u32 cfg1_raw;
u32 ecc_buf_cfg;
u32 ecc_bch_cfg;
u32 clrflashstatus;
u32 clrreadstatus;
bool bch_enabled;
};
@ -381,12 +379,12 @@ static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
ecc_cfg->clrflashstatus = FS_READY_BSY_N;
ecc_cfg->clrreadstatus = 0xc0;
conf->step_size = ecc_cfg->step_size;
conf->strength = ecc_cfg->strength;
snandc->regs->clrflashstatus = cpu_to_le32(FS_READY_BSY_N);
snandc->regs->clrreadstatus = cpu_to_le32(0xc0);
snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
@ -598,8 +596,6 @@ static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
snandc->regs->cfg0 = cpu_to_le32(cfg0);
snandc->regs->cfg1 = cpu_to_le32(cfg1);
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
snandc->regs->exec = cpu_to_le32(1);
qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
@ -733,8 +729,6 @@ static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_bu
snandc->regs->cfg0 = cpu_to_le32(cfg0);
snandc->regs->cfg1 = cpu_to_le32(cfg1);
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
snandc->regs->exec = cpu_to_le32(1);
qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
@ -849,8 +843,6 @@ static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
snandc->regs->cfg0 = cpu_to_le32(cfg0);
snandc->regs->cfg1 = cpu_to_le32(cfg1);
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
snandc->regs->exec = cpu_to_le32(1);
qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
@ -942,8 +934,6 @@ static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
snandc->regs->cfg0 = cpu_to_le32(cfg0);
snandc->regs->cfg1 = cpu_to_le32(cfg1);
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
snandc->regs->exec = cpu_to_le32(1);
qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
@ -1063,8 +1053,6 @@ static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
snandc->regs->cfg0 = cpu_to_le32(cfg0);
snandc->regs->cfg1 = cpu_to_le32(cfg1);
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
snandc->regs->exec = cpu_to_le32(1);
qcom_spi_config_page_write(snandc);