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pwm: Changes for v7.2-rc1
The usual mixture of minor fixes, a few cleanups, a new driver and dt updates for the pwm subsystem. Thanks to Chen Ni, Devi Priya, Manish Baing, Maurice Hieronymus, Ronaldo Nunez, Rosen Penev, Shiji Yang and Yixun Lan for the actual changes and Bjorn Andersson, Conor Dooley, Frank Li, Michal Wilczynski and Rob Herring for reviews and acks. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEP4GsaTp6HlmJrf7Tj4D7WH0S/k4FAmovj1UACgkQj4D7WH0S /k4ATQf/YNPhLsDzLj0q7VM4wmMdBkX5s8e1yRAu4rRKMevWGP041MQMKxSiYU5k 7vSEvxGaK2c5nmM6Iop6KJ1+wkL3fQNG+o2e5iOyedgFlayoHTE/vMOsooLPyJ7G thKFRQYqXenMtetY9n2fHaOtHayid/JWfZ1lQ9dlf8RDS1eN8dlgR/E4pNL5HUCv n3McnhbBxUrxpQaSeTfBRGwVahCORcS01srlLeT/VXlCHVGAwIZu/qtWTlHH7jXZ JO3iKxWlcUHvgt8BYxjpio3gYB9LZhunL23FtIHg48+HjYLyRS+JD2SYSWV2FZ+l 0oRKImnotlW2zeFskp8VIqReUrJMgg== =4Uq3 -----END PGP SIGNATURE----- Merge tag 'pwm/for-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux Pull pwm updates from Uwe Kleine-König: "The usual mixture of minor fixes, a few cleanups, a new driver and dt updates for the pwm subsystem. Thanks to Chen Ni, Devi Priya, Manish Baing, Maurice Hieronymus, Ronaldo Nunez, Rosen Penev, Shiji Yang and Yixun Lan for the actual changes and Bjorn Andersson, Conor Dooley, Frank Li, Michal Wilczynski and Rob Herring for reviews and acks" * tag 'pwm/for-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux: pwm: th1520: Remove requirement for mul_u64_u64_div_u64_roundup dt-bindings: pwm: stmpe: Drop legacy binding pwm: pca9685: Use named initializers for struct i2c_device_id pwm: pxa: Add optional bus clock dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K3 PWM support pwm: ipq: Add missing module description pwm: stm32: Make use of mul_u64_u64_div_u64_roundup() pwm: Consistently define pci_device_ids using named initializers pwm: Driver for qualcomm ipq6018 pwm block pwm: imx27: Fix variable truncation in .apply() pwm: mediatek: correct mt7628 clock source setting pwm: mediatek: set mt7628 pwm45_fixup flag to false pwm: atmel-tcb: Remove unneeded semicolon
This commit is contained in:
Linus Torvalds
commit
6b617c8258
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|
@ -15,7 +15,9 @@ allOf:
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|||
properties:
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compatible:
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contains:
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const: spacemit,k1-pwm
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enum:
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- spacemit,k1-pwm
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- spacemit,k3-pwm
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then:
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properties:
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"#pwm-cells":
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|
|
@ -26,6 +28,26 @@ allOf:
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const: 1
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description: |
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Used for specifying the period length in nanoseconds.
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- if:
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properties:
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compatible:
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contains:
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enum:
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- spacemit,k3-pwm
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then:
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required:
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- clock-names
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properties:
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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properties:
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compatible:
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@ -36,7 +58,9 @@ properties:
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- marvell,pxa168-pwm
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- marvell,pxa910-pwm
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- items:
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- const: spacemit,k1-pwm
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- enum:
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- spacemit,k1-pwm
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- spacemit,k3-pwm
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- const: marvell,pxa910-pwm
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reg:
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@ -47,7 +71,18 @@ properties:
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description: Number of cells in a pwm specifier.
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clocks:
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maxItems: 1
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minItems: 1
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items:
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- description: The function clock
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- description: An optional bus clock
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clock-names:
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minItems: 1
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maxItems: 2
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oneOf:
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- items:
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- const: func
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- const: bus
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resets:
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maxItems: 1
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|
|
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|
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@ -1,18 +0,0 @@
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== ST STMPE PWM controller ==
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This is a PWM block embedded in the ST Microelectronics STMPE
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(ST Multi-Purpose Expander) chips. The PWM is registered as a
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subdevices of the STMPE MFD device.
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Required properties:
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- compatible: should be:
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- "st,stmpe-pwm"
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- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
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the cells format.
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Example:
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pwm0: pwm {
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compatible = "st,stmpe-pwm";
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#pwm-cells = <2>;
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};
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@ -347,6 +347,18 @@ config PWM_INTEL_LGM
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To compile this driver as a module, choose M here: the module
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will be called pwm-intel-lgm.
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config PWM_IPQ
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tristate "IPQ PWM support"
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depends on ARCH_QCOM || COMPILE_TEST
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depends on HAVE_CLK && HAS_IOMEM
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help
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Generic PWM framework driver for IPQ PWM block which supports
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4 pwm channels. Each of the these channels can be configured
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independent of each other.
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To compile this driver as a module, choose M here: the module
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will be called pwm-ipq.
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config PWM_IQS620A
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tristate "Azoteq IQS620A PWM support"
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depends on MFD_IQS62X || COMPILE_TEST
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|
|
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@ -29,6 +29,7 @@ obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
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obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o
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obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o
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obj-$(CONFIG_PWM_INTEL_LGM) += pwm-intel-lgm.o
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obj-$(CONFIG_PWM_IPQ) += pwm-ipq.o
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obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o
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obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
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obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o
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|
|
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|
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@ -443,7 +443,7 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)
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err = clk_prepare_enable(tcbpwmc->slow_clk);
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if (err)
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goto err_disable_clk;;
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goto err_disable_clk;
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err = clk_rate_exclusive_get(tcbpwmc->clk);
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if (err)
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|
|
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|
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@ -147,8 +147,8 @@ static int dwc_pwm_resume(struct device *dev)
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static DEFINE_SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume);
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static const struct pci_device_id dwc_pwm_id_table[] = {
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{ PCI_VDEVICE(INTEL, 0x4bb7), (kernel_ulong_t)&ehl_pwm_info },
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{ } /* Terminating Entry */
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{ PCI_VDEVICE(INTEL, 0x4bb7), .driver_data = (kernel_ulong_t)&ehl_pwm_info },
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{ } /* Terminating Entry */
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};
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MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table);
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|
|
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@ -200,7 +200,7 @@ static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
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static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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unsigned long period_cycles, duty_cycles, prescale, period_us, tmp;
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unsigned long period_cycles, duty_cycles, prescale, period_us;
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struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
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unsigned long long c;
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unsigned long long clkrate;
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@ -208,6 +208,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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int val;
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int ret;
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u32 cr;
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u64 tmp;
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clkrate = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);
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c = clkrate * state->period;
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|
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@ -249,6 +250,11 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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val = readl(imx->mmio_base + MX3_PWMPR);
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val = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
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cr = readl(imx->mmio_base + MX3_PWMCR);
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/*
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* tmp stores period in nanoseconds. Result fits in u64 since
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* val <= 0xfffe and prescaler in [1, 0x1000].
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*/
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tmp = NSEC_PER_SEC * (u64)(val + 2) * MX3_PWMCR_PRESCALER_GET(cr);
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tmp = DIV_ROUND_UP_ULL(tmp, clkrate);
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period_us = DIV_ROUND_UP_ULL(tmp, 1000);
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|
|
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264
drivers/pwm/pwm-ipq.c
Normal file
264
drivers/pwm/pwm-ipq.c
Normal file
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@ -0,0 +1,264 @@
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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
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/*
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* Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
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*
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* Limitations:
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* - The PWM controller has no publicly available datasheet.
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* - Each of the four channels is programmed via two 32-bit registers
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* (REG0 and REG1 at 8-byte stride).
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* - Period and duty-cycle reconfiguration is fully atomic: new divider,
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* pre-divider, and high-duration values are latched by setting the
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* UPDATE bit (bit 30 in REG1). The hardware applies the new settings
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* at the beginning of the next period without disabling the output,
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* so the currently running period is always completed.
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* - On disable (clearing the ENABLE bit 31 in REG1), the hardware
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* finishes the current period before stopping the output. The pin
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* is then driven to the inactive (low) level.
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* - Upon disabling, the hardware resets the pre-divider (PRE_DIV) and divider
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* fields (PWM_DIV) in REG0 and REG1 to 0x0000 and 0x0001 respectively.
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* - Only normal polarity is supported.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/math64.h>
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#include <linux/of_device.h>
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#include <linux/bitfield.h>
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#include <linux/units.h>
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/* The frequency range supported is 1 Hz to 100 Mhz (clock rate) */
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#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC)
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#define IPQ_PWM_MIN_PERIOD_NS 10
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/*
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* Two 32-bit registers for each PWM: REG0, and REG1.
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* Base offset for PWM #i is at 8 * #i.
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*/
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#define IPQ_PWM_REG0 0
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#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0)
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#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16)
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#define IPQ_PWM_REG1 4
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#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0)
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/*
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* Enable bit is set to enable output toggling in pwm device.
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* Update bit is set to trigger the change and is unset automatically
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* to reflect the changed divider and high duration values in register.
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*/
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#define IPQ_PWM_REG1_UPDATE BIT(30)
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#define IPQ_PWM_REG1_ENABLE BIT(31)
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/*
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* The max value specified for each field is based on the number of bits
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* in the pwm control register for that field (16-bit)
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*/
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#define IPQ_PWM_MAX_DIV FIELD_MAX(IPQ_PWM_REG0_PWM_DIV)
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struct ipq_pwm_chip {
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void __iomem *mem;
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unsigned long clk_rate;
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};
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static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip)
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{
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return pwmchip_get_drvdata(chip);
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}
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static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int reg)
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{
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struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(pwm->chip);
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unsigned int off = 8 * pwm->hwpwm + reg;
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|
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return readl(ipq_chip->mem + off);
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}
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|
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static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg,
|
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unsigned int val)
|
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{
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struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(pwm->chip);
|
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unsigned int off = 8 * pwm->hwpwm + reg;
|
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|
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writel(val, ipq_chip->mem + off);
|
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}
|
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|
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static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
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const struct pwm_state *state)
|
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{
|
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struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
|
||||
unsigned int pre_div, pwm_div;
|
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u64 period_ns, duty_ns;
|
||||
unsigned long val = 0;
|
||||
unsigned long hi_dur;
|
||||
|
||||
if (!state->enabled) {
|
||||
/* clear IPQ_PWM_REG1_ENABLE */
|
||||
ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, IPQ_PWM_REG1_UPDATE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (state->polarity != PWM_POLARITY_NORMAL)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Check the upper and lower bounds for the period as per
|
||||
* hardware limits
|
||||
*/
|
||||
if (state->period < IPQ_PWM_MIN_PERIOD_NS)
|
||||
return -ERANGE;
|
||||
period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);
|
||||
duty_ns = min(state->duty_cycle, period_ns);
|
||||
|
||||
/*
|
||||
* Pick the maximal value for PWM_DIV that still allows a
|
||||
* 100% relative duty cycle. This allows a fine grained
|
||||
* selection of duty cycles.
|
||||
*/
|
||||
pwm_div = IPQ_PWM_MAX_DIV - 1;
|
||||
|
||||
/*
|
||||
* although mul_u64_u64_div_u64 returns a u64, in practice it
|
||||
* won't overflow due to above constraints. Take the max period
|
||||
* of 10^9 (NSEC_PER_SEC) and the pwm_div + 1 (IPQ_PWM_MAX_DIV)
|
||||
* 10^9 * 10^8
|
||||
* ------------- => which fits well into a 32-bit unsigned int.
|
||||
* 10^9 * 65,535
|
||||
*/
|
||||
pre_div = mul_u64_u64_div_u64(period_ns, ipq_chip->clk_rate,
|
||||
(u64)NSEC_PER_SEC * (pwm_div + 1));
|
||||
|
||||
if (!pre_div)
|
||||
return -ERANGE;
|
||||
|
||||
pre_div -= 1;
|
||||
|
||||
if (pre_div > IPQ_PWM_MAX_DIV)
|
||||
pre_div = IPQ_PWM_MAX_DIV;
|
||||
|
||||
/* pwm duty = HI_DUR * (PRE_DIV + 1) / clk_rate */
|
||||
hi_dur = mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate,
|
||||
(u64)NSEC_PER_SEC * (pre_div + 1));
|
||||
|
||||
val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |
|
||||
FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);
|
||||
ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val);
|
||||
|
||||
val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div);
|
||||
ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
|
||||
|
||||
/* PWM enable toggle needs a separate write to REG1 */
|
||||
val |= IPQ_PWM_REG1_UPDATE | IPQ_PWM_REG1_ENABLE;
|
||||
ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
struct pwm_state *state)
|
||||
{
|
||||
struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
|
||||
unsigned int pre_div, pwm_div, hi_dur;
|
||||
u64 effective_div, hi_div;
|
||||
u32 reg0, reg1;
|
||||
|
||||
reg1 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG1);
|
||||
state->enabled = reg1 & IPQ_PWM_REG1_ENABLE;
|
||||
|
||||
if (!state->enabled)
|
||||
return 0;
|
||||
|
||||
reg0 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG0);
|
||||
|
||||
state->polarity = PWM_POLARITY_NORMAL;
|
||||
|
||||
pwm_div = FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0);
|
||||
hi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0);
|
||||
pre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1);
|
||||
|
||||
effective_div = (u64)(pwm_div + 1) * (pre_div + 1);
|
||||
|
||||
/*
|
||||
* effective_div <= 0x100000000, so the multiplication doesn't overflow.
|
||||
*/
|
||||
state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC,
|
||||
ipq_chip->clk_rate);
|
||||
|
||||
hi_div = hi_dur * (pre_div + 1);
|
||||
state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC,
|
||||
ipq_chip->clk_rate);
|
||||
|
||||
/*
|
||||
* ensure a valid config is passed back to PWM core in case duty_cycle
|
||||
* is > period (>100%)
|
||||
*/
|
||||
state->duty_cycle = min(state->duty_cycle, state->period);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pwm_ops ipq_pwm_ops = {
|
||||
.apply = ipq_pwm_apply,
|
||||
.get_state = ipq_pwm_get_state,
|
||||
};
|
||||
|
||||
static int ipq_pwm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct ipq_pwm_chip *pwm;
|
||||
struct pwm_chip *chip;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
chip = devm_pwmchip_alloc(dev, 4, sizeof(*pwm));
|
||||
if (IS_ERR(chip))
|
||||
return PTR_ERR(chip);
|
||||
pwm = ipq_pwm_from_chip(chip);
|
||||
|
||||
pwm->mem = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(pwm->mem))
|
||||
return dev_err_probe(dev, PTR_ERR(pwm->mem),
|
||||
"Failed to acquire resource\n");
|
||||
|
||||
clk = devm_clk_get_enabled(dev, NULL);
|
||||
if (IS_ERR(clk))
|
||||
return dev_err_probe(dev, PTR_ERR(clk),
|
||||
"Failed to get clock\n");
|
||||
|
||||
ret = devm_clk_rate_exclusive_get(dev, clk);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to lock clock rate\n");
|
||||
|
||||
pwm->clk_rate = clk_get_rate(clk);
|
||||
if (!pwm->clk_rate)
|
||||
return dev_err_probe(dev, -EINVAL, "Failed due to clock rate being zero\n");
|
||||
|
||||
chip->ops = &ipq_pwm_ops;
|
||||
|
||||
ret = devm_pwmchip_add(dev, chip);
|
||||
if (ret < 0)
|
||||
return dev_err_probe(dev, ret, "Failed to add pwm chip\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id pwm_ipq_dt_match[] = {
|
||||
{ .compatible = "qcom,ipq6018-pwm", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match);
|
||||
|
||||
static struct platform_driver ipq_pwm_driver = {
|
||||
.driver = {
|
||||
.name = "ipq-pwm",
|
||||
.of_match_table = pwm_ipq_dt_match,
|
||||
},
|
||||
.probe = ipq_pwm_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(ipq_pwm_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Qualcomm IPQ PWM driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -48,15 +48,15 @@ static void pwm_lpss_remove_pci(struct pci_dev *pdev)
|
|||
}
|
||||
|
||||
static const struct pci_device_id pwm_lpss_pci_ids[] = {
|
||||
{ PCI_VDEVICE(INTEL, 0x0ac8), (unsigned long)&pwm_lpss_bxt_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x0f08), (unsigned long)&pwm_lpss_byt_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x0f09), (unsigned long)&pwm_lpss_byt_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x11a5), (unsigned long)&pwm_lpss_tng_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)&pwm_lpss_bxt_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x2288), (unsigned long)&pwm_lpss_bsw_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x2289), (unsigned long)&pwm_lpss_bsw_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x31c8), (unsigned long)&pwm_lpss_bxt_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x5ac8), (unsigned long)&pwm_lpss_bxt_info},
|
||||
{ PCI_VDEVICE(INTEL, 0x0ac8), .driver_data = (unsigned long)&pwm_lpss_bxt_info },
|
||||
{ PCI_VDEVICE(INTEL, 0x0f08), .driver_data = (unsigned long)&pwm_lpss_byt_info },
|
||||
{ PCI_VDEVICE(INTEL, 0x0f09), .driver_data = (unsigned long)&pwm_lpss_byt_info },
|
||||
{ PCI_VDEVICE(INTEL, 0x11a5), .driver_data = (unsigned long)&pwm_lpss_tng_info },
|
||||
{ PCI_VDEVICE(INTEL, 0x1ac8), .driver_data = (unsigned long)&pwm_lpss_bxt_info },
|
||||
{ PCI_VDEVICE(INTEL, 0x2288), .driver_data = (unsigned long)&pwm_lpss_bsw_info },
|
||||
{ PCI_VDEVICE(INTEL, 0x2289), .driver_data = (unsigned long)&pwm_lpss_bsw_info },
|
||||
{ PCI_VDEVICE(INTEL, 0x31c8), .driver_data = (unsigned long)&pwm_lpss_bxt_info },
|
||||
{ PCI_VDEVICE(INTEL, 0x5ac8), .driver_data = (unsigned long)&pwm_lpss_bxt_info },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids);
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
/* PWM registers and bits definitions */
|
||||
#define PWMCON 0x00
|
||||
#define PWMCON_CLKDIV GENMASK(2, 0)
|
||||
#define PWMCON_CLKSEL BIT(3)
|
||||
#define PWMCON_OLD_PWM_MODE BIT(15)
|
||||
#define PWMHDUR 0x04
|
||||
#define PWMLDUR 0x08
|
||||
#define PWMGDUR 0x0c
|
||||
|
|
@ -38,6 +40,7 @@
|
|||
|
||||
struct pwm_mediatek_of_data {
|
||||
unsigned int num_pwms;
|
||||
bool clksel_fixup;
|
||||
bool pwm45_fixup;
|
||||
u16 pwm_ck_26m_sel_reg;
|
||||
unsigned int chanreg_base;
|
||||
|
|
@ -337,6 +340,7 @@ static int pwm_mediatek_write_waveform(struct pwm_chip *chip,
|
|||
|
||||
if (wfhw->enable) {
|
||||
u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
|
||||
u32 con_val = PWMCON_OLD_PWM_MODE | wfhw->con;
|
||||
|
||||
if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
|
||||
/*
|
||||
|
|
@ -364,7 +368,11 @@ static int pwm_mediatek_write_waveform(struct pwm_chip *chip,
|
|||
if (pc->soc->pwm_ck_26m_sel_reg)
|
||||
writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg);
|
||||
|
||||
pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | wfhw->con);
|
||||
/* Set BIT(3) to disable clock division */
|
||||
if (pc->soc->clksel_fixup)
|
||||
con_val |= PWMCON_CLKSEL;
|
||||
|
||||
pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, con_val);
|
||||
pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, wfhw->width);
|
||||
pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, wfhw->thres);
|
||||
} else {
|
||||
|
|
@ -496,6 +504,7 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
|
|||
|
||||
static const struct pwm_mediatek_of_data mt2712_pwm_data = {
|
||||
.num_pwms = 8,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.chanreg_base = 0x10,
|
||||
.chanreg_width = 0x40,
|
||||
|
|
@ -503,6 +512,7 @@ static const struct pwm_mediatek_of_data mt2712_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt6795_pwm_data = {
|
||||
.num_pwms = 7,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.chanreg_base = 0x10,
|
||||
.chanreg_width = 0x40,
|
||||
|
|
@ -510,6 +520,7 @@ static const struct pwm_mediatek_of_data mt6795_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt7622_pwm_data = {
|
||||
.num_pwms = 6,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
|
||||
.chanreg_base = 0x10,
|
||||
|
|
@ -518,6 +529,7 @@ static const struct pwm_mediatek_of_data mt7622_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt7623_pwm_data = {
|
||||
.num_pwms = 5,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = true,
|
||||
.chanreg_base = 0x10,
|
||||
.chanreg_width = 0x40,
|
||||
|
|
@ -525,13 +537,15 @@ static const struct pwm_mediatek_of_data mt7623_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt7628_pwm_data = {
|
||||
.num_pwms = 4,
|
||||
.pwm45_fixup = true,
|
||||
.clksel_fixup = true,
|
||||
.pwm45_fixup = false,
|
||||
.chanreg_base = 0x10,
|
||||
.chanreg_width = 0x40,
|
||||
};
|
||||
|
||||
static const struct pwm_mediatek_of_data mt7629_pwm_data = {
|
||||
.num_pwms = 1,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.chanreg_base = 0x10,
|
||||
.chanreg_width = 0x40,
|
||||
|
|
@ -539,6 +553,7 @@ static const struct pwm_mediatek_of_data mt7629_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt7981_pwm_data = {
|
||||
.num_pwms = 3,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
|
||||
.chanreg_base = 0x80,
|
||||
|
|
@ -547,6 +562,7 @@ static const struct pwm_mediatek_of_data mt7981_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt7986_pwm_data = {
|
||||
.num_pwms = 2,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
|
||||
.chanreg_base = 0x10,
|
||||
|
|
@ -555,6 +571,7 @@ static const struct pwm_mediatek_of_data mt7986_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt7988_pwm_data = {
|
||||
.num_pwms = 8,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.chanreg_base = 0x80,
|
||||
.chanreg_width = 0x40,
|
||||
|
|
@ -562,6 +579,7 @@ static const struct pwm_mediatek_of_data mt7988_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt8183_pwm_data = {
|
||||
.num_pwms = 4,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
|
||||
.chanreg_base = 0x10,
|
||||
|
|
@ -570,6 +588,7 @@ static const struct pwm_mediatek_of_data mt8183_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt8365_pwm_data = {
|
||||
.num_pwms = 3,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
|
||||
.chanreg_base = 0x10,
|
||||
|
|
@ -578,6 +597,7 @@ static const struct pwm_mediatek_of_data mt8365_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt8516_pwm_data = {
|
||||
.num_pwms = 5,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
|
||||
.chanreg_base = 0x10,
|
||||
|
|
@ -586,6 +606,7 @@ static const struct pwm_mediatek_of_data mt8516_pwm_data = {
|
|||
|
||||
static const struct pwm_mediatek_of_data mt6991_pwm_data = {
|
||||
.num_pwms = 4,
|
||||
.clksel_fixup = false,
|
||||
.pwm45_fixup = false,
|
||||
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL_V3,
|
||||
.chanreg_base = 0x100,
|
||||
|
|
|
|||
|
|
@ -538,7 +538,7 @@ static int __maybe_unused pca9685_pwm_runtime_resume(struct device *dev)
|
|||
}
|
||||
|
||||
static const struct i2c_device_id pca9685_id[] = {
|
||||
{ "pca9685" },
|
||||
{ .name = "pca9685" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, pca9685_id);
|
||||
|
|
|
|||
|
|
@ -161,6 +161,7 @@ static int pwm_probe(struct platform_device *pdev)
|
|||
const struct platform_device_id *id = platform_get_device_id(pdev);
|
||||
struct pwm_chip *chip;
|
||||
struct pxa_pwm_chip *pc;
|
||||
struct clk *bus_clk;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct reset_control *rst;
|
||||
int ret = 0;
|
||||
|
|
@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(chip);
|
||||
pc = to_pxa_pwm_chip(chip);
|
||||
|
||||
pc->clk = devm_clk_get(dev, NULL);
|
||||
bus_clk = devm_clk_get_optional_enabled(dev, "bus");
|
||||
if (IS_ERR(bus_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n");
|
||||
|
||||
/* Get named func clk if bus clock is valid */
|
||||
pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL);
|
||||
if (IS_ERR(pc->clk))
|
||||
return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n");
|
||||
|
||||
|
|
|
|||
|
|
@ -193,22 +193,6 @@ static int stm32_pwm_round_waveform_tohw(struct pwm_chip *chip,
|
|||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* This should be moved to lib/math/div64.c. Currently there are some changes
|
||||
* pending to mul_u64_u64_div_u64. Uwe will care for that when the dust settles.
|
||||
*/
|
||||
static u64 stm32_pwm_mul_u64_u64_div_u64_roundup(u64 a, u64 b, u64 c)
|
||||
{
|
||||
u64 res = mul_u64_u64_div_u64(a, b, c);
|
||||
/* Those multiplications might overflow but it doesn't matter */
|
||||
u64 rem = a * b - c * res;
|
||||
|
||||
if (rem)
|
||||
res += 1;
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip,
|
||||
struct pwm_device *pwm,
|
||||
const void *_wfhw,
|
||||
|
|
@ -223,16 +207,15 @@ static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip,
|
|||
u64 ccr_ns;
|
||||
|
||||
/* The result doesn't overflow for rate >= 15259 */
|
||||
wf->period_length_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1),
|
||||
NSEC_PER_SEC, rate);
|
||||
wf->period_length_ns = mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1),
|
||||
NSEC_PER_SEC, rate);
|
||||
|
||||
ccr_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr,
|
||||
NSEC_PER_SEC, rate);
|
||||
ccr_ns = mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr, NSEC_PER_SEC, rate);
|
||||
|
||||
if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) {
|
||||
wf->duty_length_ns =
|
||||
stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr),
|
||||
NSEC_PER_SEC, rate);
|
||||
mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr),
|
||||
NSEC_PER_SEC, rate);
|
||||
|
||||
wf->duty_offset_ns = ccr_ns;
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -67,16 +67,10 @@ fn ns_to_cycles(ns: u64, rate_hz: u64) -> u64 {
|
|||
ns.saturating_mul(rate_hz) / NSEC_PER_SEC_U64
|
||||
}
|
||||
|
||||
fn cycles_to_ns(cycles: u64, rate_hz: u64) -> u64 {
|
||||
fn cycles_to_ns(cycles: u32, rate_hz: u64) -> u64 {
|
||||
const NSEC_PER_SEC_U64: u64 = time::NSEC_PER_SEC as u64;
|
||||
|
||||
// TODO: Replace with a kernel helper like `mul_u64_u64_div_u64_roundup`
|
||||
// once available in Rust.
|
||||
let numerator = cycles
|
||||
.saturating_mul(NSEC_PER_SEC_U64)
|
||||
.saturating_add(rate_hz - 1);
|
||||
|
||||
numerator / rate_hz
|
||||
(u64::from(cycles) * NSEC_PER_SEC_U64).div_ceil(rate_hz)
|
||||
}
|
||||
|
||||
/// Hardware-specific waveform representation for TH1520.
|
||||
|
|
@ -192,15 +186,15 @@ fn round_waveform_fromhw(
|
|||
return Ok(());
|
||||
}
|
||||
|
||||
wf.period_length_ns = cycles_to_ns(u64::from(wfhw.period_cycles), rate_hz);
|
||||
wf.period_length_ns = cycles_to_ns(wfhw.period_cycles, rate_hz);
|
||||
|
||||
let duty_cycles = u64::from(wfhw.duty_cycles);
|
||||
let duty_cycles = wfhw.duty_cycles;
|
||||
|
||||
if (wfhw.ctrl_val & TH1520_PWM_FPOUT) != 0 {
|
||||
wf.duty_length_ns = cycles_to_ns(duty_cycles, rate_hz);
|
||||
wf.duty_offset_ns = 0;
|
||||
} else {
|
||||
let period_cycles = u64::from(wfhw.period_cycles);
|
||||
let period_cycles = wfhw.period_cycles;
|
||||
let original_duty_cycles = period_cycles.saturating_sub(duty_cycles);
|
||||
|
||||
// For an inverted signal, `duty_length_ns` is the high time (period - low_time).
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user