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arm64: dts: ti: k3-j7200: Add node to disable loopback connection

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CTRLMMR_MCU_SPI1_CTRL register controls if MCU_SPI1 is directly
connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1
and SPI3 are independently pinned out. By default, the field
SPI1_LINKDIS (Bit 0) is set to 0h. In order to disable the direct
connection, the SPI1_LINKDIS (Bit 0) needs to be set to 1h. Model
this functionality as a "reg-mux" device and based on the idle-state
property, enable/disable the connection bewtween MCU_SPI1 and MAIN_SPI3.

The register field description has been referred from J7200 TRM [1]
(Table 5-517. CTRLMMR_MCU_SPI1_CTRL Register Field Descriptions).

[1] https://www.ti.com/lit/pdf/spruiu1

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Link: https://lore.kernel.org/r/20241127075644.210759-1-a-dutta@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Anurag Dutta 2024-11-27 13:26:44 +05:30 committed by Nishanth Menon
parent b48888c9c4
commit 6b51892b31
2 changed files with 11 additions and 0 deletions
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4
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View File

@ -409,6 +409,10 @@ &serdes_ln_ctrl {
<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
};
&mcu_spi1 {
mux-controls = <&spi1_linkdis 0>;
};
&usb_serdes_mux {
idle-states = <1>; /* USB0 to SERDES lane 3 */
bootph-all;

7
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
View File

@ -184,6 +184,13 @@ phy_gmii_sel: phy@4040 {
reg = <0x4040 0x4>;
#phy-cells = <1>;
};
spi1_linkdis: mux-controller@4060 {
compatible = "reg-mux";
reg = <0x4060 0x4>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x1>;
};
};
wkup_conf: bus@43000000 {