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drm/amd/pm: Unify version check in SMUv11

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Use common helper function for firmware version check and logging in
SMUv11

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2026-03-20 11:01:02 +05:30 committed by Alex Deucher
parent c842980a21
commit 6b0a611628
7 changed files with 52 additions and 94 deletions
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14
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
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@ -25,18 +25,6 @@
#include "amdgpu_smu.h" #include "amdgpu_smu.h"
#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
#define SMU11_DRIVER_IF_VERSION_ARCT 0x17
#define SMU11_DRIVER_IF_VERSION_NV10 0x37
#define SMU11_DRIVER_IF_VERSION_NV12 0x38
#define SMU11_DRIVER_IF_VERSION_NV14 0x38
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x40
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD
#define SMU11_DRIVER_IF_VERSION_Cyan_Skillfish 0x8
/* MP Apertures */ /* MP Apertures */
#define MP0_Public 0x03800000 #define MP0_Public 0x03800000
#define MP0_SRAM 0x03900000 #define MP0_SRAM 0x03900000
@ -148,8 +136,6 @@ int smu_v11_0_setup_pptable(struct smu_context *smu);
int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu); int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
int smu_v11_0_check_fw_version(struct smu_context *smu);
int smu_v11_0_set_driver_table_location(struct smu_context *smu); int smu_v11_0_set_driver_table_location(struct smu_context *smu);
int smu_v11_0_set_tool_table_location(struct smu_context *smu); int smu_v11_0_set_tool_table_location(struct smu_context *smu);

5
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
View File

@ -65,6 +65,8 @@
#define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
#define SMU_FEATURES_HIGH_SHIFT 32 #define SMU_FEATURES_HIGH_SHIFT 32
#define SMU11_DRIVER_IF_VERSION_ARCT 0x17
static const struct smu_feature_bits arcturus_dpm_features = { static const struct smu_feature_bits arcturus_dpm_features = {
.bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
@ -1905,7 +1907,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
/* pptable related */ /* pptable related */
.setup_pptable = arcturus_setup_pptable, .setup_pptable = arcturus_setup_pptable,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
.check_fw_version = smu_v11_0_check_fw_version, .check_fw_version = smu_cmn_check_fw_version,
.write_pptable = smu_cmn_write_pptable, .write_pptable = smu_cmn_write_pptable,
.set_driver_table_location = smu_v11_0_set_driver_table_location, .set_driver_table_location = smu_v11_0_set_driver_table_location,
.set_tool_table_location = smu_v11_0_set_tool_table_location, .set_tool_table_location = smu_v11_0_set_tool_table_location,
@ -1958,5 +1960,6 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
smu->table_map = arcturus_table_map; smu->table_map = arcturus_table_map;
smu->pwr_src_map = arcturus_pwr_src_map; smu->pwr_src_map = arcturus_pwr_src_map;
smu->workload_map = arcturus_workload_map; smu->workload_map = arcturus_workload_map;
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
smu_v11_0_init_msg_ctl(smu, arcturus_message_map); smu_v11_0_init_msg_ctl(smu, arcturus_message_map);
} }

3
drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
View File

@ -582,7 +582,7 @@ cyan_skillfish_get_enabled_mask(struct smu_context *smu,
static const struct pptable_funcs cyan_skillfish_ppt_funcs = { static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status, .check_fw_status = smu_v11_0_check_fw_status,
.check_fw_version = smu_v11_0_check_fw_version, .check_fw_version = smu_cmn_check_fw_version,
.init_power = smu_v11_0_init_power, .init_power = smu_v11_0_init_power,
.fini_power = smu_v11_0_fini_power, .fini_power = smu_v11_0_fini_power,
.init_smc_tables = cyan_skillfish_init_smc_tables, .init_smc_tables = cyan_skillfish_init_smc_tables,
@ -605,5 +605,6 @@ void cyan_skillfish_set_ppt_funcs(struct smu_context *smu)
smu->ppt_funcs = &cyan_skillfish_ppt_funcs; smu->ppt_funcs = &cyan_skillfish_ppt_funcs;
smu->table_map = cyan_skillfish_table_map; smu->table_map = cyan_skillfish_table_map;
smu->is_apu = true; smu->is_apu = true;
smu->smc_driver_if_version = MP1_DRIVER_IF_VERSION;
smu_v11_0_init_msg_ctl(smu, cyan_skillfish_message_map); smu_v11_0_init_msg_ctl(smu, cyan_skillfish_message_map);
} }

21
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
View File

@ -73,6 +73,10 @@ static const struct smu_feature_bits navi10_dpm_features = {
#define SMU_11_0_GFX_BUSY_THRESHOLD 15 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
#define SMU11_DRIVER_IF_VERSION_NV10 0x37
#define SMU11_DRIVER_IF_VERSION_NV12 0x38
#define SMU11_DRIVER_IF_VERSION_NV14 0x38
static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
@ -3308,7 +3312,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status, .check_fw_status = smu_v11_0_check_fw_status,
.setup_pptable = navi10_setup_pptable, .setup_pptable = navi10_setup_pptable,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
.check_fw_version = smu_v11_0_check_fw_version, .check_fw_version = smu_cmn_check_fw_version,
.write_pptable = smu_cmn_write_pptable, .write_pptable = smu_cmn_write_pptable,
.set_driver_table_location = smu_v11_0_set_driver_table_location, .set_driver_table_location = smu_v11_0_set_driver_table_location,
.set_tool_table_location = smu_v11_0_set_tool_table_location, .set_tool_table_location = smu_v11_0_set_tool_table_location,
@ -3361,11 +3365,26 @@ static const struct pptable_funcs navi10_ppt_funcs = {
void navi10_set_ppt_funcs(struct smu_context *smu) void navi10_set_ppt_funcs(struct smu_context *smu)
{ {
struct amdgpu_device *adev = smu->adev;
smu->ppt_funcs = &navi10_ppt_funcs; smu->ppt_funcs = &navi10_ppt_funcs;
smu->clock_map = navi10_clk_map; smu->clock_map = navi10_clk_map;
smu->feature_map = navi10_feature_mask_map; smu->feature_map = navi10_feature_mask_map;
smu->table_map = navi10_table_map; smu->table_map = navi10_table_map;
smu->pwr_src_map = navi10_pwr_src_map; smu->pwr_src_map = navi10_pwr_src_map;
smu->workload_map = navi10_workload_map; smu->workload_map = navi10_workload_map;
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
case IP_VERSION(11, 0, 0):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
break;
case IP_VERSION(11, 0, 9):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
break;
case IP_VERSION(11, 0, 5):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
break;
}
smu_v11_0_init_msg_ctl(smu, navi10_message_map); smu_v11_0_init_msg_ctl(smu, navi10_message_map);
} }

25
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View File

@ -3119,7 +3119,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status, .check_fw_status = smu_v11_0_check_fw_status,
.setup_pptable = sienna_cichlid_setup_pptable, .setup_pptable = sienna_cichlid_setup_pptable,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
.check_fw_version = smu_v11_0_check_fw_version, .check_fw_version = smu_cmn_check_fw_version,
.write_pptable = smu_cmn_write_pptable, .write_pptable = smu_cmn_write_pptable,
.set_driver_table_location = smu_v11_0_set_driver_table_location, .set_driver_table_location = smu_v11_0_set_driver_table_location,
.set_tool_table_location = smu_v11_0_set_tool_table_location, .set_tool_table_location = smu_v11_0_set_tool_table_location,
@ -3176,13 +3176,36 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.mode2_reset = sienna_cichlid_mode2_reset, .mode2_reset = sienna_cichlid_mode2_reset,
}; };
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x40
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
{ {
struct amdgpu_device *adev = smu->adev;
smu->ppt_funcs = &sienna_cichlid_ppt_funcs; smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
smu->clock_map = sienna_cichlid_clk_map; smu->clock_map = sienna_cichlid_clk_map;
smu->feature_map = sienna_cichlid_feature_mask_map; smu->feature_map = sienna_cichlid_feature_mask_map;
smu->table_map = sienna_cichlid_table_map; smu->table_map = sienna_cichlid_table_map;
smu->pwr_src_map = sienna_cichlid_pwr_src_map; smu->pwr_src_map = sienna_cichlid_pwr_src_map;
smu->workload_map = sienna_cichlid_workload_map; smu->workload_map = sienna_cichlid_workload_map;
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
case IP_VERSION(11, 0, 7):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
break;
case IP_VERSION(11, 0, 11):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
break;
case IP_VERSION(11, 0, 12):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
break;
case IP_VERSION(11, 0, 13):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
break;
}
smu_v11_0_init_msg_ctl(smu, sienna_cichlid_message_map); smu_v11_0_init_msg_ctl(smu, sienna_cichlid_message_map);
} }

75
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
View File

@ -192,81 +192,6 @@ int smu_v11_0_check_fw_status(struct smu_context *smu)
return -EIO; return -EIO;
} }
int smu_v11_0_check_fw_version(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
uint32_t if_version = 0xff, smu_version = 0xff;
uint8_t smu_program, smu_major, smu_minor, smu_debug;
int ret = 0;
ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
if (ret)
return ret;
smu_program = (smu_version >> 24) & 0xff;
smu_major = (smu_version >> 16) & 0xff;
smu_minor = (smu_version >> 8) & 0xff;
smu_debug = (smu_version >> 0) & 0xff;
if (smu->is_apu)
adev->pm.fw_version = smu_version;
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
case IP_VERSION(11, 0, 0):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
break;
case IP_VERSION(11, 0, 9):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
break;
case IP_VERSION(11, 0, 5):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
break;
case IP_VERSION(11, 0, 7):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
break;
case IP_VERSION(11, 0, 11):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
break;
case IP_VERSION(11, 5, 0):
case IP_VERSION(11, 5, 2):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
break;
case IP_VERSION(11, 0, 12):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
break;
case IP_VERSION(11, 0, 13):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
break;
case IP_VERSION(11, 0, 8):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
break;
case IP_VERSION(11, 0, 2):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
break;
default:
dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
amdgpu_ip_version(adev, MP1_HWIP, 0));
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
break;
}
/*
* 1. if_version mismatch is not critical as our fw is designed
* to be backward compatible.
* 2. New fw usually brings some optimizations. But that's visible
* only on the paired driver.
* Considering above, we just leave user a verbal message instead
* of halt driver loading.
*/
if (if_version != smu->smc_driver_if_version) {
dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
"smu fw program = %d, version = 0x%08x (%d.%d.%d)\n",
smu->smc_driver_if_version, if_version,
smu_program, smu_version, smu_major, smu_minor, smu_debug);
}
return ret;
}
static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
{ {
struct amdgpu_device *adev = smu->adev; struct amdgpu_device *adev = smu->adev;

3
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
View File

@ -2511,7 +2511,7 @@ static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entr
static const struct pptable_funcs vangogh_ppt_funcs = { static const struct pptable_funcs vangogh_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status, .check_fw_status = smu_v11_0_check_fw_status,
.check_fw_version = smu_v11_0_check_fw_version, .check_fw_version = smu_cmn_check_fw_version,
.init_smc_tables = vangogh_init_smc_tables, .init_smc_tables = vangogh_init_smc_tables,
.fini_smc_tables = smu_v11_0_fini_smc_tables, .fini_smc_tables = smu_v11_0_fini_smc_tables,
.init_power = smu_v11_0_init_power, .init_power = smu_v11_0_init_power,
@ -2561,5 +2561,6 @@ void vangogh_set_ppt_funcs(struct smu_context *smu)
smu->table_map = vangogh_table_map; smu->table_map = vangogh_table_map;
smu->workload_map = vangogh_workload_map; smu->workload_map = vangogh_workload_map;
smu->is_apu = true; smu->is_apu = true;
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION;
smu_v11_0_init_msg_ctl(smu, vangogh_message_map); smu_v11_0_init_msg_ctl(smu, vangogh_message_map);
} }