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rtw-next patches for -next

Browse Source 
Pull-request includes many random fixes and new features.
 
 Major changes are listed below:
 
 rtl8xxxu:
 
  * declare supported channel width by firmware report
 
 rtw88:
 
  * validate RX descriptor to avoid malformed data causing warnings
 
 rtw89:
 
  * support USB devices RTL8922AU
 
  * add sysfs entry to show SN and UUID for specific USB devices
 
  * support to switch USB 3.0 mode for higher performance
 
  * add more fields (mainly SIG-A/SIG-B) to radiotap in monitor mode
 
  * offload packed IO to firmware to reduce IO time (for USB devices)
 
  * add debugfs to diagnose BB healthy
 
  * more preparations for RTL8922DE
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Merge tag 'rtw-next-2026-06-03' of https://github.com/pkshih/rtw

Ping-Ke Shih says:
==================
rtw-next patches for -next

Pull-request includes many random fixes and new features.

Major changes are listed below:

rtl8xxxu:

 * declare supported channel width by firmware report

rtw88:

 * validate RX descriptor to avoid malformed data causing warnings

rtw89:

 * support USB devices RTL8922AU

 * add sysfs entry to show SN and UUID for specific USB devices

 * support to switch USB 3.0 mode for higher performance

 * add more fields (mainly SIG-A/SIG-B) to radiotap in monitor mode

 * offload packed IO to firmware to reduce IO time (for USB devices)

 * add debugfs to diagnose BB healthy

 * more preparations for RTL8922DE
==================

Signed-off-by: Johannes Berg <johannes.berg@intel.com>
This commit is contained in:
Johannes Berg 2026-06-03 13:58:19 +02:00
commit 6aded6c104
74 changed files with 6202 additions and 781 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
Documentation/ABI/testing/sysfs-class-ieee80211-rtw89 Normal file
View File

@ -0,0 +1,24 @@
What: /sys/class/ieee80211/phyX/rtw89_usb/serial_number
Date: May 2026
Contact: Johnson Tsai <wenjie.tsai@realtek.com>, linux-wireless@vger.kernel.org
Description: (Read) Serial number burned into EFUSE of the RTL8852CU-based
USB Wi-Fi adapter. Only present on devices that set the
RTW89_QUIRK_HW_INFO_SYSFS quirk (currently VID 0x28de /
PID 0x2432).
Format: %10phN (5 raw bytes printed as 10 lowercase hex
digits, no separators).
Example: 3642000123
What: /sys/class/ieee80211/phyX/rtw89_usb/uuid
Date: May 2026
Contact: Johnson Tsai <wenjie.tsai@realtek.com>, linux-wireless@vger.kernel.org
Description: (Read) UUID burned into EFUSE of the RTL8852CU-based USB Wi-Fi
adapter. Only present on devices that set the
RTW89_QUIRK_HW_INFO_SYSFS quirk (currently VID 0x28de /
PID 0x2432).
Format: %pUb (RFC 4122 UUID in lowercase with hyphens).
Example: aaec2b7c-0a55-4727-8de0-b30febccbbaa

1
drivers/net/wireless/realtek/rtl8xxxu/8188e.c
View File

@ -1866,6 +1866,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops = {
.has_tx_report = 1,
.init_reg_pkt_life_time = 1,
.gen2_thermal_meter = 1,
.hw_feature_report = 0,
.max_sec_cam_num = 32,
.adda_1t_init = 0x0b1b25a0,
.adda_1t_path_on = 0x0bdb25a0,

1
drivers/net/wireless/realtek/rtl8xxxu/8188f.c
View File

@ -1745,6 +1745,7 @@ struct rtl8xxxu_fileops rtl8188fu_fops = {
.init_reg_rxfltmap = 1,
.init_reg_pkt_life_time = 1,
.init_reg_hmtfr = 1,
.hw_feature_report = 1,
.ampdu_max_time = 0x70,
.ustime_tsf_edca = 0x28,
.max_aggr_num = 0x0c14,

1
drivers/net/wireless/realtek/rtl8xxxu/8192c.c
View File

@ -723,6 +723,7 @@ struct rtl8xxxu_fileops rtl8192cu_fops = {
.tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
.rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
.supports_ap = 1,
.hw_feature_report = 0,
.max_macid_num = 32,
.max_sec_cam_num = 32,
.adda_1t_init = 0x0b1b25a0,

1
drivers/net/wireless/realtek/rtl8xxxu/8192e.c
View File

@ -1751,6 +1751,7 @@ struct rtl8xxxu_fileops rtl8192eu_fops = {
.has_s0s1 = 0,
.gen2_thermal_meter = 1,
.needs_full_init = 1,
.hw_feature_report = 0,
.supports_ap = 1,
.max_macid_num = 128,
.max_sec_cam_num = 64,

1
drivers/net/wireless/realtek/rtl8xxxu/8192f.c
View File

@ -2074,6 +2074,7 @@ struct rtl8xxxu_fileops rtl8192fu_fops = {
.init_reg_rxfltmap = 1,
.init_reg_pkt_life_time = 1,
.init_reg_hmtfr = 1,
.hw_feature_report = 1,
.ampdu_max_time = 0x5e,
.ustime_tsf_edca = 0x50,
.max_aggr_num = 0x1f1f,

1
drivers/net/wireless/realtek/rtl8xxxu/8710b.c
View File

@ -1852,6 +1852,7 @@ struct rtl8xxxu_fileops rtl8710bu_fops = {
.init_reg_rxfltmap = 1,
.init_reg_pkt_life_time = 1,
.init_reg_hmtfr = 1,
.hw_feature_report = 0, /* TODO, it's different */
.ampdu_max_time = 0x5e,
/*
* The RTL8710BU vendor driver uses 0x50 here and it works fine,

1
drivers/net/wireless/realtek/rtl8xxxu/8723a.c
View File

@ -632,6 +632,7 @@ struct rtl8xxxu_fileops rtl8723au_fops = {
.rx_agg_buf_size = 16000,
.tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
.rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
.hw_feature_report = 0,
.max_sec_cam_num = 32,
.adda_1t_init = 0x0b1b25a0,
.adda_1t_path_on = 0x0bdb25a0,

1
drivers/net/wireless/realtek/rtl8xxxu/8723b.c
View File

@ -1746,6 +1746,7 @@ struct rtl8xxxu_fileops rtl8723bu_fops = {
.gen2_thermal_meter = 1,
.needs_full_init = 1,
.init_reg_hmtfr = 1,
.hw_feature_report = 0,
.ampdu_max_time = 0x5e,
.ustime_tsf_edca = 0x50,
.max_aggr_num = 0x0c14,

77
drivers/net/wireless/realtek/rtl8xxxu/core.c
View File

@ -14,6 +14,7 @@
*/
#include <linux/firmware.h>
#include <linux/iopoll.h>
#include "regs.h"
#include "rtl8xxxu.h"
@ -3915,6 +3916,46 @@ static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv,
return sta_info->macid;
}
static void rtl8xxxu_request_hw_feature(struct rtl8xxxu_priv *priv)
{
if (!priv->fops->hw_feature_report)
return;
rtl8xxxu_write8(priv, REG_C2HEVT_MSG_NORMAL, C2H_HW_FEATURE_DUMP);
}
static int rtl8xxxu_dump_hw_feature(struct rtl8xxxu_priv *priv)
{
static const u8 bw_map[8] = { 0, 0, 160, 5, 10, 20, 40, 80 };
struct rtl8xxxu_hw_feature *hw_feature = &priv->hw_feature;
u8 feature[13];
int i, ret;
u8 id, bw;
if (!priv->fops->hw_feature_report) {
hw_feature->max_bw = 40;
return 0;
}
ret = read_poll_timeout(rtl8xxxu_read8, id,
id == C2H_HW_FEATURE_REPORT,
10000, 800000, false,
priv, REG_C2HEVT_MSG_NORMAL);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(feature); i++)
feature[i] = rtl8xxxu_read8(priv, REG_C2HEVT_MSG_NORMAL + 2 + i);
rtl8xxxu_write8(priv, REG_C2HEVT_MSG_NORMAL, 0);
bw = u8_get_bits(feature[6], GENMASK(2, 0));
hw_feature->max_bw = bw_map[bw];
return 0;
}
static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
{
struct rtl8xxxu_priv *priv = hw->priv;
@ -3961,6 +4002,8 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
*/
rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
rtl8xxxu_request_hw_feature(priv);
for (int retry = 5; retry >= 0 ; retry--) {
ret = rtl8xxxu_download_firmware(priv);
dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
@ -3976,6 +4019,12 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
if (ret)
goto exit;
ret = rtl8xxxu_dump_hw_feature(priv);
if (ret) {
dev_err(dev, "failed to dump hw feature\n");
goto exit;
}
if (fops->phy_init_antenna_selection)
fops->phy_init_antenna_selection(priv);
@ -5126,7 +5175,7 @@ static void rtl8xxxu_tx_complete(struct urb *urb)
}
static void rtl8xxxu_dump_action(struct device *dev,
struct ieee80211_hdr *hdr)
struct ieee80211_hdr *hdr, unsigned int skb_len)
{
struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
u16 cap, timeout;
@ -5134,8 +5183,14 @@ static void rtl8xxxu_dump_action(struct device *dev,
if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
return;
if (skb_len < IEEE80211_MIN_ACTION_SIZE(action_code))
return;
switch (mgmt->u.action.action_code) {
case WLAN_ACTION_ADDBA_RESP:
if (skb_len < IEEE80211_MIN_ACTION_SIZE(addba_resp))
break;
cap = le16_to_cpu(mgmt->u.action.addba_resp.capab);
timeout = le16_to_cpu(mgmt->u.action.addba_resp.timeout);
dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
@ -5148,6 +5203,9 @@ static void rtl8xxxu_dump_action(struct device *dev,
le16_to_cpu(mgmt->u.action.addba_resp.status));
break;
case WLAN_ACTION_ADDBA_REQ:
if (skb_len < IEEE80211_MIN_ACTION_SIZE(addba_req))
break;
cap = le16_to_cpu(mgmt->u.action.addba_req.capab);
timeout = le16_to_cpu(mgmt->u.action.addba_req.timeout);
dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
@ -5437,7 +5495,7 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
}
if (ieee80211_is_action(hdr->frame_control))
rtl8xxxu_dump_action(dev, hdr);
rtl8xxxu_dump_action(dev, hdr, skb->len);
tx_info->rate_driver_data[0] = hw;
@ -7835,15 +7893,20 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
sband->ht_cap.ht_supported = true;
sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
IEEE80211_HT_CAP_SUP_WIDTH_20_40;
sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20;
if (priv->hw_feature.max_bw >= 40) {
sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
} else {
dev_info(&udev->dev, "hardware doesn't support HT40\n");
}
memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
sband->ht_cap.mcs.rx_mask[0] = 0xff;
sband->ht_cap.mcs.rx_mask[4] = 0x01;
if (priv->rf_paths > 1) {
if (priv->rf_paths > 1)
sband->ht_cap.mcs.rx_mask[1] = 0xff;
sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
}
sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;

2
drivers/net/wireless/realtek/rtl8xxxu/regs.h
View File

@ -447,6 +447,8 @@
/* 8188EU */
#define REG_32K_CTRL 0x0194
#define REG_C2HEVT_MSG_NORMAL 0x01a0
#define C2H_HW_FEATURE_REPORT 0x19
#define C2H_HW_FEATURE_DUMP 0xfd
/* 8192EU/8723BU/8812 */
#define REG_C2HEVT_CMD_ID_8723B 0x01ae
#define REG_C2HEVT_CLEAR 0x01af

7
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
View File

@ -1789,11 +1789,17 @@ struct rtl8xxxu_cfo_tracking {
#define RTL8XXXU_BC_MC_MACID1 1
#define RTL8XXXU_MAX_SEC_CAM_NUM 64
struct rtl8xxxu_hw_feature {
u8 max_bw;
};
struct rtl8xxxu_priv {
struct ieee80211_hw *hw;
struct usb_device *udev;
struct rtl8xxxu_fileops *fops;
struct rtl8xxxu_hw_feature hw_feature;
spinlock_t tx_urb_lock;
struct list_head tx_urb_free_list;
int tx_urb_free_count;
@ -2009,6 +2015,7 @@ struct rtl8xxxu_fileops {
u8 init_reg_pkt_life_time:1;
u8 init_reg_hmtfr:1;
u8 supports_concurrent:1;
u8 hw_feature_report:1;
u8 ampdu_max_time;
u8 ustime_tsf_edca;
u16 max_aggr_num;

17
drivers/net/wireless/realtek/rtlwifi/base.c
View File

@ -1369,18 +1369,19 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct ieee80211_mgmt *mgmt;
__le16 fc = rtl_get_fc(skb);
u8 *act = (u8 *)(((u8 *)skb->data + MAC80211_3ADDR_LEN));
u8 category;
if (!ieee80211_is_action(fc))
return true;
category = *act;
act++;
switch (category) {
mgmt = (void *)skb->data;
if (skb->len < IEEE80211_MIN_ACTION_SIZE(action_code))
return true;
switch (mgmt->u.action.category) {
case ACT_CAT_BA:
switch (*act) {
switch (mgmt->u.action.action_code) {
case ACT_ADDBAREQ:
if (mac->act_scanning)
return false;
@ -1394,9 +1395,11 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
struct ieee80211_sta *sta = NULL;
struct rtl_sta_info *sta_entry = NULL;
struct rtl_tid_data *tid_data;
struct ieee80211_mgmt *mgmt = (void *)skb->data;
u16 capab = 0, tid = 0;
if (skb->len < IEEE80211_MIN_ACTION_SIZE(addba_req))
return true;
rcu_read_lock();
sta = rtl_find_sta(hw, hdr->addr3);
if (sta == NULL) {

7
drivers/net/wireless/realtek/rtlwifi/pci.c
View File

@ -505,9 +505,10 @@ static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
}
}
if (ieee80211_is_action(fc)) {
struct ieee80211_mgmt *action_frame =
(struct ieee80211_mgmt *)skb->data;
if (action_frame->u.action.action_code ==
struct ieee80211_mgmt *action_frame = (void *)skb->data;
if (skb->len >= IEEE80211_MIN_ACTION_SIZE(action_code) &&
action_frame->u.action.action_code ==
WLAN_HT_ACTION_SMPS) {
dev_kfree_skb(skb);
goto tx_status_ok;

21
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
View File

@ -2355,7 +2355,7 @@ void rtl8821ae_card_disable(struct ieee80211_hw *hw)
rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
}
/* 3 <3> Hw Configutations */
/* 3 <3> Hw Configurations */
/* Wait until Rx DMA Finished before host sleep.
* FW Pause Rx DMA may happen when received packet doing DMA.
@ -3257,9 +3257,9 @@ static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
u32 ratr_value;
u8 ratr_index = 0;
u8 b_nmode = mac->ht_enable;
u8 mimo_ps = IEEE80211_SMPS_OFF;
u16 shortgi_rate;
u32 tmp_ratr_value;
u32 ratr_mask;
u8 curtxbw_40mhz = mac->bw_40;
u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1 : 0;
@ -3288,19 +3288,14 @@ static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
case WIRELESS_MODE_N_24G:
case WIRELESS_MODE_N_5G:
b_nmode = 1;
if (mimo_ps == IEEE80211_SMPS_STATIC) {
ratr_value &= 0x0007F005;
} else {
u32 ratr_mask;
if (get_rf_type(rtlphy) == RF_1T2R ||
get_rf_type(rtlphy) == RF_1T1R)
ratr_mask = 0x000ff005;
else
ratr_mask = 0x0f0ff005;
if (get_rf_type(rtlphy) == RF_1T2R ||
get_rf_type(rtlphy) == RF_1T1R)
ratr_mask = 0x000ff005;
else
ratr_mask = 0x0f0ff005;
ratr_value &= ratr_mask;
}
ratr_value &= ratr_mask;
break;
default:
if (rtlphy->rf_type == RF_1T2R)

2
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h
View File

@ -291,7 +291,7 @@ static inline int get_rx_desc_paggr(__le32 *__pdesc)
static inline int get_rx_status_desc_rpt_sel(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc + 1), BIT(28));
return le32_get_bits(*(__pdesc + 2), BIT(28));
}
static inline int get_rx_desc_rxmcs(__le32 *__pdesc)

3
drivers/net/wireless/realtek/rtw88/fw.c
View File

@ -279,6 +279,9 @@ static void rtw_fw_adaptivity_result(struct rtw_dev *rtwdev, u8 *payload,
const struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th;
struct rtw_c2h_adaptivity *result = (struct rtw_c2h_adaptivity *)payload;
if (!edcca_th)
return;
rtw_dbg(rtwdev, RTW_DBG_ADAPTIVITY,
"Adaptivity: density %x igi %x l2h_th_init %x l2h %x h2l %x option %x\n",
result->density, result->igi, result->l2h_th_init, result->l2h,

29
drivers/net/wireless/realtek/rtw88/pci.c
View File

@ -1042,20 +1042,21 @@ static int rtw_pci_get_hw_rx_ring_nr(struct rtw_dev *rtwdev,
static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci,
u8 hw_queue, u32 limit)
{
struct rtw_pci_rx_ring *ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU];
const struct rtw_chip_info *chip = rtwdev->chip;
struct napi_struct *napi = &rtwpci->napi;
struct rtw_pci_rx_ring *ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU];
struct rtw_rx_pkt_stat pkt_stat;
u32 pkt_desc_sz = chip->rx_pkt_desc_sz;
u32 buf_desc_sz = chip->rx_buf_desc_sz;
struct ieee80211_rx_status rx_status;
struct rtw_rx_pkt_stat pkt_stat;
struct sk_buff *skb, *new;
u32 cur_rp = ring->r.rp;
u32 count, rx_done = 0;
u32 pkt_offset;
u32 pkt_desc_sz = chip->rx_pkt_desc_sz;
u32 buf_desc_sz = chip->rx_buf_desc_sz;
dma_addr_t dma;
u32 new_len;
u8 *rx_desc;
dma_addr_t dma;
int ret;
count = rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci);
count = min(count, limit);
@ -1067,7 +1068,10 @@ static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci,
dma_sync_single_for_cpu(rtwdev->dev, dma, RTK_PCI_RX_BUF_SIZE,
DMA_FROM_DEVICE);
rx_desc = skb->data;
rtw_rx_query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status);
ret = rtw_rx_query_rx_desc(rtwdev, rx_desc,
&pkt_stat, &rx_status);
if (ret)
goto next_rp;
/* offset from rx_desc to payload */
pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz +
@ -1077,6 +1081,11 @@ static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci,
* discard the frame if none available
*/
new_len = pkt_stat.pkt_len + pkt_offset;
if (unlikely(new_len > RTK_PCI_RX_BUF_SIZE)) {
rtw_dbg(rtwdev, RTW_DBG_RX,
"oversized RX packet: %u\n", new_len);
goto next_rp;
}
new = dev_alloc_skb(new_len);
if (WARN_ONCE(!new, "rx routine starvation\n"))
goto next_rp;
@ -1711,9 +1720,9 @@ static void rtw_pci_napi_deinit(struct rtw_dev *rtwdev)
static pci_ers_result_t rtw_pci_io_err_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
netif_device_detach(netdev);
ieee80211_stop_queues(hw);
return PCI_ERS_RESULT_NEED_RESET;
}
@ -1730,12 +1739,12 @@ static pci_ers_result_t rtw_pci_io_slot_reset(struct pci_dev *pdev)
static void rtw_pci_io_resume(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
/* ack any pending wake events, disable PME */
pci_enable_wake(pdev, PCI_D0, 0);
netif_device_attach(netdev);
ieee80211_wake_queues(hw);
}
const struct pci_error_handlers rtw_pci_err_handler = {

31
drivers/net/wireless/realtek/rtw88/rx.c
View File

@ -3,6 +3,7 @@
*/
#include "main.h"
#include "mac.h"
#include "rx.h"
#include "ps.h"
#include "debug.h"
@ -261,9 +262,9 @@ static void rtw_rx_fill_rx_status(struct rtw_dev *rtwdev,
}
}
void rtw_rx_query_rx_desc(struct rtw_dev *rtwdev, void *rx_desc8,
struct rtw_rx_pkt_stat *pkt_stat,
struct ieee80211_rx_status *rx_status)
int rtw_rx_query_rx_desc(struct rtw_dev *rtwdev, void *rx_desc8,
struct rtw_rx_pkt_stat *pkt_stat,
struct ieee80211_rx_status *rx_status)
{
u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
struct rtw_rx_desc *rx_desc = rx_desc8;
@ -295,20 +296,28 @@ void rtw_rx_query_rx_desc(struct rtw_dev *rtwdev, void *rx_desc8,
pkt_stat->tsf_low = le32_get_bits(rx_desc->w5, RTW_RX_DESC_W5_TSFL);
if (unlikely(pkt_stat->rate >= DESC_RATE_MAX)) {
rtw_dbg(rtwdev, RTW_DBG_UNEXP,
"unexpected RX rate=0x%x\n", pkt_stat->rate);
if (unlikely(pkt_stat->rate >= DESC_RATE_MAX))
return -EINVAL;
pkt_stat->rate = DESC_RATE1M;
pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
}
if (unlikely(pkt_stat->drv_info_sz &&
pkt_stat->drv_info_sz != PHY_STATUS_SIZE))
return -EINVAL;
if (unlikely(pkt_stat->phy_status && !pkt_stat->drv_info_sz))
return -EINVAL;
if (unlikely(pkt_stat->pkt_len > IEEE80211_MAX_MPDU_LEN_VHT_11454))
return -EINVAL;
/* drv_info_sz is in unit of 8-bytes */
pkt_stat->drv_info_sz *= 8;
/* c2h cmd pkt's rx/phy status is not interested */
if (pkt_stat->is_c2h)
return;
return 0;
if (unlikely(pkt_stat->pkt_len <= FCS_LEN))
return -EINVAL;
phy_status = rx_desc8 + desc_sz + pkt_stat->shift;
hdr = phy_status + pkt_stat->drv_info_sz;
@ -318,5 +327,7 @@ void rtw_rx_query_rx_desc(struct rtw_dev *rtwdev, void *rx_desc8,
rtwdev->chip->ops->query_phy_status(rtwdev, phy_status, pkt_stat);
rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status);
return 0;
}
EXPORT_SYMBOL(rtw_rx_query_rx_desc);

6
drivers/net/wireless/realtek/rtw88/rx.h
View File

@ -45,9 +45,9 @@ struct rtw_rx_desc {
void rtw_rx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
struct sk_buff *skb);
void rtw_rx_query_rx_desc(struct rtw_dev *rtwdev, void *rx_desc8,
struct rtw_rx_pkt_stat *pkt_stat,
struct ieee80211_rx_status *rx_status);
int rtw_rx_query_rx_desc(struct rtw_dev *rtwdev, void *rx_desc8,
struct rtw_rx_pkt_stat *pkt_stat,
struct ieee80211_rx_status *rx_status);
void rtw_update_rx_freq_from_ie(struct rtw_dev *rtwdev, struct sk_buff *skb,
struct ieee80211_rx_status *rx_status,
struct rtw_rx_pkt_stat *pkt_stat);

8
drivers/net/wireless/realtek/rtw88/sdio.c
View File

@ -995,7 +995,13 @@ static void rtw_sdio_rxfifo_recv(struct rtw_dev *rtwdev, u32 rx_len)
while (true) {
rx_desc = skb->data;
rtw_rx_query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status);
ret = rtw_rx_query_rx_desc(rtwdev, rx_desc,
&pkt_stat, &rx_status);
if (ret) {
dev_kfree_skb_any(skb);
return;
}
pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz +
pkt_stat.shift;

25
drivers/net/wireless/realtek/rtw88/tx.c
View File

@ -196,6 +196,7 @@ void rtw_tx_report_purge_timer(struct timer_list *t)
void rtw_tx_report_enqueue(struct rtw_dev *rtwdev, struct sk_buff *skb, u8 sn)
{
struct rtw_tx_report *tx_report = &rtwdev->tx_report;
unsigned long timeout = RTW_TX_PROBE_TIMEOUT;
unsigned long flags;
u8 *drv_data;
@ -207,7 +208,11 @@ void rtw_tx_report_enqueue(struct rtw_dev *rtwdev, struct sk_buff *skb, u8 sn)
__skb_queue_tail(&tx_report->queue, skb);
spin_unlock_irqrestore(&tx_report->q_lock, flags);
mod_timer(&tx_report->purge_timer, jiffies + RTW_TX_PROBE_TIMEOUT);
if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D &&
rtwdev->hci.type == RTW_HCI_TYPE_USB)
timeout = msecs_to_jiffies(2500);
mod_timer(&tx_report->purge_timer, jiffies + timeout);
}
EXPORT_SYMBOL(rtw_tx_report_enqueue);
@ -619,31 +624,19 @@ static int rtw_txq_push_skb(struct rtw_dev *rtwdev,
return 0;
}
static struct sk_buff *rtw_txq_dequeue(struct rtw_dev *rtwdev,
struct rtw_txq *rtwtxq)
{
struct ieee80211_txq *txq = rtwtxq_to_txq(rtwtxq);
struct sk_buff *skb;
skb = ieee80211_tx_dequeue(rtwdev->hw, txq);
if (!skb)
return NULL;
return skb;
}
static void rtw_txq_push(struct rtw_dev *rtwdev,
struct rtw_txq *rtwtxq,
unsigned long frames)
{
struct ieee80211_txq *txq = rtwtxq_to_txq(rtwtxq);
struct sk_buff *skb;
unsigned long i;
int ret;
int i;
rcu_read_lock();
for (i = 0; i < frames; i++) {
skb = rtw_txq_dequeue(rtwdev, rtwtxq);
skb = ieee80211_tx_dequeue(rtwdev->hw, txq);
if (!skb)
break;

22
drivers/net/wireless/realtek/rtw88/usb.c
View File

@ -399,6 +399,7 @@ static bool rtw_usb_tx_agg_skb(struct rtw_usb *rtwusb, struct sk_buff_head *list
int agg_num = 0;
unsigned int align_next = 0;
u8 qsel;
int ret;
if (skb_queue_empty(list))
return false;
@ -456,7 +457,13 @@ static bool rtw_usb_tx_agg_skb(struct rtw_usb *rtwusb, struct sk_buff_head *list
tx_desc = (struct rtw_tx_desc *)skb_head->data;
qsel = le32_get_bits(tx_desc->w1, RTW_TX_DESC_W1_QSEL);
rtw_usb_write_port(rtwdev, qsel, skb_head, rtw_usb_write_port_tx_complete, txcb);
ret = rtw_usb_write_port(rtwdev, qsel, skb_head,
rtw_usb_write_port_tx_complete, txcb);
if (ret) {
ieee80211_purge_tx_queue(rtwdev->hw, &txcb->tx_ack_queue);
kfree(txcb);
return false;
}
return true;
}
@ -518,8 +525,10 @@ static int rtw_usb_write_data(struct rtw_dev *rtwdev,
ret = rtw_usb_write_port(rtwdev, qsel, skb,
rtw_usb_write_port_complete, skb);
if (unlikely(ret))
if (unlikely(ret)) {
rtw_err(rtwdev, "failed to do USB write, ret=%d\n", ret);
dev_kfree_skb_any(skb);
}
return ret;
}
@ -610,8 +619,8 @@ static void rtw_usb_rx_handler(struct work_struct *work)
u32 max_skb_len = pkt_desc_sz + PHY_STATUS_SIZE * 8 +
IEEE80211_MAX_MPDU_LEN_VHT_11454;
u32 pkt_offset, next_pkt, skb_len;
int limit, ret;
u8 *rx_desc;
int limit;
for (limit = 0; limit < 200; limit++) {
rx_skb = skb_dequeue(&rtwusb->rx_queue);
@ -627,8 +636,11 @@ static void rtw_usb_rx_handler(struct work_struct *work)
rx_desc = rx_skb->data;
do {
rtw_rx_query_rx_desc(rtwdev, rx_desc, &pkt_stat,
&rx_status);
ret = rtw_rx_query_rx_desc(rtwdev, rx_desc,
&pkt_stat, &rx_status);
if (ret)
break;
pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz +
pkt_stat.shift;

12
drivers/net/wireless/realtek/rtw89/Kconfig
View File

@ -157,6 +157,18 @@ config RTW89_8922AE
The variant 8922AE-VS has the same features except 1024-QAM.
config RTW89_8922AU
tristate "Realtek 8922AU USB wireless network (Wi-Fi 7) adapter"
depends on USB
select RTW89_CORE
select RTW89_USB
select RTW89_8922A
help
Select this option will enable support for 8922AU chipset
802.11be USB wireless network (Wi-Fi 7) adapter
supporting 2x2 2GHz/5GHz/6GHz 4096-QAM 160MHz channels.
config RTW89_DEBUG
bool

3
drivers/net/wireless/realtek/rtw89/Makefile
View File

@ -88,6 +88,9 @@ rtw89_8922a-objs := rtw8922a.o \
obj-$(CONFIG_RTW89_8922AE) += rtw89_8922ae.o
rtw89_8922ae-objs := rtw8922ae.o
obj-$(CONFIG_RTW89_8922AU) += rtw89_8922au.o
rtw89_8922au-objs := rtw8922au.o
rtw89_core-$(CONFIG_RTW89_DEBUG) += debug.o
obj-$(CONFIG_RTW89_PCI) += rtw89_pci.o

92
drivers/net/wireless/realtek/rtw89/chan.c
View File

@ -150,6 +150,8 @@ void rtw89_chan_create(struct rtw89_chan *chan, u8 center_chan, u8 primary_chan,
primary_freq);
chan->pri_sb_idx = rtw89_get_primary_sb_idx(center_chan, primary_chan,
bandwidth);
chan->rfsi_band = band == RTW89_BAND_2G ? RFSI_CTRL_BAND_2GHZ :
RFSI_CTRL_BAND_5_6GHZ;
}
static void _rtw89_chan_update_punctured(struct rtw89_dev *rtwdev,
@ -398,43 +400,6 @@ static u8 rtw89_entity_role_get_index(struct rtw89_dev *rtwdev)
}
}
const struct rtw89_chan *__rtw89_mgnt_chan_get(struct rtw89_dev *rtwdev,
const char *caller_message,
u8 link_index, bool nullchk)
{
struct rtw89_hal *hal = &rtwdev->hal;
struct rtw89_entity_mgnt *mgnt = &hal->entity_mgnt;
enum rtw89_chanctx_idx chanctx_idx;
u8 role_index;
lockdep_assert_wiphy(rtwdev->hw->wiphy);
if (unlikely(link_index >= __RTW89_MLD_MAX_LINK_NUM)) {
WARN(1, "link index %u is invalid (max link inst num: %d)\n",
link_index, __RTW89_MLD_MAX_LINK_NUM);
goto dflt;
}
role_index = rtw89_entity_role_get_index(rtwdev);
chanctx_idx = mgnt->chanctx_tbl[role_index][link_index];
if (chanctx_idx == RTW89_CHANCTX_IDLE)
goto dflt;
return rtw89_chan_get(rtwdev, chanctx_idx);
dflt:
if (unlikely(nullchk))
return NULL;
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"%s (%s): prefetch NULL on link index %u\n",
__func__, caller_message ?: "", link_index);
return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
}
EXPORT_SYMBOL(__rtw89_mgnt_chan_get);
bool rtw89_entity_check_hw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
switch (rtwdev->mlo_dbcc_mode) {
@ -457,6 +422,59 @@ void rtw89_entity_force_hw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
rtw89_debug(rtwdev, RTW89_DBG_CHAN, "%s: (none)\n", __func__);
}
void rtw89_entity_get_conf(struct rtw89_dev *rtwdev, struct rtw89_entity_conf *conf)
{
struct rtw89_entity_mgnt *mgnt = &rtwdev->hal.entity_mgnt;
enum rtw89_chanctx_idx idxes[ARRAY_SIZE(conf->chans)];
struct rtw89_vif *role;
u8 ridx;
int i;
lockdep_assert_wiphy(rtwdev->hw->wiphy);
memset(conf, 0, sizeof(*conf));
ridx = rtw89_entity_role_get_index(rtwdev);
role = mgnt->active_roles[ridx];
if (role) {
struct ieee80211_vif *vif = rtwvif_to_vif(role);
conf->is_mld = ieee80211_vif_is_mld(vif);
conf->en_emlsr = role->mlo_mode == RTW89_MLO_MODE_EMLSR;
}
for (i = 0; i < ARRAY_SIZE(idxes); i++)
idxes[i] = RTW89_CHANCTX_IDLE;
switch (rtwdev->mlo_dbcc_mode) {
default:
case MLO_2_PLUS_0_1RF:
set_bit(0, conf->hw_bitmap);
idxes[0] = mgnt->chanctx_tbl[ridx][0];
idxes[1] = idxes[0];
break;
case MLO_0_PLUS_2_1RF:
set_bit(1, conf->hw_bitmap);
idxes[1] = mgnt->chanctx_tbl[ridx][1];
idxes[0] = idxes[1];
break;
case MLO_1_PLUS_1_1RF:
set_bit(0, conf->hw_bitmap);
set_bit(1, conf->hw_bitmap);
idxes[0] = mgnt->chanctx_tbl[ridx][0];
idxes[1] = mgnt->chanctx_tbl[ridx][1];
break;
}
for (i = 0; i < ARRAY_SIZE(idxes); i++) {
if (idxes[i] == RTW89_CHANCTX_IDLE)
idxes[i] = RTW89_CHANCTX_0;
conf->chans[i] = rtw89_chan_get(rtwdev, idxes[i]);
}
}
EXPORT_SYMBOL(rtw89_entity_get_conf);
static enum rtw89_mlo_dbcc_mode
rtw89_entity_sel_mlo_dbcc_mode(struct rtw89_dev *rtwdev, u8 active_hws)
{

21
drivers/net/wireless/realtek/rtw89/chan.h
View File

@ -116,6 +116,13 @@ struct rtw89_entity_weight {
unsigned int active_roles;
};
struct rtw89_entity_conf {
bool is_mld;
bool en_emlsr;
DECLARE_BITMAP(hw_bitmap, __RTW89_MLD_MAX_LINK_NUM);
const struct rtw89_chan *chans[__RTW89_MLD_MAX_LINK_NUM];
};
static inline bool rtw89_get_entity_state(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx)
{
@ -168,6 +175,7 @@ void rtw89_entity_init(struct rtw89_dev *rtwdev);
enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev);
bool rtw89_entity_check_hw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw89_entity_force_hw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw89_entity_get_conf(struct rtw89_dev *rtwdev, struct rtw89_entity_conf *conf);
void rtw89_chanctx_work(struct wiphy *wiphy, struct wiphy_work *work);
void rtw89_queue_chanctx_work(struct rtw89_dev *rtwdev);
void rtw89_queue_chanctx_change(struct rtw89_dev *rtwdev,
@ -180,19 +188,6 @@ void rtw89_chanctx_pause(struct rtw89_dev *rtwdev,
void rtw89_chanctx_proceed(struct rtw89_dev *rtwdev,
const struct rtw89_chanctx_cb_parm *cb_parm);
const struct rtw89_chan *__rtw89_mgnt_chan_get(struct rtw89_dev *rtwdev,
const char *caller_message,
u8 link_index, bool nullchk);
#define rtw89_mgnt_chan_get(rtwdev, link_index) \
__rtw89_mgnt_chan_get(rtwdev, __func__, link_index, false)
static inline const struct rtw89_chan *
rtw89_mgnt_chan_get_or_null(struct rtw89_dev *rtwdev, u8 link_index)
{
return __rtw89_mgnt_chan_get(rtwdev, NULL, link_index, true);
}
struct rtw89_mcc_links_info {
struct rtw89_vif_link *links[NUM_OF_RTW89_MCC_ROLES];
};

815
drivers/net/wireless/realtek/rtw89/core.c
View File

File diff suppressed because it is too large Load Diff

347
drivers/net/wireless/realtek/rtw89/core.h
View File

@ -24,9 +24,13 @@ struct rtw89_h2c_rf_tssi;
struct rtw89_fw_txpwr_track_cfg;
struct rtw89_phy_rfk_log_fmt;
struct rtw89_phy_calc_efuse_gain;
union rtw89_phy_sts_ie09;
struct rtw89_phy_sts_ie10;
struct rtw89_debugfs;
struct rtw89_regd_data;
struct rtw89_wow_cam_info;
struct rtw89_bb_wrap_data;
struct rtw89_fw_cmd_ofld_info;
extern const struct ieee80211_ops rtw89_ops;
@ -55,14 +59,17 @@ extern const struct ieee80211_ops rtw89_ops;
#define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
#define DELTA_SWINGIDX_SIZE 30
#define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
#define RTW89_RADIOTAP_ROOM_VHT sizeof(struct ieee80211_radiotap_vht)
#define RTW89_RADIOTAP_ROOM_HE (sizeof(struct ieee80211_radiotap_he) + \
sizeof(struct ieee80211_radiotap_he_mu))
#define RTW89_RADIOTAP_ROOM_EHT \
(sizeof(struct ieee80211_radiotap_tlv) + \
ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
sizeof(struct ieee80211_radiotap_tlv) + \
ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
#define RTW89_RADIOTAP_ROOM \
ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
ALIGN(max3(RTW89_RADIOTAP_ROOM_VHT, RTW89_RADIOTAP_ROOM_HE, \
RTW89_RADIOTAP_ROOM_EHT), 64)
#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
#define RTW89_HTC_VARIANT_HE 3
@ -839,7 +846,7 @@ struct rtw89_rx_phy_ppdu {
u8 mac_id;
u8 chan_idx;
u8 phy_idx;
u8 ie;
u8 ie; /* enum rtw89_phy_status_bitmap */
u16 rate;
u8 rpl_avg;
u8 rpl_path[RF_PATH_MAX];
@ -854,11 +861,15 @@ struct rtw89_rx_phy_ppdu {
} ofdm;
bool has_data;
bool has_bcn;
bool su;
bool ldpc;
bool stbc;
bool bf;
bool to_self;
bool valid;
bool hdr_2_en;
const union rtw89_phy_sts_ie09 *ie09; /* SIG-A */
const struct rtw89_phy_sts_ie10 *ie10; /* SIG-B */
};
enum rtw89_mac_idx {
@ -946,6 +957,21 @@ enum rtw89_bandwidth {
RTW89_CHANNEL_WIDTH_10 = 7,
};
enum rtw89_rx_ppdu_type {
RTW89_RX_PPDU_T_LCCK = 0,
RTW89_RX_PPDU_T_SCCK = 1,
RTW89_RX_PPDU_T_OFDM = 2,
RTW89_RX_PPDU_T_HT = 3,
RTW89_RX_PPDU_T_HTGF = 4,
RTW89_RX_PPDU_T_VHT_SU = 5,
RTW89_RX_PPDU_T_VHT_MU = 6,
RTW89_RX_PPDU_T_HE_SU = 7,
RTW89_RX_PPDU_T_HE_ERSU = 8,
RTW89_RX_PPDU_T_HE_MU = 9,
RTW89_RX_PPDU_T_HE_TB = 10,
RTW89_RX_PPDU_T_UNKNOWN = 15,
};
enum rtw89_ps_mode {
RTW89_PS_MODE_NONE = 0,
RTW89_PS_MODE_RFOFF = 1,
@ -972,6 +998,9 @@ enum rtw89_ru_bandwidth {
RTW89_RU106 = 2,
RTW89_RU52_26 = 3,
RTW89_RU106_26 = 4,
RTW89_RU484_242 = 5,
RTW89_RU996_484 = 6,
RTW89_RU996_484_242 = 7,
RTW89_RU_NUM,
};
@ -989,6 +1018,13 @@ enum rtw89_sc_offset {
RTW89_SC_40_LOWER = 10,
};
enum rtw89_rfsi_ctrl_band {
RFSI_CTRL_BAND_5_6GHZ,
RFSI_CTRL_BAND_2GHZ,
RFSI_CTRL_BAND_NUM,
};
/* only mgd features can be added to the enum */
enum rtw89_wow_flags {
RTW89_WOW_FLAG_EN_MAGIC_PKT,
@ -1012,6 +1048,7 @@ struct rtw89_chan {
enum rtw89_tx_comp_band tx_comp_band;
enum rtw89_sc_offset pri_ch_idx;
u8 pri_sb_idx;
enum rtw89_rfsi_ctrl_band rfsi_band;
};
struct rtw89_chan_rcd {
@ -1127,6 +1164,7 @@ struct rtw89_rx_desc_info {
bool hw_dec;
bool sw_dec;
bool addr1_match;
bool ampdu;
u8 frag;
u16 seq;
u8 frame_type;
@ -1477,6 +1515,10 @@ enum rtw89_tfc_lv {
DECLARE_EWMA(tp, 10, 2);
#define RTW89_TCP_TH 40
#define RTW89_UDP_RATIO_TH 70
#define RTW89_RECENT_ACTIVE_HIST GENMASK(4, 0)
struct rtw89_traffic_stats {
/* units in bytes */
u64 tx_unicast;
@ -1504,6 +1546,10 @@ struct rtw89_traffic_stats {
u16 tx_rate;
u16 rx_rate;
/* used by rtwvif only */
u64 tcp, udp, udp_ratio;
u8 active_histogram;
};
struct rtw89_btc_chdef {
@ -3479,6 +3525,7 @@ struct rtw89_ra_report {
struct rate_info txrate;
u32 bit_rate;
u16 hw_rate;
u8 retry_ratio;
bool might_fallback_legacy;
};
@ -3571,6 +3618,9 @@ struct rtw89_sta_link {
u32 data_tx_cnt_lmt:6;
};
#define RTW89_EFUSE_SN_LEN 5
#define RTW89_EFUSE_UUID_LEN 16
struct rtw89_efuse {
bool valid;
bool power_k_valid;
@ -3581,6 +3631,8 @@ struct rtw89_efuse {
u8 adc_td;
u8 bt_setting_2;
u8 bt_setting_3;
u8 sn[RTW89_EFUSE_SN_LEN];
u8 uuid[RTW89_EFUSE_UUID_LEN];
};
struct rtw89_phy_rate_pattern {
@ -3816,6 +3868,7 @@ struct rtw89_chip_ops {
enum rtw89_efuse_block block);
int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
void (*fem_setup)(struct rtw89_dev *rtwdev);
int (*data_setup)(struct rtw89_dev *rtwdev);
void (*rfe_gpio)(struct rtw89_dev *rtwdev);
void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
void (*rfk_init)(struct rtw89_dev *rtwdev);
@ -4122,6 +4175,7 @@ struct rtw89_dle_input {
u32 h2c_max_size;
u32 rx_amsdu_size; /* unit: KB */
u32 c2h_max_size;
u32 rls_rpt_max_size;
u32 mpdu_info_tbl_b0;
u32 mpdu_info_tbl_b1;
};
@ -4166,6 +4220,12 @@ struct rtw89_reg5_def {
u32 data;
};
#define RTW89_REGS_DEF(x) {x, ARRAY_SIZE(x)}
struct rtw89_regs_def {
const u32 *regs;
u32 reg_nr;
};
struct rtw89_reg_imr {
u32 addr;
u32 clr;
@ -4187,6 +4247,11 @@ struct rtw89_fw_def {
u16 fw_b_aid;
};
struct rtw89_qta_def {
const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_DLE_TYPE_NUM];
const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM];
};
struct rtw89_phy_table {
const struct rtw89_reg2_def *regs;
u32 n_regs;
@ -4478,6 +4543,54 @@ struct rtw89_edcca_regs {
u32 tx_collision_t2r_st_mask;
};
struct rtw89_pmac_regs {
struct rtw89_reg_def cck_txon;
struct rtw89_reg_def cck_txen;
struct rtw89_reg_def cck_cca;
struct rtw89_reg_def cck_sfd_gg;
struct rtw89_reg_def cck_sig_gg;
struct rtw89_reg_def cck_spoofing;
struct rtw89_reg_def cck_brk;
struct rtw89_reg_def brk;
struct rtw89_reg_def brk_option;
struct rtw89_reg_def search_fail;
struct rtw89_reg_def lsig_brk_s_th;
struct rtw89_reg_def lsig_brk_l_th;
struct rtw89_reg_def rxl_err_parity;
struct rtw89_reg_def rxl_err_rate;
struct rtw89_reg_def ofdm_cca;
struct rtw89_reg_def cca_spoofing;
struct rtw89_reg_def ampdu_miss;
struct rtw89_reg_def r1b_rx_rpt_rst;
struct rtw89_reg_def r1b_rr_sel;
struct rtw89_reg_def enable_all_cnt;
struct rtw89_reg_def rst_all_cnt;
u32 cck_crc32;
u32 cck_crc32_ok_mask;
u32 cck_crc32_fail_mask;
u32 ofdm_txon;
u32 ofdm_txon_mask;
u32 ofdm_txen_mask;
u32 l_crc;
u32 l_crc_ok_mask;
u32 l_crc_err_mask;
u32 ht_crc;
u32 ht_crc_ok_mask;
u32 ht_crc_err_mask;
u32 vht_crc;
u32 vht_crc_ok_mask;
u32 vht_crc_err_mask;
u32 he_crc;
u32 he_crc_ok_mask;
u32 he_crc_err_mask;
u32 eht_crc;
u32 eht_crc_ok_mask;
u32 eht_crc_err_mask;
u32 ampdu_crc;
u32 ampdu_crc_ok_mask;
u32 ampdu_crc_err_mask;
};
struct rtw89_phy_ul_tb_info {
bool dyn_tb_tri_en;
u8 def_if_bandedge;
@ -4502,6 +4615,16 @@ struct rtw89_antdiv_info {
bool get_stats;
};
struct rtw89_bb_stat_cfg {
bool enable;
u16 mac_id;
};
struct rtw89_phy_info {
const struct rtw89_bb_wrap_data *bb_wrap_data;
struct rtw89_bb_stat_cfg bb_stat_cfg;
};
enum rtw89_chanctx_state {
RTW89_CHANCTX_STATE_MCC_START,
RTW89_CHANCTX_STATE_MCC_STOP,
@ -4544,8 +4667,7 @@ struct rtw89_chip_info {
u16 max_rx_agg_num;
bool dis_2g_40m_ul_ofdma;
u32 rsvd_ple_ofst;
const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM];
const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM];
struct rtw89_qta_def qta_def;
u8 wde_qempty_acq_grpnum;
u8 wde_qempty_mgq_grpsel;
u32 rf_base_addr[2];
@ -4561,6 +4683,7 @@ struct rtw89_chip_info {
bool support_tas;
bool support_sar_by_ant;
bool support_noise;
bool support_fw_cmd_ofld;
bool ul_tb_waveform_ctrl;
bool ul_tb_pwr_diff;
bool rx_freq_from_ie;
@ -4663,6 +4786,7 @@ struct rtw89_chip_info {
struct rtw89_sb_regs btc_sb;
u32 dma_ch_mask;
const struct rtw89_edcca_regs *edcca_regs;
const struct rtw89_pmac_regs *pmac_regs;
const struct wiphy_wowlan_support *wowlan_stub;
const struct rtw89_xtal_info *xtal_info;
unsigned long default_quirks; /* bitmap of rtw89_quirks */
@ -4672,6 +4796,7 @@ struct rtw89_chip_variant {
bool no_mcs_12_13: 1;
u32 fw_min_ver_code;
const struct rtw89_fw_def *fw_def_override;
const struct rtw89_qta_def *qta_def_override;
};
union rtw89_bus_info {
@ -4683,6 +4808,7 @@ struct rtw89_driver_info {
const struct rtw89_chip_info *chip;
const struct rtw89_chip_variant *variant;
const struct dmi_system_id *quirks;
unsigned long dev_id_quirks; /* bitmap of rtw89_quirks */
union rtw89_bus_info bus;
};
@ -4821,6 +4947,7 @@ enum rtw89_fw_feature {
RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C,
RTW89_FW_FEATURE_LPS_ML_INFO_V1,
RTW89_FW_FEATURE_SER_POST_RECOVER_DMAC,
RTW89_FW_FEATURE_TX_HISTORY_V1,
NUM_OF_RTW89_FW_FEATURES,
};
@ -5170,6 +5297,9 @@ enum rtw89_dm_type {
RTW89_DM_THERMAL_PROTECT,
RTW89_DM_TAS,
RTW89_DM_MLO,
RTW89_DM_HW_SCAN,
RTW89_DM_INACTIVE_PS,
RTW89_DM_DIG_PD,
};
#define RTW89_THERMAL_PROT_LV_MAX 5
@ -5211,6 +5341,9 @@ struct rtw89_hal {
u8 thermal_prot_th;
u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */
u8 fixed_dig_pd_th; /* v = (X(dBm) + 102)/2 */
s8 fixed_dig_cck_pd_th; /* dBm */
};
#define RTW89_MAX_MAC_ID_NUM 128
@ -5248,6 +5381,7 @@ enum rtw89_quirks {
RTW89_QUIRK_PCI_BER,
RTW89_QUIRK_THERMAL_PROT_120C,
RTW89_QUIRK_THERMAL_PROT_110C,
RTW89_QUIRK_HW_INFO_SYSFS,
NUM_OF_RTW89_QUIRKS,
};
@ -5296,6 +5430,14 @@ struct rtw89_pkt_stat {
u8 beacon_rate;
u32 beacon_len;
u32 rx_rate_cnt[RTW89_HW_RATE_NR];
struct {
u32 ldpc;
u32 bcc;
u32 stbc;
u32 su_bf;
u32 su_non_bf;
u32 mu;
} rx;
};
#define RTW89_BCN_TRACK_STAT_NR 32
@ -5326,12 +5468,11 @@ struct rtw89_beacon_stat {
DECLARE_EWMA(thermal, 4, 4);
#define RTW89_TX_RATE_NR 40
struct rtw89_phy_stat {
struct ewma_thermal avg_thermal[RF_PATH_MAX];
u8 last_thermal_max;
struct ewma_rssi bcn_rssi;
struct rtw89_pkt_stat cur_pkt_stat;
struct rtw89_pkt_stat last_pkt_stat;
u32 tx_rate_cnt[RTW89_TX_RATE_NR];
struct rtw89_beacon_stat bcn_stat;
};
@ -5480,6 +5621,78 @@ struct rtw89_phy_ch_info {
u8 is_noisy;
};
struct rtw89_pmac_stat_info {
u32 cck_phy_txon;
u32 cck_mac_txen;
u32 ofdm_mac_txen;
u32 ofdm_phy_txon;
u32 cnt_ofdm_cca;
u32 cnt_cck_cca;
u32 cnt_cca_all;
u32 cnt_cck_spoofing;
u32 cnt_ofdm_spoofing;
u32 cnt_ampdu_miss;
u32 cnt_ampdu_crc_error;
u32 cnt_ampdu_crc_ok;
u32 cnt_cck_crc32_error;
u32 cnt_cck_crc32_ok;
u32 cnt_ofdm_crc32_error;
u32 cnt_ofdm_crc32_ok;
u32 cnt_ht_crc32_error;
u32 cnt_ht_crc32_ok;
u32 cnt_vht_crc32_error;
u32 cnt_vht_crc32_ok;
u32 cnt_he_crc32_ok;
u32 cnt_he_crc32_error;
u32 cnt_eht_crc32_ok;
u32 cnt_eht_crc32_error;
u32 cnt_crc32_error_all;
u32 cnt_crc32_ok_all;
u32 cnt_sfd_gg;
u32 cnt_sig_gg;
u32 cnt_cck_fail;
u32 cnt_ofdm_fail;
u32 cnt_fail_all;
u32 cnt_lsig_brk_s_th;
u32 cnt_lsig_brk_l_th;
u32 cnt_parity_fail;
u32 cnt_rate_illegal;
u32 cnt_sb_search_fail;
};
struct rtw89_tx_stat_info {
u32 info[6];
u32 common_ctrl[2];
u32 txpwr[2];
u8 type;
u8 subtype;
u8 txcmd;
u8 txsc;
u8 bw;
u16 tmac_txpwr;
u8 tx_path_en;
u8 path_map;
u8 max_mcs;
bool stbc;
};
enum rtw89_diag_bb_type {
RTW89_DIAG_BB_HANG,
RTW89_DIAG_BB_PD,
RTW89_DIAG_BB_NO_RX,
RTW89_DIAG_BB_FA,
RTW89_DIAG_BB_EDCCA,
RTW89_DIAG_BB_NR,
};
struct rtw89_diag_bb {
u32 diag_bb_bitmap; /* bitmap of enum rtw89_diag_bb_type */
u32 diag_bb_cnt[RTW89_DIAG_BB_NR];
u16 consecutive_no_tx_cnt;
u16 consecutive_no_rx_cnt;
};
struct rtw89_agc_gaincode_set {
u8 lna_idx;
u8 tia_idx;
@ -5495,6 +5708,7 @@ struct rtw89_dig_info {
struct rtw89_agc_gaincode_set cur_gaincode;
bool force_gaincode_idx_en;
struct rtw89_agc_gaincode_set force_gaincode;
enum rtw89_dig_noisy_level noisy_lv;
u8 igi_rssi_th[IGI_RSSI_TH_NUM];
u16 fa_th[FA_TH_NUM];
u8 igi_rssi;
@ -5504,6 +5718,7 @@ struct rtw89_dig_info {
u8 dyn_igi_min;
bool dyn_pd_th_en;
u8 dyn_pd_th_max;
u8 dyn_pd_max_cnt;
u8 pd_low_th_ofst;
u8 ib_pbk;
s8 ib_pkpwr;
@ -5768,6 +5983,7 @@ struct rtw89_env_monitor_info {
u8 nhm_th[RTW89_NHM_RPT_NUM];
struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM];
struct list_head nhm_rpt_list;
u8 edcca_clm_ratio;
};
enum rtw89_ser_rcvy_step {
@ -6188,10 +6404,26 @@ struct rtw89_tid_stats {
bool started;
};
struct rtw89_io_ops {
int (*pack)(struct rtw89_dev *rtwdev);
int (*unpack)(struct rtw89_dev *rtwdev);
void (*do_udelay)(struct rtw89_dev *rtwdev, u32 us);
void (*do_mdelay)(struct rtw89_dev *rtwdev, u32 ms);
void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
void (*phy_write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
void (*phy_write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
void (*phy_write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
void (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
u32 addr, u32 mask, u32 data);
};
struct rtw89_dev {
struct ieee80211_hw *hw;
struct device *dev;
const struct ieee80211_ops *ops;
const struct rtw89_io_ops *io;
bool dbcc_en;
bool support_mlo;
@ -6213,6 +6445,8 @@ struct rtw89_dev {
struct rtw89_rfe_data *rfe_data;
enum rtw89_custid custid;
struct rtw89_fw_cmd_ofld_info *fw_cmd_ofld_info;
struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM];
refcount_t refcount_ap_info;
@ -6277,6 +6511,7 @@ struct rtw89_dev {
struct rtw89_phy_efuse_gain efuse_gain;
struct rtw89_phy_ul_tb_info ul_tb_info;
struct rtw89_antdiv_info antdiv;
struct rtw89_phy_info phy_info;
struct rtw89_bb_ctx {
enum rtw89_phy_idx phy_idx;
@ -6284,6 +6519,12 @@ struct rtw89_dev {
struct rtw89_dig_info dig;
struct rtw89_phy_ch_info ch_info;
struct rtw89_edcca_bak edcca_bak;
struct ewma_rssi bcn_rssi;
struct rtw89_pkt_stat cur_pkt_stat;
struct rtw89_pkt_stat last_pkt_stat;
struct rtw89_pmac_stat_info pmac_stat;
struct rtw89_tx_stat_info tx_stat;
struct rtw89_diag_bb diag;
} bbs[RTW89_PHY_NUM];
struct wiphy_delayed_work track_work;
@ -6354,6 +6595,7 @@ struct rtw89_vif {
struct rtw89_roc roc;
bool offchan;
bool burst_active;
enum rtw89_mlo_mode mlo_mode;
struct rtw89_vif_ml_trans ml_trans;
@ -6492,6 +6734,9 @@ static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link)
static inline struct rtw89_sta_link *
rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid)
{
if (unlikely(macid >= RTW89_MAX_MAC_ID_NUM))
return NULL;
return rcu_dereference(rtwdev->assoc_link_on_macid[macid]);
}
@ -6673,6 +6918,38 @@ struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
return (struct rtw89_tx_skb_data *)info->driver_data;
}
static inline int rtw89_io_pack(struct rtw89_dev *rtwdev)
{
if (rtwdev->io->pack)
return rtwdev->io->pack(rtwdev);
return 0;
}
static inline int rtw89_io_unpack(struct rtw89_dev *rtwdev)
{
if (rtwdev->io->unpack)
return rtwdev->io->unpack(rtwdev);
return 0;
}
static inline void rtw89_io_udelay(struct rtw89_dev *rtwdev, u32 us)
{
if (rtwdev->io->do_udelay)
rtwdev->io->do_udelay(rtwdev, us);
else
udelay(us);
}
static inline void rtw89_io_mdelay(struct rtw89_dev *rtwdev, u32 ms)
{
if (rtwdev->io->do_mdelay)
rtwdev->io->do_mdelay(rtwdev, ms);
else
mdelay(ms);
}
static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
{
return rtwdev->hci.ops->read8(rtwdev, addr);
@ -6688,21 +6965,36 @@ static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
return rtwdev->hci.ops->read32(rtwdev, addr);
}
static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
static inline void rtw89_raw_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
{
rtwdev->hci.ops->write8(rtwdev, addr, data);
}
static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
static inline void rtw89_raw_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
{
rtwdev->hci.ops->write16(rtwdev, addr, data);
}
static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
static inline void rtw89_raw_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
{
rtwdev->hci.ops->write32(rtwdev, addr, data);
}
static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
{
rtwdev->io->write8(rtwdev, addr, data);
}
static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
{
rtwdev->io->write16(rtwdev, addr, data);
}
static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
{
rtwdev->io->write32(rtwdev, addr, data);
}
static inline void
rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
{
@ -6847,13 +7139,20 @@ rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
return rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
}
static inline void
rtw89_raw_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
u32 addr, u32 mask, u32 data)
{
rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
}
static inline void
rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
u32 addr, u32 mask, u32 data)
{
lockdep_assert_wiphy(rtwdev->hw->wiphy);
rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
rtwdev->io->write_rf(rtwdev, rf_path, addr, mask, data);
}
static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr)
@ -7212,6 +7511,16 @@ static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
chip->ops->fem_setup(rtwdev);
}
static inline int rtw89_chip_data_setup(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
if (!chip->ops->data_setup)
return 0;
return chip->ops->data_setup(rtwdev);
}
static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
@ -7449,6 +7758,17 @@ const struct rtw89_fw_def *rtw89_chip_get_fw_def(struct rtw89_dev *rtwdev)
return __rtw89_chip_get_fw_def(rtwdev->chip, rtwdev->variant);
}
static inline
const struct rtw89_qta_def *rtw89_chip_get_qta_def(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_variant *variant = rtwdev->variant;
if (variant && variant->qta_def_override)
return variant->qta_def_override;
return &rtwdev->chip->qta_def;
}
static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
const struct rtw89_txpwr_table *tbl)
{
@ -7816,8 +8136,7 @@ int rtw89_core_register(struct rtw89_dev *rtwdev);
void rtw89_core_unregister(struct rtw89_dev *rtwdev);
struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
u32 bus_data_size,
const struct rtw89_chip_info *chip,
const struct rtw89_chip_variant *variant);
const struct rtw89_driver_info *info);
void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);

940
drivers/net/wireless/realtek/rtw89/debug.c
View File

File diff suppressed because it is too large Load Diff

500
drivers/net/wireless/realtek/rtw89/fw.c
View File

@ -930,8 +930,9 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = {
__DIS_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, WITH_RFK_PRE_NOTIFY, G),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, RFK_PRE_NOTIFY_MCC_V1),
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 97, 0, SIM_SER_L0L1_BY_HALT_H2C),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 92, 0, TX_HISTORY_V1),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 100, 0, SER_POST_RECOVER_DMAC),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 108, 0, SIM_SER_L0L1_BY_HALT_H2C),
};
static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
@ -1208,12 +1209,17 @@ int rtw89_build_txpwr_trk_tbl_from_elm(struct rtw89_dev *rtwdev,
{
struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_hal *hal = &rtwdev->hal;
u16 aid = le16_to_cpu(elm->aid);
u32 needed_bitmap = 0;
u32 offset = 0;
int subband;
u32 bitmap;
int type;
if (aid && aid != hal->aid)
return 1;
if (chip->support_bands & BIT(NL80211_BAND_6GHZ))
needed_bitmap |= RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ;
if (chip->support_bands & BIT(NL80211_BAND_5GHZ))
@ -1417,12 +1423,18 @@ int rtw89_build_tx_comp_from_elm(struct rtw89_dev *rtwdev,
const union rtw89_fw_element_arg arg)
{
struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
struct rtw89_efuse *efuse = &rtwdev->efuse;
struct rtw89_hal *hal = &rtwdev->hal;
u8 rfe_type;
u16 aid;
aid = le16_to_cpu(elm->aid);
rfe_type = elm->u.tx_comp.rfe_type;
if (aid && aid != hal->aid)
return 1; /* ignore if aid not matched */
else if (rfe_type && rfe_type != efuse->rfe_type)
return 1; /* ignore if rfe_type not matched */
else if (elm_info->tx_comp)
return 1; /* ignore if an element is existing */
@ -2957,6 +2969,8 @@ static struct sk_buff *rtw89_arp_response_get(struct rtw89_dev *rtwdev,
ether_addr_copy(arp_skb->sender_hw, rtwvif_link->mac_addr);
arp_skb->sender_ip = rtwvif->ip_addr;
ether_addr_copy(arp_skb->target_hw, rtwvif_link->mac_addr);
arp_skb->target_ip = rtwvif->ip_addr;
return skb;
}
@ -3223,14 +3237,15 @@ int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev,
struct rtw89_vif *rtwvif)
{
const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
static const u8 bcn_bw_ofst[] = {0, 0, 0, 3, 6, 9, 0, 12};
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_efuse *efuse = &rtwdev->efuse;
struct rtw89_h2c_lps_ml_cmn_info *h2c;
struct rtw89_vif_link *rtwvif_link;
struct rtw89_pkt_stat *pkt_stat;
const struct rtw89_chan *chan;
u8 bw_idx = RTW89_BB_BW_20_40;
struct rtw89_bb_ctx *bb;
u32 len = sizeof(*h2c);
unsigned int link_id;
struct sk_buff *skb;
@ -3261,11 +3276,14 @@ int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev,
path = rtwvif_link->phy_idx == RTW89_PHY_1 ? RF_PATH_B : RF_PATH_A;
chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
h2c->central_ch[rtwvif_link->phy_idx] = chan->channel;
h2c->pri_ch[rtwvif_link->phy_idx] = chan->primary_channel;
h2c->band[rtwvif_link->phy_idx] = chan->band_type;
h2c->bw[rtwvif_link->phy_idx] = chan->band_width;
pkt_stat = &bb->cur_pkt_stat;
if (pkt_stat->beacon_rate < RTW89_HW_RATE_OFDM6)
h2c->bcn_rate_type[rtwvif_link->phy_idx] = 0x1;
else
@ -5584,6 +5602,127 @@ int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi
return ret;
}
int rtw89_fw_h2c_tx_history(struct rtw89_dev *rtwdev, u16 mac_id)
{
struct rtw89_bb_stat_cfg *bb_stat = &rtwdev->phy_info.bb_stat_cfg;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_h2c_ra_tx_history *h2c;
u32 len = sizeof(*h2c);
struct sk_buff *skb;
int ret;
if (chip->chip_gen == RTW89_CHIP_AX)
return 0;
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
if (!skb) {
rtw89_err(rtwdev, "failed to alloc skb for h2c tx history\n");
return -ENOMEM;
}
skb_put(skb, len);
h2c = (struct rtw89_h2c_ra_tx_history *)skb->data;
h2c->w0 = le32_encode_bits(mac_id, RTW89_H2C_RA_TX_HISTORY_W0_MACID) |
le32_encode_bits(0, RTW89_H2C_RA_TX_HISTORY_W0_PER_PPDU);
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA,
H2C_FUNC_OUTSRC_RA_TX_HISTORY, 0, 0, len);
ret = rtw89_h2c_tx(rtwdev, skb, false);
if (ret) {
rtw89_err(rtwdev, "failed to send h2c\n");
goto fail;
}
bb_stat->mac_id = mac_id;
return 0;
fail:
dev_kfree_skb_any(skb);
return ret;
}
int rtw89_fw_h2c_phy_ch_rpt(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_h2c_ra_phy_ch_rpt *h2c;
u32 len = sizeof(*h2c);
struct sk_buff *skb;
int ret;
if (chip->chip_gen == RTW89_CHIP_AX)
return 0;
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
if (!skb) {
rtw89_err(rtwdev, "failed to alloc skb for h2c phy ch rpt\n");
return -ENOMEM;
}
skb_put(skb, len);
h2c = (struct rtw89_h2c_ra_phy_ch_rpt *)skb->data;
h2c->w1 = le32_encode_bits(1, RTW89_H2C_RA_PHY_CH_RPT_W1_RPT_TX_COUNT);
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA,
H2C_FUNC_OUTSRC_RA_PHY_CH_RPT, 0, 0, len);
ret = rtw89_h2c_tx(rtwdev, skb, false);
if (ret) {
rtw89_err(rtwdev, "failed to send h2c\n");
goto fail;
}
return 0;
fail:
dev_kfree_skb_any(skb);
return ret;
}
int rtw89_fw_h2c_drv_ctrl_fw(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_h2c_ra_drv_ctrl_fw *h2c;
u32 len = sizeof(*h2c);
struct sk_buff *skb;
int ret;
if (chip->chip_gen == RTW89_CHIP_AX)
return 0;
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
if (!skb) {
rtw89_err(rtwdev, "failed to alloc skb for h2c drv ctrl fw\n");
return -ENOMEM;
}
skb_put(skb, len);
h2c = (struct rtw89_h2c_ra_drv_ctrl_fw *)skb->data;
h2c->w0 = le32_encode_bits(1, RTW89_H2C_RA_DRV_CTRL_FW_W0_RPT_TX_COUNT);
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA,
H2C_FUNC_OUTSRC_RA_DRV_CTRL_FW, 0, 0, len);
ret = rtw89_h2c_tx(rtwdev, skb, false);
if (ret) {
rtw89_err(rtwdev, "failed to send h2c\n");
goto fail;
}
return 0;
fail:
dev_kfree_skb_any(skb);
return ret;
}
int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type)
{
struct rtw89_btc *btc = &rtwdev->btc;
@ -8167,6 +8306,12 @@ void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev)
rtw89_info(rtwdev, "FW MISC = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM3));
rtw89_info(rtwdev, "R_AX_HALT_C2H = 0x%x\n",
rtw89_read32(rtwdev, R_AX_HALT_C2H));
rtw89_info(rtwdev, "R_AX_HALT_C2H_CTRL = 0x%x\n",
rtw89_read32(rtwdev, R_AX_HALT_C2H_CTRL));
rtw89_info(rtwdev, "R_AX_HALT_H2C = 0x%x\n",
rtw89_read32(rtwdev, R_AX_HALT_H2C));
rtw89_info(rtwdev, "R_AX_HALT_H2C_CTRL = 0x%x\n",
rtw89_read32(rtwdev, R_AX_HALT_H2C_CTRL));
rtw89_info(rtwdev, "R_AX_SER_DBG_INFO = 0x%x\n",
rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
@ -8318,7 +8463,7 @@ static int rtw89_update_6ghz_rnr_chan_ax(struct rtw89_dev *rtwdev,
struct sk_buff *skb;
bool found;
int ret = 0;
u8 i;
u32 i;
if (!req->n_6ghz_params)
return 0;
@ -9485,7 +9630,7 @@ int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtw
if (enable) {
ret = rtw89_fw_h2c_add_general_pkt(rtwdev, rtwvif_link,
RTW89_PKT_OFLD_TYPE_NULL_DATA,
RTW89_PKT_OFLD_TYPE_ARP_RSP,
&pkt_id);
if (ret)
return -EPERM;
@ -11344,3 +11489,350 @@ rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
return parms;
}
static int rtw89_fw_cmd_ofld_pack(struct rtw89_dev *rtwdev)
{
struct rtw89_fw_cmd_ofld_info *info = rtwdev->fw_cmd_ofld_info;
lockdep_assert_wiphy(rtwdev->hw->wiphy);
info->pack_level++;
return 0;
}
static void rtw89_fw_cmd_ofld_flush(struct rtw89_dev *rtwdev)
{
struct rtw89_fw_cmd_ofld_info *info = rtwdev->fw_cmd_ofld_info;
struct sk_buff *skb;
int ret;
u32 len;
len = info->cnt * sizeof(info->cmds[0]);
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
if (!skb) {
rtw89_err(rtwdev, "alloc skb fail\n");
return;
}
skb_put_data(skb, info->cmds, len);
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
H2C_CAT_MAC,
H2C_CL_MAC_FW_OFLD,
H2C_FUNC_CMD_OFLD_PKT, 0, 0,
len);
ret = rtw89_h2c_tx(rtwdev, skb, false);
if (ret) {
rtw89_err(rtwdev, "failed to send cmd ofld\n");
dev_kfree_skb_any(skb);
return;
}
if (info->accu_delay)
fsleep(info->accu_delay);
info->cnt = 0;
info->accu_delay = 0;
}
static int rtw89_fw_cmd_ofld_unpack(struct rtw89_dev *rtwdev)
{
struct rtw89_fw_cmd_ofld_info *info = rtwdev->fw_cmd_ofld_info;
lockdep_assert_wiphy(rtwdev->hw->wiphy);
if (info->pack_level == 0)
return -EFAULT;
if (--info->pack_level != 0)
return 0;
if (info->cnt == 0)
return 0;
rtw89_fw_cmd_ofld_flush(rtwdev);
return 0;
}
static int rtw89_fw_cmd_ofld_enqueue(struct rtw89_dev *rtwdev,
const struct rtw89_fw_cmd_ofld_arg *cmd)
{
struct rtw89_fw_cmd_ofld_info *info = rtwdev->fw_cmd_ofld_info;
struct rtw89_h2c_cmd_ofld *h2c;
u32 base_off;
lockdep_assert_wiphy(rtwdev->hw->wiphy);
if (info->pack_level == 0)
return 1;
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
if (cmd->type != RTW89_FW_CMD_OFLD_DELAY &&
cmd->src != RTW89_FW_CMD_OFLD_SRC_RF &&
cmd->src != RTW89_FW_CMD_OFLD_SRC_RF_DDIE &&
!IS_ALIGNED(cmd->offset, 4))
return -EFAULT;
if (info->cnt >= ARRAY_SIZE(info->cmds))
rtw89_fw_cmd_ofld_flush(rtwdev);
h2c = &info->cmds[info->cnt++];
h2c->w0 = le32_encode_bits(cmd->src, RTW89_H2C_CMD_OFLD_W0_SRC) |
le32_encode_bits(cmd->type, RTW89_H2C_CMD_OFLD_W0_TYPE) |
le32_encode_bits(cmd->rf_path, RTW89_H2C_CMD_OFLD_W0_PATH) |
le32_encode_bits(info->cnt, RTW89_H2C_CMD_OFLD_W0_CMD_NUM) |
le32_encode_bits(cmd->offset, RTW89_H2C_CMD_OFLD_W0_OFFSET);
if (cmd->src == RTW89_FW_CMD_OFLD_SRC_RF_DDIE)
base_off = 1;
else if (cmd->src == RTW89_FW_CMD_OFLD_SRC_RF)
base_off = 0;
else
base_off = cmd->offset >> 16;
h2c->w1 = le32_encode_bits(cmd->id, RTW89_H2C_CMD_OFLD_W1_ID) |
le32_encode_bits(base_off, RTW89_H2C_CMD_OFLD_W1_BASE_OFFSET);
h2c->w2 = le32_encode_bits(cmd->value, RTW89_H2C_CMD_OFLD_W2_VALUE);
h2c->w3 = le32_encode_bits(cmd->mask, RTW89_H2C_CMD_OFLD_W3_MASK);
if (cmd->type == RTW89_FW_CMD_OFLD_DELAY)
info->accu_delay += cmd->value;
return 0;
}
static const struct rtw89_io_ops rtw89_raw_io = {
.pack = NULL,
.unpack = NULL,
.write8 = rtw89_raw_write8,
.write16 = rtw89_raw_write16,
.write32 = rtw89_raw_write32,
.phy_write8 = rtw89_raw_phy_write8,
.phy_write16 = rtw89_raw_phy_write16,
.phy_write32 = rtw89_raw_phy_write32,
.write_rf = rtw89_raw_write_rf,
};
static
void rtw89_fw_cmd_ofld_phy_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
{
struct rtw89_fw_cmd_ofld_arg cmd = {
.src = RTW89_FW_CMD_OFLD_SRC_BB,
.type = RTW89_FW_CMD_OFLD_WRITE,
.offset = ALIGN_DOWN(addr, 4),
.mask = RTW89_W8_MASK_OF_ALIGNED_ADDR(addr),
.value = data,
};
int ret;
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
rtw89_raw_io.phy_write8(rtwdev, addr, data);
}
static
void rtw89_fw_cmd_ofld_phy_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
{
struct rtw89_fw_cmd_ofld_arg cmd = {
.src = RTW89_FW_CMD_OFLD_SRC_BB,
.type = RTW89_FW_CMD_OFLD_WRITE,
.offset = ALIGN_DOWN(addr, 2),
.mask = RTW89_W16_MASK_OF_ALIGNED_ADDR(addr),
.value = data,
};
int ret;
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
rtw89_raw_io.phy_write16(rtwdev, addr, data);
}
static
void rtw89_fw_cmd_ofld_phy_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
{
struct rtw89_fw_cmd_ofld_arg cmd = {
.src = RTW89_FW_CMD_OFLD_SRC_BB,
.type = RTW89_FW_CMD_OFLD_WRITE,
.offset = addr,
.mask = MASKDWORD,
.value = data,
};
int ret;
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
rtw89_raw_io.phy_write32(rtwdev, addr, data);
}
static
void rtw89_fw_cmd_ofld_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
{
struct rtw89_fw_cmd_ofld_arg cmd = {
.src = RTW89_FW_CMD_OFLD_SRC_MAC,
.type = RTW89_FW_CMD_OFLD_WRITE,
.offset = ALIGN_DOWN(addr, 4),
.mask = RTW89_W8_MASK_OF_ALIGNED_ADDR(addr),
.value = data,
};
int ret;
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
rtw89_raw_io.write8(rtwdev, addr, data);
}
static
void rtw89_fw_cmd_ofld_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
{
struct rtw89_fw_cmd_ofld_arg cmd = {
.src = RTW89_FW_CMD_OFLD_SRC_MAC,
.type = RTW89_FW_CMD_OFLD_WRITE,
.offset = ALIGN_DOWN(addr, 2),
.mask = RTW89_W16_MASK_OF_ALIGNED_ADDR(addr),
.value = data,
};
int ret;
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
rtw89_raw_io.write16(rtwdev, addr, data);
}
static
void rtw89_fw_cmd_ofld_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
{
struct rtw89_fw_cmd_ofld_arg cmd = {
.src = RTW89_FW_CMD_OFLD_SRC_MAC,
.type = RTW89_FW_CMD_OFLD_WRITE,
.offset = addr,
.mask = MASKDWORD,
.value = data,
};
int ret;
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
rtw89_raw_io.write32(rtwdev, addr, data);
}
static void rtw89_fw_cmd_ofld_write_rf_ddv(struct rtw89_dev *rtwdev,
struct rtw89_fw_cmd_ofld_arg *cmd,
enum rtw89_rf_path rf_path, u32 addr, u32 mask,
u32 data)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
*cmd = (typeof(*cmd)){
.src = RTW89_FW_CMD_OFLD_SRC_BB,
.type = RTW89_FW_CMD_OFLD_WRITE,
.rf_path = 0, /* Set rf_path to zero in rf_ddv */
.offset = chip->rf_base_addr[rf_path] + ((addr & 0xff) << 2),
.mask = mask,
.value = data,
};
}
static void rtw89_fw_cmd_ofld_write_rf_dav(struct rtw89_dev *rtwdev,
struct rtw89_fw_cmd_ofld_arg *cmd,
enum rtw89_rf_path rf_path, u32 addr, u32 mask,
u32 data)
{
*cmd = (typeof(*cmd)){
.src = RTW89_FW_CMD_OFLD_SRC_RF,
.type = RTW89_FW_CMD_OFLD_WRITE,
.rf_path = rf_path,
.offset = addr,
.mask = mask,
.value = data,
};
}
static void rtw89_fw_cmd_ofld_write_rf(struct rtw89_dev *rtwdev,
enum rtw89_rf_path rf_path, u32 addr, u32 mask,
u32 data)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
struct rtw89_fw_cmd_ofld_arg cmd;
int ret;
if (unlikely(rf_path >= chip->rf_path_num)) {
rtw89_warn(rtwdev, "unsupported rf path (%d) in fw offload\n", rf_path);
return;
}
if (ad_sel)
rtw89_fw_cmd_ofld_write_rf_ddv(rtwdev, &cmd, rf_path, addr, mask, data);
else
rtw89_fw_cmd_ofld_write_rf_dav(rtwdev, &cmd, rf_path, addr, mask, data);
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
rtw89_raw_io.write_rf(rtwdev, rf_path, addr, mask, data);
}
static void rtw89_fw_cmd_ofld_udelay(struct rtw89_dev *rtwdev, u32 us)
{
struct rtw89_fw_cmd_ofld_arg cmd = {
.src = RTW89_FW_CMD_OFLD_SRC_OTHER,
.type = RTW89_FW_CMD_OFLD_DELAY,
.value = us,
};
int ret;
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
udelay(us);
}
static void rtw89_fw_cmd_ofld_mdelay(struct rtw89_dev *rtwdev, u32 ms)
{
struct rtw89_fw_cmd_ofld_arg cmd = {
.src = RTW89_FW_CMD_OFLD_SRC_OTHER,
.type = RTW89_FW_CMD_OFLD_DELAY,
.value = ms * 1000,
};
int ret;
ret = rtw89_fw_cmd_ofld_enqueue(rtwdev, &cmd);
if (ret)
mdelay(ms);
}
static const struct rtw89_io_ops rtw89_fw_cmd_ofld_io = {
.pack = rtw89_fw_cmd_ofld_pack,
.unpack = rtw89_fw_cmd_ofld_unpack,
.do_udelay = rtw89_fw_cmd_ofld_udelay,
.do_mdelay = rtw89_fw_cmd_ofld_mdelay,
.write8 = rtw89_fw_cmd_ofld_write8,
.write16 = rtw89_fw_cmd_ofld_write16,
.write32 = rtw89_fw_cmd_ofld_write32,
.phy_write8 = rtw89_fw_cmd_ofld_phy_write8,
.phy_write16 = rtw89_fw_cmd_ofld_phy_write16,
.phy_write32 = rtw89_fw_cmd_ofld_phy_write32,
.write_rf = rtw89_fw_cmd_ofld_write_rf,
};
const struct rtw89_io_ops *
rtw89_fw_cmd_ofld_alloc_and_get_io_ops(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_fw_cmd_ofld_info *info;
if (!(rtwdev->hci.type == RTW89_HCI_TYPE_USB && chip->support_fw_cmd_ofld))
return &rtw89_raw_io;
info = devm_kzalloc(rtwdev->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return &rtw89_raw_io;
rtwdev->fw_cmd_ofld_info = info;
return &rtw89_fw_cmd_ofld_io;
}

115
drivers/net/wireless/realtek/rtw89/fw.h
View File

@ -471,6 +471,28 @@ struct rtw89_h2c_ra_v1 {
#define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
#define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
struct rtw89_h2c_ra_tx_history {
__le32 w0;
} __packed;
#define RTW89_H2C_RA_TX_HISTORY_W0_MACID GENMASK(15, 0)
#define RTW89_H2C_RA_TX_HISTORY_W0_PER_PPDU GENMASK(23, 16)
struct rtw89_h2c_ra_phy_ch_rpt {
__le32 w0;
__le32 w1;
__le32 w2;
__le32 w3;
} __packed;
#define RTW89_H2C_RA_PHY_CH_RPT_W1_RPT_TX_COUNT BIT(10)
struct rtw89_h2c_ra_drv_ctrl_fw {
__le32 w0;
} __packed;
#define RTW89_H2C_RA_DRV_CTRL_FW_W0_RPT_TX_COUNT BIT(13)
static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
{
le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
@ -3115,6 +3137,59 @@ struct rtw89_h2c_trx_protect {
#define RTW89_H2C_TRX_PROTECT_W1_CHINFO_EN BIT(0)
#define RTW89_H2C_TRX_PROTECT_W1_DFS_EN BIT(1)
enum rtw89_fw_cmd_ofld_arg_src {
RTW89_FW_CMD_OFLD_SRC_BB,
RTW89_FW_CMD_OFLD_SRC_RF,
RTW89_FW_CMD_OFLD_SRC_MAC,
RTW89_FW_CMD_OFLD_SRC_RF_DDIE,
RTW89_FW_CMD_OFLD_SRC_OTHER,
};
enum rtw89_fw_cmd_ofld_arg_type {
RTW89_FW_CMD_OFLD_WRITE,
RTW89_FW_CMD_OFLD_COMPARE,
RTW89_FW_CMD_OFLD_DELAY,
RTW89_FW_CMD_OFLD_MOVE,
};
struct rtw89_fw_cmd_ofld_arg {
enum rtw89_fw_cmd_ofld_arg_src src;
enum rtw89_fw_cmd_ofld_arg_type type;
enum rtw89_rf_path rf_path;
u32 value;
u32 mask;
u32 offset;
u16 id;
};
struct rtw89_h2c_cmd_ofld {
__le32 w0;
__le32 w1;
__le32 w2;
__le32 w3;
} __packed;
#define RTW89_H2C_CMD_OFLD_W0_SRC GENMASK(1, 0)
#define RTW89_H2C_CMD_OFLD_W0_TYPE GENMASK(3, 2)
#define RTW89_H2C_CMD_OFLD_W0_LC BIT(4)
#define RTW89_H2C_CMD_OFLD_W0_PATH GENMASK(6, 5)
#define RTW89_H2C_CMD_OFLD_W0_CMD_NUM GENMASK(14, 8)
#define RTW89_H2C_CMD_OFLD_W0_OFFSET GENMASK(31, 16)
#define RTW89_H2C_CMD_OFLD_W1_ID GENMASK(15, 0)
#define RTW89_H2C_CMD_OFLD_W1_BASE_OFFSET GENMASK(31, 16)
#define RTW89_H2C_CMD_OFLD_W2_VALUE GENMASK(31, 0)
#define RTW89_H2C_CMD_OFLD_W3_MASK GENMASK(31, 0)
#define RTW89_W8_MASK_OF_ALIGNED_ADDR(offset) (0xff << (((offset) & 0x3) << 3))
#define RTW89_W16_MASK_OF_ALIGNED_ADDR(offset) (0xffff << (((offset) & 0x2) * 8))
#define RTW89_FW_CMD_OFLD_NR 125
struct rtw89_fw_cmd_ofld_info {
unsigned int pack_level;
u32 cnt;
u32 accu_delay;
struct rtw89_h2c_cmd_ofld cmds[RTW89_FW_CMD_OFLD_NR];
};
struct rtw89_h2c_fwips {
__le32 w0;
} __packed;
@ -3833,14 +3908,16 @@ struct rtw89_c2h_done_ack {
#define RTW89_C2H_SCAN_DONE_ACK_RETURN GENMASK(5, 0)
#define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
#define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
#define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
#define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
#define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
struct rtw89_c2h_rev_ack {
__le32 w0;
__le32 w1;
__le32 w2;
} __packed;
#define RTW89_C2H_REV_ACK_W2_CAT GENMASK(1, 0)
#define RTW89_C2H_REV_ACK_W2_CLASS GENMASK(7, 2)
#define RTW89_C2H_REV_ACK_W2_FUNC GENMASK(15, 8)
#define RTW89_C2H_REV_ACK_W2_H2C_SEQ GENMASK(23, 16)
struct rtw89_fw_c2h_log_fmt {
__le16 signature;
@ -3918,6 +3995,13 @@ struct rtw89_c2h_lps_rpt {
*/
} __packed;
struct rtw89_c2h_ra_tx_history {
struct rtw89_c2h_hdr hdr;
__le32 ra_tbtt_cnt;
__le32 tx_rate_tot_cnt_hist[RTW89_TX_RATE_NR];
__le32 tx_cat_cnt[3];
} __packed;
struct rtw89_c2h_fw_scan_rpt {
struct rtw89_c2h_hdr hdr;
u8 phy_idx;
@ -4464,6 +4548,11 @@ struct rtw89_fw_element_hdr {
u8 rsvd[4];
u8 rules_and_msgs[];
} __packed diag_mac;
struct {
u8 rfe_type;
u8 priv[7];
u8 contents[];
} __packed tx_comp;
struct __rtw89_fw_txpwr_element txpwr;
struct __rtw89_fw_regd_element regd;
} __packed u;
@ -4606,6 +4695,7 @@ enum rtw89_fw_ofld_h2c_func {
H2C_FUNC_MAC_MACID_PAUSE = 0x8,
H2C_FUNC_USR_EDCA = 0xF,
H2C_FUNC_TSF32_TOGL = 0x10,
H2C_FUNC_CMD_OFLD_PKT = 0x13,
H2C_FUNC_OFLD_CFG = 0x14,
H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
H2C_FUNC_SCANOFLD = 0x17,
@ -4715,6 +4805,9 @@ enum rtw89_mrc_h2c_func {
#define H2C_CL_OUTSRC_RA 0x1
#define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
#define H2C_FUNC_OUTSRC_RA_TX_HISTORY 0x9
#define H2C_FUNC_OUTSRC_RA_PHY_CH_RPT 0xe
#define H2C_FUNC_OUTSRC_RA_DRV_CTRL_FW 0xf
#define H2C_CL_OUTSRC_DM 0x2
#define H2C_FUNC_FW_MCC_DIG 0x6
@ -5293,6 +5386,9 @@ int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
struct rtw89_rx_phy_ppdu *phy_ppdu);
int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
int rtw89_fw_h2c_phy_ch_rpt(struct rtw89_dev *rtwdev);
int rtw89_fw_h2c_tx_history(struct rtw89_dev *rtwdev, u16 mac_id);
int rtw89_fw_h2c_drv_ctrl_fw(struct rtw89_dev *rtwdev);
int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
@ -5737,4 +5833,7 @@ enum rtw89_wow_wakeup_ver {
RTW89_WOW_REASON_NUM,
};
const struct rtw89_io_ops *
rtw89_fw_cmd_ofld_alloc_and_get_io_ops(struct rtw89_dev *rtwdev);
#endif

153
drivers/net/wireless/realtek/rtw89/mac.c
View File

@ -894,11 +894,12 @@ EXPORT_SYMBOL(rtw89_mac_set_err_status);
static int hfc_reset_param(struct rtw89_dev *rtwdev)
{
const struct rtw89_qta_def *qta_def = rtw89_chip_get_qta_def(rtwdev);
const struct rtw89_hfc_param_ini *param_ini, *param_inis;
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
param_inis = rtwdev->chip->hfc_param_ini[rtwdev->hci.type];
param_inis = qta_def->hfc_param_ini[rtwdev->hci.dle_type];
if (!param_inis)
return -EINVAL;
@ -1716,18 +1717,27 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0},
.hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0, 2, 32, 0, 0},
.hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0, 0, 256, 0, 0},
.hfc_prec_cfg_c3 = {18, 32, 148, 148, 1, 1, 1, 1},
.hfc_prec_cfg_c5 = {18, 32, 148, 148, 1, 1, 0, 1},
.hfc_prec_cfg_c6 = {8, 32, 148, 148, 1, 1, 0, 1},
/* PCIE 64 */
.wde_size0 = {RTW89_WDE_PG_64, 4095, 1,},
.wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,},
/* 8852A USB */
.wde_size1 = {RTW89_WDE_PG_64, 768, 0,},
/* DLFW */
.wde_size3_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,},
.wde_size4 = {RTW89_WDE_PG_64, 0, 4096,},
.wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,},
/* 8922A USB3.0 */
.wde_size4_v1 = {RTW89_WDE_PG_64, 892, 4, 0,},
.wde_size5_v1 = {RTW89_WDE_PG_64, 864, 32, 0,},
/* PCIE 64 */
.wde_size6 = {RTW89_WDE_PG_64, 512, 0,},
/* 8852B PCIE SCC */
.wde_size7 = {RTW89_WDE_PG_64, 510, 2,},
/* 8922A USB2.0 */
.wde_size7_v1 = {RTW89_WDE_PG_64, 508, 4,},
.wde_size8_v1 = {RTW89_WDE_PG_64, 634, 6,},
/* DLFW */
.wde_size9 = {RTW89_WDE_PG_64, 0, 1024,},
.wde_size16_v1 = {RTW89_WDE_PG_64, 639, 1, 0,},
@ -1738,6 +1748,7 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.wde_size18_v1 = {RTW89_WDE_PG_64, 0, 640, 0,},
/* 8852C PCIE SCC */
.wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
.wde_size22_v1 = {RTW89_WDE_PG_128, 384, 0, 0,},
.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
/* 8852B USB2.0/USB3.0 SCC turbo */
.wde_size30 = {RTW89_WDE_PG_64, 220, 36,},
@ -1751,8 +1762,13 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,},
/* DLFW */
.ple_size4 = {RTW89_PLE_PG_128, 64, 1472,},
/* 8922A USB3.0 */
.ple_size4_v1 = {RTW89_PLE_PG_256, 1963, 109, 57344,},
/* PCIE 64 */
.ple_size6 = {RTW89_PLE_PG_128, 496, 16,},
/* 8922A USB2.0 */
.ple_size6_v1 = {RTW89_PLE_PG_256, 2059, 109, 32768,},
.ple_size7_v1 = {RTW89_PLE_PG_256, 2027, 109, 40960,},
/* DLFW */
.ple_size8 = {RTW89_PLE_PG_128, 64, 960,},
.ple_size9 = {RTW89_PLE_PG_128, 2288, 16,},
@ -1766,6 +1782,7 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,},
/* 8851B USB2.0 SCC turbo */
.ple_size27 = {RTW89_PLE_PG_128, 1396, 12,},
.ple_size29_v1 = {RTW89_PLE_PG_128, 1895, 182, 49152,},
/* 8852B USB3.0 SCC turbo */
.ple_size31 = {RTW89_PLE_PG_128, 1392, 16,},
/* 8852C USB2.0 */
@ -1778,10 +1795,16 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.wde_qt3 = {0, 0, 0, 0,},
/* DLFW */
.wde_qt4 = {0, 0, 0, 0,},
/* 8922A USB3.0 */
.wde_qt4_v1 = {876, 6, 0, 10,},
.wde_qt5_v1 = {838, 6, 0, 20,},
/* PCIE 64 */
.wde_qt6 = {448, 48, 0, 16,},
/* 8852B PCIE SCC */
.wde_qt7 = {446, 48, 0, 16,},
/* 8922A USB2.0 */
.wde_qt7_v1 = {492, 6, 0, 10,},
.wde_qt8_v1 = {608, 6, 0, 20,},
/* 8852C USB3.0 */
.wde_qt16 = {344, 2, 0, 8,},
/* 8852C DLFW */
@ -1790,6 +1813,7 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.wde_qt18 = {3228, 60, 0, 40,},
.wde_qt19_v1 = {613, 6, 0, 20,},
.wde_qt23 = {958, 48, 0, 16,},
.wde_qt23_v1 = {371, 3, 0, 10,},
/* 8852B USB2.0/USB3.0 SCC turbo */
.wde_qt30 = {210, 2, 0, 8,},
/* 8852C USB2.0 */
@ -1801,9 +1825,22 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
/* PCIE SCC */
.ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,},
.ple_qt5_v2 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,},
/* 8922A USB3.0 */
.ple_qt6_v1 = {1806, 0, 16, 24, 7, 14, 57, 0, 12, 9, 1, 4, 0,},
.ple_qt7_v1 = {1806, 0, 16, 24, 20, 27, 70, 0, 25, 9, 1, 17, 0,},
.ple_qt8_v1 = {1638, 0, 16, 24, 7, 14, 99, 99, 24, 9, 1, 4, 0,},
/* PCIE SCC */
.ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,},
/* 8922A USB3.0 */
.ple_qt9_v1 = {1638, 0, 16, 24, 35, 42, 127, 127, 52, 9, 1, 32, 0,},
/* 8922A USB2.0 */
.ple_qt12_v1 = {463, 0, 16, 24, 7, 14, 57, 0, 12, 9, 1, 4, 0,},
/* DLFW */
.ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,},
/* 8922A USB2.0 */
.ple_qt13_v1 = {463, 0, 16, 24, 1459, 1466, 1509, 0, 1464, 9, 1, 1456, 0,},
.ple_qt14_v1 = {939, 0, 16, 24, 7, 14, 57, 57, 24, 9, 1, 4, 0,},
.ple_qt15_v1 = {939, 0, 16, 24, 882, 889, 932, 932, 899, 9, 1, 879, 0,},
/* PCIE 64 */
.ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,},
/* 8852A USB SCC */
@ -1814,18 +1851,19 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.ple_qt28 = {1040, 0, 32, 48, 43, 13, 208, 0, 62, 14, 24, 0,},
/* USB 52C USB3.0 */
.ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
.ple_qt42_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,},
/* USB 52C USB3.0 */
.ple_qt43 = {3068, 0, 32, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
.ple_qt43_v2 = {645, 645, 32, 16, 2062, 2056, 2134, 2134, 2087, 2061, 1, 2047, 0, 0,},
/* DLFW 52C */
.ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
.ple_qt44_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,},
/* DLFW 52C */
.ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
.ple_qt45_v2 = {645, 645, 32, 2055, 2058, 2052, 2132, 2132, 2083, 2057, 1, 2043, 0, 0,},
/* 8852C PCIE SCC */
.ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,},
/* 8852C PCIE SCC */
.ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,},
.ple_qt47_v2 = {0, 0, 32, 2703, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,},
.ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,},
/* PCIE 64 */
.ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
@ -1833,6 +1871,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
/* 8851B USB2.0 SCC turbo */
.ple_qt61 = {858, 0, 16, 48, 4, 13, 370, 0, 32, 14, 8, 0, 0,},
.ple_qt62 = {858, 0, 32, 48, 37, 13, 403, 0, 65, 14, 24, 0, 0,},
.ple_qt64_v2 = {91, 91, 32, 16, 19, 13, 93, 93, 44, 34, 1, 4, 0, 0,},
.ple_qt65_v2 = {645, 645, 32, 1380, 1383, 1377, 1457, 1457, 1408, 1398, 1, 1368,},
/* USB2.0 52C */
.ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,},
/* USB2.0 52C */
@ -1847,23 +1887,30 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,},
.ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,},
.ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ple_rsvd_qt2 = {1, 56, 28, 6, 6, 6, 6, 0, 0, 0,},
.ple_rsvd_qt9 = {1, 44, 44, 6, 6, 6, 6, 69, 0, 0,},
.rsvd0_size0 = {212992, 0,},
.rsvd0_size3 = {57344, 0,},
.rsvd0_size5 = {32768, 0,},
.rsvd0_size6 = {40960, 0,},
.rsvd0_size17 = {49152, 0,},
.rsvd1_size0 = {587776, 2048,},
.rsvd1_size2 = {391168, 2048,},
.dle_input3 = {0, 0, 0, 16384, 0, 2048, 0, 0,},
.dle_input18 = {128, 128, 11454, 2048, 0, 2048, 24, 24,},
.rsvd1_size3 = {315008, 78208,},
.dle_input3 = {0, 0, 0, 16384, 0, 2048, 0, 0, 0,},
.dle_input20 = {128, 128, 11454, 2048, 0, 2048, 1024, 24, 24,},
.dle_input28 = {128, 128, 11454, 2048, 0, 2048, 2048, 24, 24,},
};
EXPORT_SYMBOL(rtw89_mac_size);
static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
enum rtw89_qta_mode mode)
{
const struct rtw89_qta_def *qta_def = rtw89_chip_get_qta_def(rtwdev);
struct rtw89_mac_info *mac = &rtwdev->mac;
const struct rtw89_dle_mem *cfg, *cfgs;
cfgs = rtwdev->chip->dle_mem[rtwdev->hci.dle_type];
cfgs = qta_def->dle_mem[rtwdev->hci.dle_type];
if (!cfgs)
return NULL;
@ -2300,6 +2347,8 @@ static int preload_init_set_ax(struct rtw89_dev *rtwdev, u8 mac_idx,
{
u32 reg, max_preld_size, min_rsvd_size;
rtw89_io_pack(rtwdev);
max_preld_size = (mac_idx == RTW89_MAC_0 ?
PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE;
reg = mac_idx == RTW89_MAC_0 ?
@ -2313,6 +2362,8 @@ static int preload_init_set_ax(struct rtw89_dev *rtwdev, u8 mac_idx,
rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND);
rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2392,11 +2443,15 @@ static int sta_sch_init_ax(struct rtw89_dev *rtwdev)
return ret;
}
rtw89_io_pack(rtwdev);
rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);
rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN);
_patch_ss2f_path(rtwdev);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2408,12 +2463,16 @@ static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,
B_AX_APPEND_FCS | B_AX_A_ICV_ERR);
rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2427,6 +2486,8 @@ static int sec_eng_init_ax(struct rtw89_dev *rtwdev)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
/* init clock */
val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP);
@ -2452,6 +2513,8 @@ static int sec_eng_init_ax(struct rtw89_dev *rtwdev)
rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,
B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2535,6 +2598,8 @@ static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx);
if (rtwdev->chip->chip_id == RTL8852C)
rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
@ -2563,6 +2628,8 @@ static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
SCH_PREBKF_24US);
}
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2631,6 +2698,8 @@ static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
for (i = RTW89_MGNT; i <= RTW89_DATA; i++) {
ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST,
mac_idx);
@ -2647,6 +2716,8 @@ static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx),
plcp_ftlr);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2693,6 +2764,8 @@ static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx);
val = rtw89_read32(rtwdev, reg);
val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA |
@ -2713,16 +2786,22 @@ static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
_patch_dis_resp_chk(rtwdev, mac_idx);
rtw89_io_unpack(rtwdev);
return 0;
}
static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev)
{
rtw89_io_pack(rtwdev);
rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |
B_AX_WMAC_TF_UP_NAV_EN |
B_AX_WMAC_NAV_UPPER_EN);
rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2734,12 +2813,17 @@ static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
if (ret)
return ret;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx);
rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx);
rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2752,6 +2836,8 @@ static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx);
rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);
@ -2762,6 +2848,8 @@ static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);
rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2776,6 +2864,8 @@ static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
val = rtw89_read32(rtwdev, reg);
val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK;
@ -2806,6 +2896,8 @@ static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);
rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2840,6 +2932,8 @@ static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
if (mac_idx == RTW89_MAC_0)
rst_bacam(rtwdev);
@ -2881,6 +2975,8 @@ static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx);
rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);
rtw89_io_unpack(rtwdev);
return ret;
}
@ -2932,6 +3028,8 @@ static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx);
val = rtw89_read32(rtwdev, reg);
@ -2969,6 +3067,8 @@ static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80);
}
rtw89_io_unpack(rtwdev);
return 0;
}
@ -4229,6 +4329,8 @@ int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb)
return ret;
}
rtw89_mac_fwdl_preconfig(rtwdev);
ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb);
if (ret)
return ret;
@ -5353,16 +5455,39 @@ rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
}
static void
rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)
{
/* N.B. This will run in interrupt context. */
const struct rtw89_c2h_rev_ack *c2h = (const void *)skb_c2h->data;
u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_REV_ACK_W2_CAT);
u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_REV_ACK_W2_CLASS);
u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_REV_ACK_W2_FUNC);
u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_REV_ACK_W2_H2C_SEQ);
struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
rtw89_debug(rtwdev, RTW89_DBG_FW,
"C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n",
RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data),
RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data),
RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data),
RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data));
h2c_cat, h2c_class, h2c_func, h2c_seq);
if (h2c_cat != H2C_CAT_MAC)
return;
switch (h2c_class) {
default:
return;
case H2C_CL_MAC_FW_OFLD:
switch (h2c_func) {
default:
return;
case H2C_FUNC_SCANOFLD:
case H2C_FUNC_SCANOFLD_BE:
scan_info->seq++;
break;
}
return;
}
}
static void
@ -5370,7 +5495,6 @@ rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 le
{
/* N.B. This will run in interrupt context. */
struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait;
const struct rtw89_c2h_done_ack *c2h =
(const struct rtw89_c2h_done_ack *)skb_c2h->data;
@ -5413,11 +5537,9 @@ rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 le
h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN;
break;
case H2C_FUNC_SCANOFLD:
scan_info->seq++;
cond = RTW89_SCANOFLD_WAIT_COND_START;
break;
case H2C_FUNC_SCANOFLD_BE:
scan_info->seq++;
cond = RTW89_SCANOFLD_BE_WAIT_COND_START;
h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN;
break;
@ -7368,6 +7490,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
.reset_pwr_state = rtw89_mac_reset_pwr_state_ax,
.disable_cpu = rtw89_mac_disable_cpu_ax,
.fwdl_preconfig = NULL,
.fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax,
.fwdl_get_status = rtw89_fw_get_rdy_ax,
.fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax,

52
drivers/net/wireless/realtek/rtw89/mac.h
View File

@ -926,19 +926,27 @@ struct rtw89_mac_size_set {
const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c3;
const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c5;
const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c6;
const struct rtw89_dle_size wde_size0;
const struct rtw89_dle_size wde_size1;
const struct rtw89_dle_size wde_size0_v1;
const struct rtw89_dle_size wde_size3_v1;
const struct rtw89_dle_size wde_size4;
const struct rtw89_dle_size wde_size4_v1;
const struct rtw89_dle_size wde_size5_v1;
const struct rtw89_dle_size wde_size6;
const struct rtw89_dle_size wde_size7;
const struct rtw89_dle_size wde_size7_v1;
const struct rtw89_dle_size wde_size8_v1;
const struct rtw89_dle_size wde_size9;
const struct rtw89_dle_size wde_size16_v1;
const struct rtw89_dle_size wde_size17;
const struct rtw89_dle_size wde_size18;
const struct rtw89_dle_size wde_size18_v1;
const struct rtw89_dle_size wde_size19;
const struct rtw89_dle_size wde_size22_v1;
const struct rtw89_dle_size wde_size23;
const struct rtw89_dle_size wde_size30;
const struct rtw89_dle_size wde_size31;
@ -946,8 +954,11 @@ struct rtw89_mac_size_set {
const struct rtw89_dle_size ple_size1;
const struct rtw89_dle_size ple_size0_v1;
const struct rtw89_dle_size ple_size3_v1;
const struct rtw89_dle_size ple_size4_v1;
const struct rtw89_dle_size ple_size4;
const struct rtw89_dle_size ple_size6;
const struct rtw89_dle_size ple_size6_v1;
const struct rtw89_dle_size ple_size7_v1;
const struct rtw89_dle_size ple_size8;
const struct rtw89_dle_size ple_size9;
const struct rtw89_dle_size ple_size17;
@ -956,6 +967,7 @@ struct rtw89_mac_size_set {
const struct rtw89_dle_size ple_size20_v1;
const struct rtw89_dle_size ple_size22_v1;
const struct rtw89_dle_size ple_size27;
const struct rtw89_dle_size ple_size29_v1;
const struct rtw89_dle_size ple_size31;
const struct rtw89_dle_size ple_size34;
const struct rtw89_wde_quota wde_qt0;
@ -963,13 +975,18 @@ struct rtw89_mac_size_set {
const struct rtw89_wde_quota wde_qt0_v1;
const struct rtw89_wde_quota wde_qt3;
const struct rtw89_wde_quota wde_qt4;
const struct rtw89_wde_quota wde_qt4_v1;
const struct rtw89_wde_quota wde_qt5_v1;
const struct rtw89_wde_quota wde_qt6;
const struct rtw89_wde_quota wde_qt7;
const struct rtw89_wde_quota wde_qt7_v1;
const struct rtw89_wde_quota wde_qt8_v1;
const struct rtw89_wde_quota wde_qt16;
const struct rtw89_wde_quota wde_qt17;
const struct rtw89_wde_quota wde_qt18;
const struct rtw89_wde_quota wde_qt19_v1;
const struct rtw89_wde_quota wde_qt23;
const struct rtw89_wde_quota wde_qt23_v1;
const struct rtw89_wde_quota wde_qt30;
const struct rtw89_wde_quota wde_qt31;
const struct rtw89_ple_quota ple_qt0;
@ -977,26 +994,37 @@ struct rtw89_mac_size_set {
const struct rtw89_ple_quota ple_qt4;
const struct rtw89_ple_quota ple_qt5;
const struct rtw89_ple_quota ple_qt5_v2;
const struct rtw89_ple_quota ple_qt6_v1;
const struct rtw89_ple_quota ple_qt7_v1;
const struct rtw89_ple_quota ple_qt8_v1;
const struct rtw89_ple_quota ple_qt9;
const struct rtw89_ple_quota ple_qt9_v1;
const struct rtw89_ple_quota ple_qt12_v1;
const struct rtw89_ple_quota ple_qt13;
const struct rtw89_ple_quota ple_qt13_v1;
const struct rtw89_ple_quota ple_qt14_v1;
const struct rtw89_ple_quota ple_qt15_v1;
const struct rtw89_ple_quota ple_qt18;
const struct rtw89_ple_quota ple_qt25;
const struct rtw89_ple_quota ple_qt26;
const struct rtw89_ple_quota ple_qt27;
const struct rtw89_ple_quota ple_qt28;
const struct rtw89_ple_quota ple_qt42;
const struct rtw89_ple_quota ple_qt42_v2;
const struct rtw89_ple_quota ple_qt43;
const struct rtw89_ple_quota ple_qt43_v2;
const struct rtw89_ple_quota ple_qt44;
const struct rtw89_ple_quota ple_qt44_v2;
const struct rtw89_ple_quota ple_qt45;
const struct rtw89_ple_quota ple_qt45_v2;
const struct rtw89_ple_quota ple_qt46;
const struct rtw89_ple_quota ple_qt47;
const struct rtw89_ple_quota ple_qt47_v2;
const struct rtw89_ple_quota ple_qt57;
const struct rtw89_ple_quota ple_qt58;
const struct rtw89_ple_quota ple_qt59;
const struct rtw89_ple_quota ple_qt61;
const struct rtw89_ple_quota ple_qt62;
const struct rtw89_ple_quota ple_qt64_v2;
const struct rtw89_ple_quota ple_qt65_v2;
const struct rtw89_ple_quota ple_qt78;
const struct rtw89_ple_quota ple_qt79;
const struct rtw89_ple_quota ple_qt_52a_wow;
@ -1006,13 +1034,19 @@ struct rtw89_mac_size_set {
const struct rtw89_rsvd_quota ple_rsvd_qt0;
const struct rtw89_rsvd_quota ple_rsvd_qt1;
const struct rtw89_rsvd_quota ple_rsvd_qt1_v1;
const struct rtw89_rsvd_quota ple_rsvd_qt2;
const struct rtw89_rsvd_quota ple_rsvd_qt9;
const struct rtw89_dle_rsvd_size rsvd0_size0;
const struct rtw89_dle_rsvd_size rsvd0_size3;
const struct rtw89_dle_rsvd_size rsvd0_size5;
const struct rtw89_dle_rsvd_size rsvd0_size6;
const struct rtw89_dle_rsvd_size rsvd0_size17;
const struct rtw89_dle_rsvd_size rsvd1_size0;
const struct rtw89_dle_rsvd_size rsvd1_size2;
const struct rtw89_dle_rsvd_size rsvd1_size3;
const struct rtw89_dle_input dle_input3;
const struct rtw89_dle_input dle_input18;
const struct rtw89_dle_input dle_input20;
const struct rtw89_dle_input dle_input28;
};
extern const struct rtw89_mac_size_set rtw89_mac_size;
@ -1087,6 +1121,7 @@ struct rtw89_mac_gen_def {
int (*reset_pwr_state)(struct rtw89_dev *rtwdev);
void (*disable_cpu)(struct rtw89_dev *rtwdev);
void (*fwdl_preconfig)(struct rtw89_dev *rtwdev);
int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
bool dlfw, bool include_bb);
u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
@ -1700,6 +1735,17 @@ static inline int rtw89_mac_efuse_read_ecv(struct rtw89_dev *rtwdev)
return mac->efuse_read_ecv(rtwdev);
}
static inline
void rtw89_mac_fwdl_preconfig(struct rtw89_dev *rtwdev)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
if (!mac->fwdl_preconfig)
return;
mac->fwdl_preconfig(rtwdev);
}
static inline
void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode)
{

29
drivers/net/wireless/realtek/rtw89/mac80211.c
View File

@ -98,6 +98,9 @@ static int rtw89_ops_config(struct ieee80211_hw *hw, int radio_idx, u32 changed)
!rtwdev->scanning)
rtw89_enter_ips(rtwdev);
if (changed & IEEE80211_CONF_CHANGE_MONITOR)
rtw89_physts_parsing_init(rtwdev);
return 0;
}
@ -356,6 +359,11 @@ static void rtw89_ops_configure_filter(struct ieee80211_hw *hw,
}
}
if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)
rtwdev->hal.rx_fltr |= B_AX_SNIFFER_MODE;
else
rtwdev->hal.rx_fltr &= ~B_AX_SNIFFER_MODE;
rx_fltr = rtwdev->hal.rx_fltr;
/* mac80211 doesn't configure filter when HW scan, driver need to
@ -721,14 +729,21 @@ static void rtw89_ops_vif_cfg_changed(struct ieee80211_hw *hw,
if (changed & BSS_CHANGED_MLD_VALID_LINKS) {
struct rtw89_vif_link *cur = rtw89_get_designated_link(rtwvif);
u16 mac_id;
if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw))
rtw89_chip_rfk_channel(rtwdev, cur);
if (hweight16(vif->active_links) == 1)
if (hweight16(vif->active_links) == 1) {
mac_id = cur->mac_id;
rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
else
} else {
/* Specify for all MAC ID */
mac_id = 0xffff;
rtwvif->mlo_mode = RTW89_MLO_MODE_EMLSR;
}
rtw89_fw_h2c_tx_history(rtwdev, mac_id);
}
}
@ -964,7 +979,8 @@ static int rtw89_ops_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
rtw89_err(rtwdev, "failed to add key to sec cam\n");
return ret;
}
rtw89_core_tid_rx_stats_reset(rtwdev);
if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
rtw89_core_tid_rx_stats_reset(rtwdev);
break;
case DISABLE_KEY:
flush_work(&rtwdev->txq_work);
@ -1241,6 +1257,7 @@ static int rtw89_ops_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct rtw89_dev *rtwdev = hw->priv;
struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
struct rtw89_vif_link *rtwvif_link;
struct rtw89_hal *hal = &rtwdev->hal;
int ret;
lockdep_assert_wiphy(hw->wiphy);
@ -1248,6 +1265,12 @@ static int rtw89_ops_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
if (!RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw))
return 1;
if (hal->disabled_dm_bitmap & BIT(RTW89_DM_HW_SCAN)) {
rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
"reject hw scan due to disabled_dm\n");
return -EBUSY;
}
if (rtwdev->scanning || rtwvif->offchan)
return -EBUSY;

68
drivers/net/wireless/realtek/rtw89/mac_be.c
View File

@ -622,6 +622,12 @@ static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev)
rtw89_write32(rtwdev, R_BE_UDM2, 0);
}
static void rtw89_mac_fwdl_preconfig_be(struct rtw89_dev *rtwdev)
{
rtw89_write32_clr(rtwdev, R_BE_FW_AUTO_CAL_DELAY, B_BE_WCPU_FW_DELAY_COUNT_VALID);
rtw89_write32_mask(rtwdev, R_BE_FW_AUTO_CAL_DELAY, B_BE_WCPU_FW_DELAY_COUNT_MASK, 0);
}
static void set_cpu_en(struct rtw89_dev *rtwdev, bool include_bb)
{
u32 set = B_BE_WLANCPU_FWDL_EN;
@ -1000,6 +1006,8 @@ static int mpdu_proc_init_be(struct rtw89_dev *rtwdev)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
rtw89_write32_set(rtwdev, R_BE_MPDU_PROC, B_BE_APPEND_FCS);
rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL |
B_BE_CA_CHK_ADDRCAM_EN);
@ -1019,6 +1027,8 @@ static int mpdu_proc_init_be(struct rtw89_dev *rtwdev)
val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_1_MASK);
rtw89_write32(rtwdev, R_BE_DISP_FWD_WLAN_0, val32);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1031,6 +1041,8 @@ static int sec_eng_init_be(struct rtw89_dev *rtwdev)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
val32 = rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL);
val32 |= B_BE_CLK_EN_CGCMP | B_BE_CLK_EN_WAPI | B_BE_CLK_EN_WEP_TKIP |
B_BE_SEC_TX_ENC | B_BE_SEC_RX_DEC |
@ -1041,6 +1053,8 @@ static int sec_eng_init_be(struct rtw89_dev *rtwdev)
rtw89_write32_set(rtwdev, R_BE_SEC_MPDU_PROC, B_BE_APPEND_ICV | B_BE_APPEND_MIC);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1083,13 +1097,16 @@ static int mlo_init_be(struct rtw89_dev *rtwdev)
u32 reg;
int ret;
val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL);
rtw89_io_pack(rtwdev);
val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL);
val32 |= B_BE_MLO_TABLE_REINIT;
rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
val32 &= ~B_BE_MLO_TABLE_REINIT;
rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
rtw89_io_unpack(rtwdev);
ret = read_poll_timeout_atomic(rtw89_read32, val32,
val32 & B_BE_MLO_TABLE_INIT_DONE,
1, 1000, false, rtwdev, R_BE_MLO_INIT_CTL);
@ -1101,9 +1118,13 @@ static int mlo_init_be(struct rtw89_dev *rtwdev)
else
reg = R_BE_SS_CTRL_V1;
rtw89_io_pack(rtwdev);
rtw89_write32_set(rtwdev, reg, B_BE_MLO_HW_CHGLINK_EN);
rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_ACQCHK_CFG_0, B_BE_R_MACID_ACQ_CHK_EN);
rtw89_io_unpack(rtwdev);
return ret;
}
@ -1173,6 +1194,8 @@ static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
if (chip->chip_id == RTL8922D) {
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SCH_EXT_CTRL, mac_idx);
rtw89_write32_set(rtwdev, reg, B_BE_CWCNT_PLUS_MODE);
@ -1216,6 +1239,8 @@ static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
rtw89_write32_set(rtwdev, reg, B_BE_TX_NAV_RST_EDCA_EN);
}
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1292,6 +1317,8 @@ static int rx_fltr_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
u32 reg;
u32 val;
rtw89_io_pack(rtwdev);
rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_MGNT, RTW89_FWD_TO_HOST, mac_idx);
rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_CTRL, RTW89_FWD_TO_HOST, mac_idx);
rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_DATA, RTW89_FWD_TO_HOST, mac_idx);
@ -1309,6 +1336,8 @@ static int rx_fltr_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
B_BE_LSIG_PARITY_CHK_EN | B_BE_CCK_SIG_CHK | B_BE_CCK_CRC_CHK;
rtw89_write16(rtwdev, reg, val);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1322,6 +1351,8 @@ static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
u32 val32;
u32 reg;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_NAV_CTL, mac_idx);
val32 = rtw89_read32(rtwdev, reg);
@ -1337,6 +1368,8 @@ static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx);
rtw89_write32_set(rtwdev, reg, B_BE_WMAC_MBA_DUR_FORCE);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1349,12 +1382,16 @@ static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx);
rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSSID_SRC_CTRL, mac_idx);
rtw89_write8_set(rtwdev, reg, B_BE_PLCP_SRC_EN);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1364,6 +1401,8 @@ static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
struct rtw89_hal *hal = &rtwdev->hal;
u32 reg;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx);
rtw89_write32_clr(rtwdev, reg, B_BE_QOSNULL_UPD_MUEDCA_EN);
@ -1378,6 +1417,8 @@ static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
rtw89_write32_clr(rtwdev, reg, CLEAR_DTOP_DIS);
}
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1394,6 +1435,8 @@ static int trxptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MAC_LOOPBACK, mac_idx);
val32 = rtw89_read32(rtwdev, reg);
val32 = u32_replace_bits(val32, S_BE_MACLBK_PLCP_DLY_DEF,
@ -1453,6 +1496,8 @@ static int trxptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1);
}
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1495,6 +1540,8 @@ static int rmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
return ret;
}
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DLK_PROTECT_CTL, mac_idx);
val16 = rtw89_read16(rtwdev, reg);
val16 = u16_replace_bits(val16, TRXCFG_RMAC_DATA_TO, B_BE_RX_DLK_DATA_TIME_MASK);
@ -1534,6 +1581,8 @@ static int rmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
rtw89_write32_set(rtwdev, reg, B_BE_DIS_CHK_MIN_LEN);
}
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1555,10 +1604,14 @@ static int resp_pktctl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
return ret;
}
rtw89_io_pack(rtwdev);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RESP_CSI_RESERVED_PAGE, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_START_PAGE_MASK, qt_cfg.pktid);
rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num + 1);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1602,6 +1655,8 @@ static int ptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
rtw89_io_pack(rtwdev);
if (is_qta_poh(rtwdev)) {
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SIFS_SETTING, mac_idx);
val32 = rtw89_read32(rtwdev, reg);
@ -1671,6 +1726,8 @@ static int ptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
B_BE_PRELD_HIQ_P0_EN);
}
rtw89_io_unpack(rtwdev);
return 0;
}
@ -1965,6 +2022,8 @@ static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx,
if (!(chip->chip_id == RTL8922A || rtw89_mac_chk_preload_allow(rtwdev)))
return 0;
rtw89_io_pack(rtwdev);
max_preld_size = mac_idx == RTW89_MAC_0 ?
PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM;
if (chip->chip_id == RTL8922D)
@ -1997,6 +2056,8 @@ static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx,
val32 |= B_BE_B0_PRELD_FEN;
rtw89_write32(rtwdev, reg, val32);
rtw89_io_unpack(rtwdev);
return 0;
}
@ -2750,6 +2811,10 @@ static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev,
sound_dim = min(sound_dim, t);
}
/* Disable stbc_en in VHT 160MHz to avoid IOT issues with certain APs */
if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ)
stbc_en = 0;
nc = min(nc, sound_dim);
nr = min(nr, sound_dim);
@ -3229,6 +3294,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
.reset_pwr_state = rtw89_mac_reset_pwr_state_be,
.disable_cpu = rtw89_mac_disable_cpu_be,
.fwdl_preconfig = rtw89_mac_fwdl_preconfig_be,
.fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,
.fwdl_get_status = fwdl_get_status_be,
.fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be,

41
drivers/net/wireless/realtek/rtw89/pci.c
View File

@ -3039,6 +3039,17 @@ static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev)
return 0;
}
static bool rtw89_pci_dev_ltr_enabled(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct pci_dev *pdev = rtwpci->pdev;
u16 cap;
pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap);
return !!(cap & PCI_EXP_DEVCTL2_LTR_EN);
}
static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
@ -3143,7 +3154,7 @@ int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en)
{
u32 val;
if (!en)
if (!en || !rtw89_pci_dev_ltr_enabled(rtwdev))
return 0;
val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0);
@ -3179,6 +3190,9 @@ int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en)
u32 dec_ctrl;
u32 val32;
if (!rtw89_pci_dev_ltr_enabled(rtwdev))
return 0;
val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0);
if (rtw89_pci_ltr_is_err_reg_val(val32))
return -EINVAL;
@ -4366,10 +4380,20 @@ static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev)
static void rtw89_pci_cpl_timeout_cfg(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
struct rtw89_hal *hal = &rtwdev->hal;
struct pci_dev *pdev = rtwpci->pdev;
bool dis = true;
pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
PCI_EXP_DEVCTL2_COMP_TMOUT_DIS);
if (chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)
dis = false;
if (dis)
pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
PCI_EXP_DEVCTL2_COMP_TMOUT_DIS);
else
pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
PCI_EXP_DEVCTL2_COMP_TMOUT_DIS);
}
static int rtw89_pci_poll_io_idle_ax(struct rtw89_dev *rtwdev)
@ -4624,9 +4648,9 @@ EXPORT_SYMBOL(rtw89_pm_ops);
static pci_ers_result_t rtw89_pci_io_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
netif_device_detach(netdev);
ieee80211_stop_queues(hw);
return PCI_ERS_RESULT_NEED_RESET;
}
@ -4643,12 +4667,12 @@ static pci_ers_result_t rtw89_pci_io_slot_reset(struct pci_dev *pdev)
static void rtw89_pci_io_resume(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
/* ack any pending wake events, disable PME */
pci_enable_wake(pdev, PCI_D0, 0);
netif_device_attach(netdev);
ieee80211_wake_queues(hw);
}
const struct pci_error_handlers rtw89_pci_err_handler = {
@ -4748,8 +4772,7 @@ int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
info = (const struct rtw89_driver_info *)id->driver_data;
rtwdev = rtw89_alloc_ieee80211_hw(&pdev->dev,
sizeof(struct rtw89_pci),
info->chip, info->variant);
sizeof(struct rtw89_pci), info);
if (!rtwdev) {
dev_err(&pdev->dev, "failed to allocate hw\n");
return -ENOMEM;

6
drivers/net/wireless/realtek/rtw89/pci.h
View File

@ -33,6 +33,8 @@
#define RAC_REG_REV2 0x1B
#define BAC_CMU_EN_DLY_MASK GENMASK(15, 12)
#define PCIE_DPHY_DLY_25US 0x1
#define RAC_ANA14 0x14
#define EIEOS_L1SS_WAIT_CLKRDY BIT(2)
#define RAC_ANA19 0x19
#define B_PCIE_BIT_RD_SEL BIT(2)
#define RAC_REG_FLD_0 0x1D
@ -56,7 +58,7 @@
#define B_AX_DIV GENMASK(15, 14)
#define RAC_SET_PPR_V1 0x31
#define RAC_ANA40 0x40
#define PHY_ERR_IMR_DIS (BIT(9) | BIT(0))
#define PHY_ERR_IMR_DIS (BIT(9) | BIT(8) | BIT(0))
#define RAC_ANA41 0x41
#define PHY_ERR_FLAG_EN BIT(6)
@ -961,6 +963,8 @@
#define R_BE_PCIE_HRPWM 0x30C0
#define R_BE_PCIE_CRPWM 0x30C4
#define R_BE_PCIE_HCI2FW_ISR 0x30CC
#define R_BE_L1_2_CTRL_HCILDO 0x3110
#define B_BE_PM_CLKREQ_EXT_RB BIT(11)
#define B_BE_PCIE_DIS_RTK_PRST_N_L1_2 BIT(10)

15
drivers/net/wireless/realtek/rtw89/pci_be.c
View File

@ -83,6 +83,17 @@ static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up)
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1);
}
static void _patch_pre_init_be(struct rtw89_dev *rtwdev)
{
struct rtw89_hal *hal = &rtwdev->hal;
if (!(rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090))
return;
rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
RAC_ANA14 * RAC_MULT, EIEOS_L1SS_WAIT_CLKRDY);
}
static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
@ -336,6 +347,7 @@ static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev)
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_SYM_PRST_CPHY_RST);
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_USUS_OFFCAPC_EN);
rtw89_write32(rtwdev, R_BE_PCIE_HCI2FW_ISR, 0xFFFFFFFF);
}
static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
@ -475,6 +487,7 @@ static int rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev *rtwdev)
rtw89_pci_set_io_rcy_be(rtwdev);
_patch_pcie_power_wake_be(rtwdev, true);
_patch_pre_init_be(rtwdev);
rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, false);
rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE);
@ -831,6 +844,8 @@ static int __maybe_unused rtw89_pci_resume_be(struct device *dev)
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
}
rtw89_write32(rtwdev, R_BE_PCIE_HCI2FW_ISR, 0xFFFFFFFF);
}
rtw89_pci_basic_cfg(rtwdev, true);

622
drivers/net/wireless/realtek/rtw89/phy.c
View File

@ -1352,17 +1352,17 @@ static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
u32 addr;
if (reg->addr == 0xfe) {
mdelay(50);
rtw89_io_mdelay(rtwdev, 50);
} else if (reg->addr == 0xfd) {
mdelay(5);
rtw89_io_mdelay(rtwdev, 5);
} else if (reg->addr == 0xfc) {
mdelay(1);
rtw89_io_mdelay(rtwdev, 1);
} else if (reg->addr == 0xfb) {
udelay(50);
rtw89_io_udelay(rtwdev, 50);
} else if (reg->addr == 0xfa) {
udelay(5);
rtw89_io_udelay(rtwdev, 5);
} else if (reg->addr == 0xf9) {
udelay(1);
rtw89_io_udelay(rtwdev, 1);
} else if (reg->data == BYPASS_CR_DATA) {
rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
} else {
@ -1692,17 +1692,17 @@ void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
void *extra_data)
{
if (reg->addr == 0xfe) {
mdelay(50);
rtw89_io_mdelay(rtwdev, 50);
} else if (reg->addr == 0xfd) {
mdelay(5);
rtw89_io_mdelay(rtwdev, 5);
} else if (reg->addr == 0xfc) {
mdelay(1);
rtw89_io_mdelay(rtwdev, 1);
} else if (reg->addr == 0xfb) {
udelay(50);
rtw89_io_udelay(rtwdev, 50);
} else if (reg->addr == 0xfa) {
udelay(5);
rtw89_io_udelay(rtwdev, 5);
} else if (reg->addr == 0xf9) {
udelay(1);
rtw89_io_udelay(rtwdev, 1);
} else {
rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
@ -1715,6 +1715,11 @@ void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
enum rtw89_rf_path rf_path,
void *extra_data)
{
if (reg->addr == 0xfe) {
rtw89_io_mdelay(rtwdev, 50);
return;
}
rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
if (reg->addr < 0x100)
@ -1885,11 +1890,16 @@ void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
const struct rtw89_phy_table *bb_gain_table;
bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
rtw89_io_pack(rtwdev);
rtw89_phy_init_reg(rtwdev, bb_table, false, rtw89_phy_config_bb_reg, NULL);
if (rtwdev->dbcc_en)
rtw89_phy_init_reg(rtwdev, bb_table, false, rtw89_phy_config_bb_reg,
(void *)RTW89_PHY_1);
rtw89_io_unpack(rtwdev);
rtw89_chip_init_txpwr_unit(rtwdev);
bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
@ -2016,7 +2026,11 @@ void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
else
config = rf_table->config ? rf_table->config :
rtw89_phy_config_rf_reg;
rtw89_io_pack(rtwdev);
rtw89_phy_init_reg(rtwdev, rf_table, by_acv, config, (void *)rf_reg_info);
rtw89_io_unpack(rtwdev);
if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
rf_reg_info->rf_path);
@ -3225,6 +3239,7 @@ static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
u8 mode, rate, bw, giltf, mac_id;
u16 legacy_bitrate, amsdu_len;
u8 retry_ratio = 0;
bool valid;
u8 mcs = 0;
u8 t;
@ -3245,6 +3260,7 @@ static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
bw |= u8_encode_bits(t, BIT(2));
t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
mode |= u8_encode_bits(t, BIT(2));
retry_ratio = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_RETRY_RATIO);
}
if (mode == RTW89_RA_RPT_MODE_LEGACY) {
@ -3320,6 +3336,7 @@ static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) :
u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
ra_report->retry_ratio = retry_ratio;
ra_report->might_fallback_legacy = mcs <= 2;
amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
@ -3365,12 +3382,24 @@ rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
&ra_data);
}
static void
rtw89_phy_c2h_tx_history(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
{
const struct rtw89_c2h_ra_tx_history *history = (const void *)c2h->data;
u32 *tx_rate_cnt = rtwdev->phystat.tx_rate_cnt;
u32 i;
for (i = 0; i < RTW89_TX_RATE_NR; i++)
tx_rate_cnt[i] = le32_to_cpu(history->tx_rate_tot_cnt_hist[i]);
}
static
void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
struct sk_buff *c2h, u32 len) = {
[RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
[RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
[RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
[RTW89_PHY_C2H_FUNC_TX_HISTORY] = rtw89_phy_c2h_tx_history,
[RTW89_PHY_C2H_FUNC_ACCELERATE_EN] = rtw89_fw_c2h_dummy_handler,
};
@ -3956,6 +3985,14 @@ int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name,
struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
unsigned long time_left;
/*
* USB transport adds latency to H2C/C2H round-trips, so RF
* calibrations take longer than on PCIe. Apply a 4x multiplier
* to avoid spurious timeouts.
*/
if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
ms *= 4;
/* Since we can't receive C2H event during SER, use a fixed delay. */
if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
fsleep(1000 * ms / 2);
@ -5792,6 +5829,7 @@ static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
{
struct rtw89_phy_stat *phystat = &rtwdev->phystat;
struct rtw89_bb_ctx *bb;
int i;
for (i = 0; i < rtwdev->chip->rf_path_num; i++)
@ -5799,24 +5837,360 @@ static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
rtw89_phy_stat_thermal_update(rtwdev);
memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
rtw89_for_each_capab_bb(rtwdev, bb) {
memset(&bb->cur_pkt_stat, 0, sizeof(bb->cur_pkt_stat));
memset(&bb->last_pkt_stat, 0, sizeof(bb->last_pkt_stat));
ewma_rssi_init(&phystat->bcn_rssi);
ewma_rssi_init(&bb->bcn_rssi);
}
rtwdev->hal.thermal_prot_lv = 0;
}
static void rtw89_phy_pmac_diag(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
{
#define RTW89_DIAG_BB_FA_RATIO_TH 80
#define RTW89_DIAG_BB_NO_RX_TH 5
#define RTW89_DIAG_BB_HANG_TH 30
struct rtw89_pmac_stat_info *pmac_stat = &bb->pmac_stat;
bool is_linked = rtwdev->total_sta_assoc > 0;
struct rtw89_diag_bb *diag = &bb->diag;
u8 fa_ratio = 0;
if (!(pmac_stat->cck_mac_txen || pmac_stat->ofdm_mac_txen))
diag->consecutive_no_tx_cnt++;
else
diag->consecutive_no_tx_cnt = 0;
if (!pmac_stat->cnt_cca_all)
diag->consecutive_no_rx_cnt++;
else
diag->consecutive_no_rx_cnt = 0;
if (pmac_stat->cnt_cca_all)
fa_ratio = pmac_stat->cnt_fail_all * PERCENT / pmac_stat->cnt_cca_all;
diag->diag_bb_bitmap &= ~(BIT(RTW89_DIAG_BB_NO_RX) |
BIT(RTW89_DIAG_BB_HANG) |
BIT(RTW89_DIAG_BB_FA));
if (diag->consecutive_no_rx_cnt >= RTW89_DIAG_BB_NO_RX_TH && is_linked) {
diag->diag_bb_bitmap |= BIT(RTW89_DIAG_BB_NO_RX);
diag->diag_bb_cnt[RTW89_DIAG_BB_NO_RX]++;
}
if (fa_ratio >= RTW89_DIAG_BB_FA_RATIO_TH && is_linked) {
diag->diag_bb_bitmap |= BIT(RTW89_DIAG_BB_FA);
diag->diag_bb_cnt[RTW89_DIAG_BB_FA]++;
}
if (diag->consecutive_no_tx_cnt > RTW89_DIAG_BB_HANG_TH &&
diag->consecutive_no_rx_cnt > RTW89_DIAG_BB_HANG_TH) {
diag->diag_bb_bitmap |= BIT(RTW89_DIAG_BB_HANG);
diag->diag_bb_cnt[RTW89_DIAG_BB_HANG]++;
}
}
static void rtw89_phy_pmac_stat_reset(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb, bool cck)
{
const struct rtw89_pmac_regs *regs = rtwdev->chip->pmac_regs;
if (cck) {
rtw89_phy_write32_clr(rtwdev, regs->r1b_rx_rpt_rst.addr,
regs->r1b_rx_rpt_rst.mask);
rtw89_phy_write32_set(rtwdev, regs->r1b_rx_rpt_rst.addr,
regs->r1b_rx_rpt_rst.mask);
}
rtw89_phy_write32_idx_set(rtwdev, regs->enable_all_cnt.addr,
regs->enable_all_cnt.mask, bb->phy_idx);
rtw89_phy_write32_idx_set(rtwdev, regs->rst_all_cnt.addr,
regs->rst_all_cnt.mask, bb->phy_idx);
rtw89_phy_write32_idx_clr(rtwdev, regs->rst_all_cnt.addr,
regs->rst_all_cnt.mask, bb->phy_idx);
}
static void rtw89_phy_pmac_stat_cck(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb)
{
const struct rtw89_pmac_regs *regs = rtwdev->chip->pmac_regs;
struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat;
const struct rtw89_chip_info *chip = rtwdev->chip;
u32 val;
pmac->cck_phy_txon =
rtw89_phy_read32_mask(rtwdev, regs->cck_txon.addr, regs->cck_txon.mask);
pmac->cck_mac_txen =
rtw89_phy_read32_mask(rtwdev, regs->cck_txen.addr, regs->cck_txen.mask);
if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
rtw89_phy_write32_mask(rtwdev, regs->r1b_rr_sel.addr,
regs->r1b_rr_sel.mask, 0x2);
if (bb->phy_idx == RTW89_PHY_1)
pmac->cnt_cck_cca =
rtw89_phy_read32_mask(rtwdev, regs->cck_cca.addr + 8,
regs->cck_cca.mask);
else
pmac->cnt_cck_cca =
rtw89_phy_read32_mask(rtwdev, regs->cck_cca.addr,
regs->cck_cca.mask);
if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
rtw89_phy_write32_mask(rtwdev, regs->r1b_rr_sel.addr,
regs->r1b_rr_sel.mask, 0x1);
if (bb->phy_idx == RTW89_PHY_1)
val = rtw89_phy_read32(rtwdev, regs->cck_crc32 + 8);
else
val = rtw89_phy_read32(rtwdev, regs->cck_crc32);
pmac->cnt_cck_crc32_ok = field_get(regs->cck_crc32_ok_mask, val);
pmac->cnt_cck_crc32_error = field_get(regs->cck_crc32_fail_mask, val);
pmac->cnt_sfd_gg =
rtw89_phy_read32_idx(rtwdev, regs->cck_sfd_gg.addr,
regs->cck_sfd_gg.mask, bb->phy_idx);
pmac->cnt_sig_gg =
rtw89_phy_read32_idx(rtwdev, regs->cck_sig_gg.addr,
regs->cck_sig_gg.mask, bb->phy_idx);
pmac->cnt_cck_spoofing =
rtw89_phy_read32_idx(rtwdev, regs->cck_spoofing.addr,
regs->cck_spoofing.mask, bb->phy_idx);
if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
pmac->cnt_cck_fail =
pmac->cnt_cck_cca - pmac->cnt_cck_crc32_ok -
pmac->cnt_cck_crc32_error - pmac->cnt_cck_spoofing;
else
pmac->cnt_cck_fail =
rtw89_phy_read32_idx(rtwdev, regs->cck_brk.addr,
regs->cck_brk.mask, bb->phy_idx);
}
static void rtw89_phy_pmac_stat_ofdm(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb)
{
const struct rtw89_pmac_regs *regs = rtwdev->chip->pmac_regs;
struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat;
const struct rtw89_chip_info *chip = rtwdev->chip;
u32 val;
val = rtw89_phy_read32_idx(rtwdev, regs->ofdm_txon, MASKDWORD, bb->phy_idx);
pmac->ofdm_phy_txon = field_get(regs->ofdm_txon_mask, val);
pmac->ofdm_mac_txen = field_get(regs->ofdm_txen_mask, val);
val = rtw89_phy_read32_idx(rtwdev, regs->l_crc, MASKDWORD, bb->phy_idx);
pmac->cnt_ofdm_crc32_ok = field_get(regs->l_crc_ok_mask, val);
pmac->cnt_ofdm_crc32_error = field_get(regs->l_crc_err_mask, val);
val = rtw89_phy_read32_idx(rtwdev, regs->ht_crc, MASKDWORD, bb->phy_idx);
pmac->cnt_ht_crc32_ok = field_get(regs->ht_crc_ok_mask, val);
pmac->cnt_ht_crc32_error = field_get(regs->ht_crc_err_mask, val);
val = rtw89_phy_read32_idx(rtwdev, regs->vht_crc, MASKDWORD, bb->phy_idx);
pmac->cnt_vht_crc32_ok = field_get(regs->vht_crc_ok_mask, val);
pmac->cnt_vht_crc32_error = field_get(regs->vht_crc_err_mask, val);
val = rtw89_phy_read32_idx(rtwdev, regs->he_crc, MASKDWORD, bb->phy_idx);
pmac->cnt_he_crc32_ok = field_get(regs->he_crc_ok_mask, val);
pmac->cnt_he_crc32_error = field_get(regs->he_crc_err_mask, val);
if (chip->chip_gen == RTW89_CHIP_BE) {
val = rtw89_phy_read32_idx(rtwdev, regs->eht_crc,
MASKDWORD, bb->phy_idx);
pmac->cnt_eht_crc32_ok = field_get(regs->eht_crc_ok_mask, val);
pmac->cnt_eht_crc32_error = field_get(regs->eht_crc_err_mask, val);
}
val = rtw89_phy_read32_idx(rtwdev, regs->ampdu_crc, MASKDWORD, bb->phy_idx);
pmac->cnt_ampdu_crc_ok = field_get(regs->ampdu_crc_ok_mask, val);
pmac->cnt_ampdu_crc_error = field_get(regs->ampdu_crc_err_mask, val);
val = rtw89_phy_read32_idx(rtwdev, regs->brk.addr, regs->brk.mask, bb->phy_idx);
if (chip->chip_id == RTL8852C &&
rtw89_phy_read32_idx(rtwdev, regs->brk_option.addr,
regs->brk_option.mask, bb->phy_idx) == 1) {
u32 tmp = pmac->ofdm_phy_txon + pmac->cck_phy_txon;
val = (val > tmp) ? (val - tmp) : 0;
}
pmac->cnt_ofdm_fail = val;
pmac->cnt_sb_search_fail =
rtw89_phy_read32_idx(rtwdev, regs->search_fail.addr,
regs->search_fail.mask, bb->phy_idx);
pmac->cnt_lsig_brk_s_th =
rtw89_phy_read32_idx(rtwdev, regs->lsig_brk_s_th.addr,
regs->lsig_brk_s_th.mask, bb->phy_idx);
pmac->cnt_lsig_brk_l_th =
rtw89_phy_read32_idx(rtwdev, regs->lsig_brk_l_th.addr,
regs->lsig_brk_l_th.mask, bb->phy_idx);
pmac->cnt_parity_fail =
rtw89_phy_read32_idx(rtwdev, regs->rxl_err_parity.addr,
regs->rxl_err_parity.mask, bb->phy_idx);
pmac->cnt_rate_illegal =
rtw89_phy_read32_idx(rtwdev, regs->rxl_err_rate.addr,
regs->rxl_err_rate.mask, bb->phy_idx);
pmac->cnt_ofdm_cca =
rtw89_phy_read32_idx(rtwdev, regs->ofdm_cca.addr,
regs->ofdm_cca.mask, bb->phy_idx);
pmac->cnt_ofdm_spoofing =
rtw89_phy_read32_idx(rtwdev, regs->cca_spoofing.addr,
regs->cca_spoofing.mask, bb->phy_idx);
pmac->cnt_ampdu_miss =
rtw89_phy_read32_idx(rtwdev, regs->ampdu_miss.addr,
regs->ampdu_miss.mask, bb->phy_idx);
}
static void rtw89_phy_pmac_stat_update(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb)
{
struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_entity_conf conf;
const struct rtw89_chan *chan;
bool cck;
rtw89_entity_get_conf(rtwdev, &conf);
chan = conf.chans[bb->phy_idx];
cck = chan->band_type == RTW89_BAND_2G;
if (cck)
rtw89_phy_pmac_stat_cck(rtwdev, bb);
rtw89_phy_pmac_stat_ofdm(rtwdev, bb);
pmac->cnt_fail_all = pmac->cnt_ofdm_fail;
pmac->cnt_cca_all = pmac->cnt_ofdm_cca;
if (cck) {
pmac->cnt_fail_all += pmac->cnt_cck_fail;
pmac->cnt_cca_all += pmac->cnt_cck_cca;
}
pmac->cnt_crc32_error_all = pmac->cnt_he_crc32_error +
pmac->cnt_vht_crc32_error +
pmac->cnt_ht_crc32_error +
pmac->cnt_ofdm_crc32_error +
pmac->cnt_cck_crc32_error;
pmac->cnt_crc32_ok_all = pmac->cnt_he_crc32_ok +
pmac->cnt_vht_crc32_ok +
pmac->cnt_ht_crc32_ok +
pmac->cnt_ofdm_crc32_ok +
pmac->cnt_cck_crc32_ok;
if (chip->chip_gen == RTW89_CHIP_BE) {
pmac->cnt_crc32_error_all += pmac->cnt_eht_crc32_error;
pmac->cnt_crc32_ok_all += pmac->cnt_eht_crc32_ok;
}
rtw89_phy_pmac_diag(rtwdev, bb);
rtw89_phy_pmac_stat_reset(rtwdev, bb, cck);
}
static void rtw89_phy_tx_stat_update(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
{
const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
const struct rtw89_physts_regs *physts = phy->physts;
struct rtw89_tx_stat_info *tx_stat = &bb->tx_stat;
const struct rtw89_chip_info *chip = rtwdev->chip;
u32 reg_nr;
u32 val;
u32 i;
if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF &&
bb->phy_idx != RTW89_PHY_0)
val = 1;
else
val = 0;
rtw89_phy_write32_mask(rtwdev, physts->mac_phy_intf_sel.addr,
physts->mac_phy_intf_sel.mask, val);
reg_nr = min(physts->tx_info.reg_nr, ARRAY_SIZE(tx_stat->info));
for (i = 0; i < reg_nr; i++)
tx_stat->info[i] = rtw89_phy_read32(rtwdev, physts->tx_info.regs[i]);
reg_nr = min(physts->tx_common_ctrl.reg_nr, ARRAY_SIZE(tx_stat->common_ctrl));
for (i = 0; i < reg_nr; i++)
tx_stat->common_ctrl[i] =
rtw89_phy_read32(rtwdev, physts->tx_common_ctrl.regs[i]);
reg_nr = min(chip->rf_path_num, ARRAY_SIZE(tx_stat->txpwr));
for (i = 0; i < reg_nr; i++)
tx_stat->txpwr[i] = rtw89_phy_read32_mask(rtwdev, physts->txpwr[i].addr,
physts->txpwr[i].mask);
tx_stat->type = u32_get_bits(tx_stat->info[0], TX_STATUS_TYPE);
if (chip->chip_gen == RTW89_CHIP_AX) {
tx_stat->tx_path_en = u32_get_bits(tx_stat->info[0], TX_STATUS_TX_PATH_EN);
tx_stat->path_map = u32_get_bits(tx_stat->info[0], TX_STATUS_PATH_MAP);
tx_stat->txcmd = u32_get_bits(tx_stat->info[0], TX_STATUS_TXCMD);
tx_stat->txsc = u32_get_bits(tx_stat->info[1], TX_STATUS_TXSC);
tx_stat->bw = u32_get_bits(tx_stat->info[1], TX_STATUS_BW);
tx_stat->tmac_txpwr = u32_get_bits(tx_stat->info[1], TX_STATUS_TMAC_TXPWR);
if (!(chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)))
tx_stat->max_mcs = u32_get_bits(tx_stat->info[3], TX_STATUS_MAX_MCS);
} else {
tx_stat->type = u32_get_bits(tx_stat->info[0], TX_STATUS_TYPE);
tx_stat->subtype = u32_get_bits(tx_stat->info[0], TX_STATUS_SUBTYPE);
if (chip->chip_id == RTL8922A)
tx_stat->txcmd = u32_get_bits(tx_stat->info[0], TX_STATUS_TXCMD_V1);
else
tx_stat->txcmd = u32_get_bits(tx_stat->info[0], TX_STATUS_TXCMD_V2);
tx_stat->txsc = u32_get_bits(tx_stat->info[0], TX_STATUS_TXSC_V1);
tx_stat->bw = u32_get_bits(tx_stat->info[1], TX_STATUS_BW_V1);
tx_stat->tmac_txpwr = u32_get_bits(tx_stat->info[1], TX_STATUS_TMAC_TXPWR_V1);
tx_stat->tx_path_en = u32_get_bits(tx_stat->info[2], TX_STATUS_TX_PATH_EN_V1);
tx_stat->path_map = u32_get_bits(tx_stat->info[2], TX_STATUS_PATH_MAP_V1);
tx_stat->max_mcs = u32_get_bits(tx_stat->info[4], TX_STATUS_MAX_MCS_V1);
}
tx_stat->stbc = !!(tx_stat->common_ctrl[0] & TX_STATUS_STBC);
}
static void rtw89_phy_trigger_tx_count(struct rtw89_dev *rtwdev)
{
if (RTW89_CHK_FW_FEATURE(TX_HISTORY_V1, &rtwdev->fw))
rtw89_fw_h2c_phy_ch_rpt(rtwdev);
else
rtw89_fw_h2c_drv_ctrl_fw(rtwdev);
}
static void rtw89_phy_stat_update(struct rtw89_dev *rtwdev)
{
struct rtw89_bb_ctx *bb;
if (!rtwdev->phy_info.bb_stat_cfg.enable)
return;
rtw89_phy_trigger_tx_count(rtwdev);
rtw89_for_each_active_bb(rtwdev, bb) {
rtw89_phy_pmac_stat_update(rtwdev, bb);
rtw89_phy_tx_stat_update(rtwdev, bb);
}
}
void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
{
struct rtw89_phy_stat *phystat = &rtwdev->phystat;
struct rtw89_bb_ctx *bb;
rtw89_phy_stat_thermal_update(rtwdev);
rtw89_phy_thermal_protect(rtwdev);
rtw89_phy_stat_rssi_update(rtwdev);
rtw89_phy_stat_update(rtwdev);
phystat->last_pkt_stat = phystat->cur_pkt_stat;
memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
rtw89_for_each_active_bb(rtwdev, bb) {
bb->last_pkt_stat = bb->cur_pkt_stat;
memset(&bb->cur_pkt_stat, 0, sizeof(bb->cur_pkt_stat));
}
}
static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev,
@ -6401,6 +6775,29 @@ static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev,
return true;
}
static bool rtw89_phy_edcca_clm_get_result(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb)
{
const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
struct rtw89_env_monitor_info *env = &bb->env_monitor;
const struct rtw89_ccx_regs *ccx = phy->ccx;
u32 val;
val = rtw89_phy_read32_idx(rtwdev, ccx->edcca_clm_rdy,
ccx->edcca_clm_rdy_mask, bb->phy_idx);
if (!val) {
rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
"Get EDCCA_CLM report Fail\n");
return false;
}
val = rtw89_phy_read32_idx(rtwdev, ccx->edcca_clm_cnt,
ccx->edcca_clm_cnt_mask, bb->phy_idx);
env->edcca_clm_ratio = rtw89_phy_ccx_get_report(rtwdev, bb, val, PERCENT);
return true;
}
static void rtw89_phy_nhm_th_update(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb)
{
@ -6568,6 +6965,9 @@ static void __rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev,
if (rtw89_phy_ifs_clm_get_result(rtwdev, bb))
env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
if (rtw89_phy_edcca_clm_get_result(rtwdev, bb))
env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_EDCCA_CLM;
rtw89_phy_ccx_racing_release(rtwdev, bb);
para.mntr_time = 1900;
para.rac_lv = RTW89_RAC_LV_1;
@ -6685,10 +7085,21 @@ static void rtw89_physts_enable_hdr_2(struct rtw89_dev *rtwdev, enum rtw89_phy_i
static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx)
{
const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
const struct rtw89_chip_info *chip = rtwdev->chip;
u32 monitor_mode_mu_ies = 0;
u32 monitor_mode_su_ies = 0;
u32 val;
u8 i;
if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
monitor_mode_mu_ies = BIT(RTW89_PHYSTS_IE09_FTR_0);
if (phy->physt_gen < 2)
monitor_mode_mu_ies |= BIT(RTW89_PHYSTS_IE10_FTR_PLCP_EXT);
monitor_mode_su_ies = BIT(RTW89_PHYSTS_IE09_FTR_0);
}
rtw89_physts_enable_fail_report(rtwdev, false, phy_idx);
/* enable hdr_2 for 8922D (PHYSTS_BE_GEN2 above) */
@ -6702,6 +7113,7 @@ static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev,
val = rtw89_physts_get_ie_bitmap(rtwdev, i, phy_idx);
if (i == RTW89_HE_MU || i == RTW89_VHT_MU) {
val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF);
val |= monitor_mode_mu_ies;
} else if (i == RTW89_TRIG_BASE_PPDU) {
val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF) |
BIT(RTW89_PHYSTS_IE01_CMN_OFDM);
@ -6715,11 +7127,14 @@ static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev,
val |= BIT(RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0);
}
if (i == RTW89_HE_PKT || i == RTW89_VHT_PKT)
val |= monitor_mode_su_ies;
rtw89_physts_set_ie_bitmap(rtwdev, i, val, phy_idx);
}
}
static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
{
__rtw89_physts_parsing_init(rtwdev, RTW89_PHY_0);
if (rtwdev->dbcc_en)
@ -6825,11 +7240,15 @@ static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev,
static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb)
{
const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
struct rtw89_dig_info *dig = &bb->dig;
bool is_linked = rtwdev->total_sta_assoc > 0;
struct rtw89_entity_conf conf;
const struct rtw89_chan *chan;
const u16 *fa_th_src = NULL;
rtw89_entity_get_conf(rtwdev, &conf);
chan = conf.chans[bb->phy_idx];
switch (chan->band_type) {
case RTW89_BAND_2G:
dig->lna_gain = dig->lna_gain_g;
@ -6870,6 +7289,7 @@ static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev,
dig->dyn_igi_max = igi_max_performance_mode;
dig->dyn_igi_min = dynamic_igi_min;
dig->dyn_pd_th_max = dynamic_pd_threshold_max;
dig->dyn_pd_max_cnt = 0;
dig->pd_low_th_ofst = pd_low_th_offset;
dig->is_linked_pre = false;
}
@ -6993,6 +7413,7 @@ static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev,
igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
dig->fa_rssi_ofst = igi_offset;
dig->noisy_lv = noisy_lv;
rtw89_debug(rtwdev, RTW89_DBG_DIG,
"fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
@ -7159,14 +7580,26 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb,
u8 rssi, bool enable)
{
const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
struct rtw89_dig_info *dig = &bb->dig;
struct rtw89_hal *hal = &rtwdev->hal;
u8 final_rssi, under_region = dig->pd_low_th_ofst;
struct rtw89_entity_conf conf;
const struct rtw89_chan *chan;
s8 cck_cca_th;
u32 pd_val;
pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi, enable, chan);
rtw89_entity_get_conf(rtwdev, &conf);
chan = conf.chans[bb->phy_idx];
if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DIG_PD)) {
pd_val = hal->fixed_dig_pd_th;
rtw89_debug(rtwdev, RTW89_DBG_DIG,
"Fixed DIG: PD_low=%d\n", pd_val);
} else {
pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi, enable, chan);
}
dig->bak_dig = pd_val;
rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
@ -7174,17 +7607,24 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
dig_regs->pd_spatial_reuse_en, enable, bb->phy_idx);
if (!rtwdev->hal.support_cckpd)
if (!hal->support_cckpd)
return;
final_rssi = min_t(u8, rssi, dig->igi_rssi);
under_region = rtw89_phy_dig_cal_under_region(rtwdev, bb, chan);
cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DIG_PD)) {
pd_val = hal->fixed_dig_cck_pd_th;
rtw89_debug(rtwdev, RTW89_DBG_DIG,
"igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
final_rssi, cck_cca_th, under_region, pd_val);
rtw89_debug(rtwdev, RTW89_DBG_DIG,
"Fixed DIG: cck_PD_low=((%d))dB\n", pd_val);
} else {
final_rssi = min_t(u8, rssi, dig->igi_rssi);
under_region = rtw89_phy_dig_cal_under_region(rtwdev, bb, chan);
cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
rtw89_debug(rtwdev, RTW89_DBG_DIG,
"igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
final_rssi, cck_cca_th, under_region, pd_val);
}
rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_reg,
dig_regs->bmode_cca_rssi_limit_en, enable, bb->phy_idx);
@ -7204,10 +7644,33 @@ void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
rtw89_phy_dig_update_para(rtwdev, bb);
}
static void rtw89_phy_dig_diag(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb, bool is_linked)
{
#define RTW89_DIAG_BB_PD_MAX_PERIOD 5
struct rtw89_diag_bb *diag = &bb->diag;
struct rtw89_dig_info *dig = &bb->dig;
diag->diag_bb_bitmap &= ~BIT(RTW89_DIAG_BB_PD);
if (dig->dyn_igi_max != dig->igi_fa_rssi ||
dig->noisy_lv < RTW89_DIG_NOISY_LEVEL_MAX) {
dig->dyn_pd_max_cnt = 0;
return;
}
if (++dig->dyn_pd_max_cnt < RTW89_DIAG_BB_PD_MAX_PERIOD || !is_linked)
return;
diag->diag_bb_bitmap |= BIT(RTW89_DIAG_BB_PD);
diag->diag_bb_cnt[RTW89_DIAG_BB_PD]++;
}
#define IGI_RSSI_MIN 10
#define ABS_IGI_MIN 0xc
static
void rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
void rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb, bool is_linked)
{
struct rtw89_dig_info *dig = &bb->dig;
u8 igi_min;
@ -7225,6 +7688,8 @@ void rtw89_phy_cal_igi_fa_rssi(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb
} else {
dig->igi_fa_rssi = dig->dyn_igi_max;
}
rtw89_phy_dig_diag(rtwdev, bb, is_linked);
}
struct rtw89_phy_iter_mcc_dig {
@ -7253,7 +7718,7 @@ static void rtw89_phy_set_mcc_dig(struct rtw89_dev *rtwdev,
}
chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
rtw89_phy_cal_igi_fa_rssi(rtwdev, bb);
rtw89_phy_cal_igi_fa_rssi(rtwdev, bb, is_linked);
pd_val = __rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi,
is_linked, chan);
rtw89_fw_h2c_mcc_dig(rtwdev, rtwvif_link->chanctx_idx,
@ -7315,6 +7780,7 @@ static void rtw89_phy_dig_ctrl(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb
{
const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
struct rtw89_dig_info *dig = &bb->dig;
struct rtw89_hal *hal = &rtwdev->hal;
bool en_dig;
u32 pd_val;
@ -7323,10 +7789,16 @@ static void rtw89_phy_dig_ctrl(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb
if (pause_dig) {
en_dig = false;
pd_val = 0;
if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DIG_PD))
pd_val = hal->fixed_dig_pd_th;
else
pd_val = 0;
} else {
en_dig = rtwdev->total_sta_assoc > 0;
pd_val = restore ? dig->bak_dig : 0;
if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DIG_PD))
pd_val = hal->fixed_dig_pd_th;
else
pd_val = restore ? dig->bak_dig : 0;
}
rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s <%s> PD_low=%d", __func__,
@ -7391,7 +7863,7 @@ static void __rtw89_phy_dig(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
}
dig->is_linked_pre = is_linked;
rtw89_phy_cal_igi_fa_rssi(rtwdev, bb);
rtw89_phy_cal_igi_fa_rssi(rtwdev, bb, is_linked);
rtw89_debug(rtwdev, RTW89_DBG_DIG,
"rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n",
@ -7646,6 +8118,14 @@ static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
__rtw89_phy_env_monitor_init(rtwdev, bb);
}
static void rtw89_phy_diag_init(struct rtw89_dev *rtwdev)
{
struct rtw89_bb_ctx *bb;
rtw89_for_each_capab_bb(rtwdev, bb)
memset(&bb->diag, 0, sizeof(bb->diag));
}
static void __rtw89_phy_edcca_init(struct rtw89_dev *rtwdev,
struct rtw89_bb_ctx *bb)
{
@ -7686,6 +8166,7 @@ void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
rtw89_chip_bb_sethw(rtwdev);
rtw89_phy_diag_init(rtwdev);
rtw89_phy_env_monitor_init(rtwdev);
rtw89_phy_nhm_setting_init(rtwdev);
rtw89_physts_parsing_init(rtwdev);
@ -7750,12 +8231,24 @@ void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev)
__rtw89_phy_dm_init_data(rtwdev, bb);
}
void __rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, u8 bss_color, u16 aid,
enum rtw89_phy_idx phy_idx)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
phy_idx);
rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
bss_color, phy_idx);
rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
aid, phy_idx);
}
void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
struct rtw89_vif_link *rtwvif_link)
{
struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
struct ieee80211_bss_conf *bss_conf;
u8 bss_color;
@ -7772,12 +8265,7 @@ void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
rcu_read_unlock();
rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
phy_idx);
rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
bss_color, phy_idx);
rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
vif->cfg.aid, phy_idx);
__rtw89_phy_set_bss_color(rtwdev, bss_color, vif->cfg.aid, phy_idx);
}
static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc)
@ -8262,6 +8750,24 @@ void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb
edcca_regs->ppdu_mask, th, bb->phy_idx);
}
static void rtw89_phy_edcca_diag(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
{
#define RTW89_DIAG_BB_EDCCA_RATIO_TH 50
#define RTW89_DIAG_BB_EDCCA_TX_TH 10
struct rtw89_env_monitor_info *env = &bb->env_monitor;
struct rtw89_traffic_stats *stats = &rtwdev->stats;
struct rtw89_diag_bb *diag = &bb->diag;
diag->diag_bb_bitmap &= ~BIT(RTW89_DIAG_BB_EDCCA);
if (stats->tx_throughput <= RTW89_DIAG_BB_EDCCA_TX_TH ||
env->edcca_clm_ratio <= RTW89_DIAG_BB_EDCCA_RATIO_TH)
return;
diag->diag_bb_bitmap |= BIT(RTW89_DIAG_BB_EDCCA);
diag->diag_bb_cnt[RTW89_DIAG_BB_EDCCA]++;
}
static
void __rtw89_phy_edcca_track(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
{
@ -8269,6 +8775,7 @@ void __rtw89_phy_edcca_track(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
rtw89_phy_edcca_thre_calc(rtwdev, bb);
rtw89_phy_edcca_log(rtwdev, bb);
rtw89_phy_edcca_diag(rtwdev, bb);
}
void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev)
@ -8419,12 +8926,37 @@ static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = {
.nhm_en_mask = B_NHM_EN_MSK,
.nhm_method = R_NHM_TH9,
.nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK,
.edcca_clm_rdy = R_CLM_EDCCA_RDY,
.edcca_clm_rdy_mask = B_CLM_EDCCA_RDY,
.edcca_clm_cnt = R_CLM_EDCCA_RESULT,
.edcca_clm_cnt_mask = B_CLM_EDCCA_RESULT,
};
static const u32 rtw89_txinfo_reg_ax[] = {
R_TX_INFO_0_0_COMB,
R_TX_INFO_0_1_COMB,
R_TX_INFO_1_0_COMB,
R_TX_INFO_1_1_COMB
};
static const u32 rtw89_tx_common_ctrl_reg_ax[] = {
R_TX_COMMON_CTRL_0_0_COMB,
R_TX_COMMON_CTRL_0_1_COMB
};
static const struct rtw89_reg_def rtw89_txpwr_ax[] = {
{.addr = R_PATH0_TXPWR, .mask = B_PATH0_TXPWR},
{.addr = R_PATH1_TXPWR, .mask = B_PATH1_TXPWR}
};
static const struct rtw89_physts_regs rtw89_physts_regs_ax = {
.setting_addr = R_PLCP_HISTOGRAM,
.dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
.dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
.mac_phy_intf_sel = {R_INTF_R_INTF_RPT_SEL, B_INTF_R_INTF_RPT_SEL},
.txpwr = rtw89_txpwr_ax,
.tx_info = RTW89_REGS_DEF(rtw89_txinfo_reg_ax),
.tx_common_ctrl = RTW89_REGS_DEF(rtw89_tx_common_ctrl_reg_ax),
};
static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = {
@ -8438,6 +8970,10 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
.cr_base = 0x10000,
.physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START,
.physt_bmp_eht = 0xfc,
.physt_ie_len = {16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32},
.physt_gen = 0,
.ccx = &rtw89_ccx_regs_ax,
.physts = &rtw89_physts_regs_ax,
.cfo = &rtw89_cfo_regs_ax,

164
drivers/net/wireless/realtek/rtw89/phy.h
View File

@ -57,6 +57,25 @@
#define RA_MASK_EHT_4SS_MCS0_11 GENMASK_ULL(62, 60)
#define RA_MASK_EHT_RATES GENMASK_ULL(62, 12)
#define TX_STATUS_TYPE GENMASK(3, 0)
#define TX_STATUS_SUBTYPE GENMASK(7, 4)
#define TX_STATUS_TXCMD GENMASK(29, 24)
#define TX_STATUS_TXCMD_V1 GENMASK(13, 8)
#define TX_STATUS_TXCMD_V2 GENMASK(15, 8)
#define TX_STATUS_TXSC GENMASK(7, 4)
#define TX_STATUS_TXSC_V1 GENMASK(27, 24)
#define TX_STATUS_BW GENMASK(17, 16)
#define TX_STATUS_BW_V1 GENMASK(6, 4)
#define TX_STATUS_TMAC_TXPWR GENMASK(26, 18)
#define TX_STATUS_TMAC_TXPWR_V1 GENMASK(16, 8)
#define TX_STATUS_TX_PATH_EN GENMASK(15, 12)
#define TX_STATUS_TX_PATH_EN_V1 GENMASK(7, 4)
#define TX_STATUS_PATH_MAP GENMASK(23, 16)
#define TX_STATUS_PATH_MAP_V1 GENMASK(15, 8)
#define TX_STATUS_MAX_MCS GENMASK(7, 4)
#define TX_STATUS_MAX_MCS_V1 GENMASK(3, 0)
#define TX_STATUS_STBC BIT(0)
#define CFO_TRK_ENABLE_TH (2 << 2)
#define CFO_TRK_STOP_TH_4 (30 << 2)
#define CFO_TRK_STOP_TH_3 (20 << 2)
@ -135,10 +154,14 @@
#define EDCCA_UNIT_CONVER 128
#define EDCCA_PWROFST_DEFAULT 18
#define VAR_LEN 0xff
#define VAR_LEN_UNIT 8
enum rtw89_phy_c2h_ra_func {
RTW89_PHY_C2H_FUNC_STS_RPT,
RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
RTW89_PHY_C2H_FUNC_TXSTS,
RTW89_PHY_C2H_FUNC_TX_HISTORY = 0x4,
RTW89_PHY_C2H_FUNC_ACCELERATE_EN = 0x7,
RTW89_PHY_C2H_FUNC_RA_NUM,
@ -451,12 +474,20 @@ struct rtw89_ccx_regs {
u32 nhm_en_mask;
u32 nhm_method;
u32 nhm_pwr_method_msk;
u32 edcca_clm_rdy;
u32 edcca_clm_rdy_mask;
u32 edcca_clm_cnt;
u32 edcca_clm_cnt_mask;
};
struct rtw89_physts_regs {
u32 setting_addr;
u32 dis_trigger_fail_mask;
u32 dis_trigger_brk_mask;
struct rtw89_reg_def mac_phy_intf_sel;
const struct rtw89_reg_def *txpwr;
struct rtw89_regs_def tx_info;
struct rtw89_regs_def tx_common_ctrl;
};
struct rtw89_cfo_regs {
@ -537,14 +568,113 @@ struct rtw89_txpwr_limit_ru_be {
s8 ru106_26[RTW89_RU_SEC_NUM_BE];
};
#define RTW89_RU484_242_SEC_NUM_BE 4
#define RTW89_RU996_484_SEC_NUM_BE 2
#define RTW89_RU996_484_242_SEC_NUM_BE 2
struct rtw89_txpwr_limit_large_mru_be {
s8 ru484_242[RTW89_NSS_NUM][RTW89_RU484_242_SEC_NUM_BE];
s8 ru996_484[RTW89_NSS_NUM][RTW89_RU996_484_SEC_NUM_BE];
s8 ru996_484_242[RTW89_NSS_NUM][RTW89_RU996_484_242_SEC_NUM_BE];
};
struct rtw89_phy_rfk_log_fmt {
const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM];
};
enum rtw89_mdpd_onoff {
MDPD_ON = 0,
MDPD_OFF = 1,
};
enum rtw89_oob_dpd_onoff {
OOB_DPD_OFF = 0,
OOB_DPD_ON = 1,
};
enum rtw89_cim3k_onoff {
CIM3K_ON = 1,
CIM3K_OFF = 0,
};
enum rtw89_cim3k_en_dis {
CIM3K_ENABLE = 1,
CIM3K_DISABLE = 0,
};
enum rtw89_rfsi_ctrl_modulation {
RFSI_BPSK = 0,
RFSI_QPSK = 1,
RFSI_16QAM = 2,
RFSI_64QAM = 3,
RFSI_256QAM = 4,
RFSI_1024QAM = 5,
RFSI_4096QAM = 6,
RFSI_MAX,
};
enum rtw89_cfir_onoff {
CFIR_ON = 1,
CFIR_OFF = 0,
};
enum rtw89_filter_onoff {
FILTER_A_ON = 1,
FILTER_A_OFF = 0,
};
#define MAX_TX_RFSI_CTRL_OPT 10
#define _8nibble(n0, n1, n2, n3, n4, n5, n6, n7) \
((n0) << 0 | (n1) << 4 | (n2) << 8 | (n3) << 12 | \
(n4) << 16 | (n5) << 20 | (n6) << 24 | (n7) << 28)
#define _qam_comp_code(c) ((((c) & (BIT(15) | BIT(14))) >> 11) | \
(((c) & BIT(12)) >> 10) | \
(((c) & (BIT(9) | BIT(8))) >> 8))
#define _10qam_comp_code(c0, c1, c2, c3, c4, c5, c6, c7, c8, c9) \
_qam_comp_code(c0), _qam_comp_code(c1), _qam_comp_code(c2), _qam_comp_code(c3), \
_qam_comp_code(c4), _qam_comp_code(c5), _qam_comp_code(c6), _qam_comp_code(c7), \
_qam_comp_code(c8), _qam_comp_code(c9)
struct rtw89_bb_wrap_common_data {
struct {
struct rtw89_bb_wrap_data_cim3k {
u8 th, ow, non_bandedge, bandedge;
} cim3k;
u32 rfsi_ct_opt[2];
u8 pb_tb;
} bands[RFSI_CTRL_BAND_NUM];
u8 qam_th[6];
};
struct rtw89_bb_wrap_common_data_gen3 {
struct {
u8 qam_th[6];
} bands[RFSI_CTRL_BAND_NUM];
u8 cck_val[2];
};
struct rtw89_bb_wrap_data {
const struct rtw89_bb_wrap_common_data *common;
const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
struct {
u16 qam_comp_th0[MAX_TX_RFSI_CTRL_OPT];
u16 qam_comp_th1[MAX_TX_RFSI_CTRL_OPT]; /* encoded */
u16 qam_comp_th2[MAX_TX_RFSI_CTRL_OPT]; /* encoded */
u16 qam_comp_ow[MAX_TX_RFSI_CTRL_OPT];
u8 oob_dpd_by_cbw[8];
} bands[RFSI_CTRL_BAND_NUM];
u8 mdpd_by_dbw[4];
};
struct rtw89_phy_gen_def {
u32 cr_base;
u32 physt_bmp_start;
u32 physt_bmp_eht;
u8 physt_ie_len[32];
u8 physt_gen;
const struct rtw89_ccx_regs *ccx;
const struct rtw89_physts_regs *physts;
const struct rtw89_cfo_regs *cfo;
@ -576,30 +706,48 @@ extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax;
extern const struct rtw89_phy_gen_def rtw89_phy_gen_be;
extern const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1;
static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
u32 addr, u8 data)
static inline void rtw89_raw_phy_write8(struct rtw89_dev *rtwdev,
u32 addr, u8 data)
{
const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
rtw89_write8(rtwdev, addr + phy->cr_base, data);
}
static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
u32 addr, u16 data)
static inline void rtw89_raw_phy_write16(struct rtw89_dev *rtwdev,
u32 addr, u16 data)
{
const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
rtw89_write16(rtwdev, addr + phy->cr_base, data);
}
static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
u32 addr, u32 data)
static inline void rtw89_raw_phy_write32(struct rtw89_dev *rtwdev,
u32 addr, u32 data)
{
const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
rtw89_write32(rtwdev, addr + phy->cr_base, data);
}
static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
u32 addr, u8 data)
{
rtwdev->io->phy_write8(rtwdev, addr, data);
}
static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
u32 addr, u16 data)
{
rtwdev->io->phy_write16(rtwdev, addr, data);
}
static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
u32 addr, u32 data)
{
rtwdev->io->phy_write32(rtwdev, addr, data);
}
static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
u32 addr, u32 bits)
{
@ -863,6 +1011,7 @@ void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev);
void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev);
void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev);
void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
u32 data, enum rtw89_phy_idx phy_idx);
void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
@ -904,6 +1053,7 @@ static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev)
}
void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev,
enum rtw89_rfsi_ctrl_band ctrl_band,
enum rtw89_phy_idx phy_idx);
void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
@ -1076,6 +1226,8 @@ void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev);
void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work);
void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
struct rtw89_vif_link *rtwvif_link);
void __rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, u8 bss_color, u16 aid,
enum rtw89_phy_idx phy_idx);
void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx,
enum rtw89_tssi_bandedge_cfg bandedge_cfg);

724
drivers/net/wireless/realtek/rtw89/phy_be.c
View File

@ -74,6 +74,10 @@ static const struct rtw89_ccx_regs rtw89_ccx_regs_be = {
.nhm_en_mask = B_NHM_EN_MSK,
.nhm_method = R_NHM_TH9,
.nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK,
.edcca_clm_rdy = R_CLM_EDCCA_RDY_V1,
.edcca_clm_rdy_mask = B_CLM_EDCCA_RDY,
.edcca_clm_cnt = R_CLM_EDCCA_RESULT_V1,
.edcca_clm_cnt_mask = B_CLM_EDCCA_RESULT,
};
static const struct rtw89_ccx_regs rtw89_ccx_regs_be_v1 = {
@ -133,18 +137,68 @@ static const struct rtw89_ccx_regs rtw89_ccx_regs_be_v1 = {
.ifs_total_addr = R_IFS_TOTAL_BE4,
.ifs_cnt_done_mask = B_IFS_CNT_DONE_BE4,
.ifs_total_mask = B_IFS_TOTAL_BE4,
.edcca_clm_rdy = R_CLM_EDCCA_RDY_BE4,
.edcca_clm_rdy_mask = B_CLM_EDCCA_RDY,
.edcca_clm_cnt = R_CLM_EDCCA_RESULT_BE4,
.edcca_clm_cnt_mask = B_CLM_EDCCA_RESULT,
};
static const u32 rtw89_tx_info_reg_be[] = {
R_TX_INFO_0_0_COMB_V1,
R_TX_INFO_0_1_COMB_V1,
R_TX_INFO_1_0_COMB_V1,
R_TX_INFO_1_1_COMB_V1,
R_TX_INFO_2_0_COMB_V1,
R_TX_INFO_2_1_COMB_V1
};
static const u32 rtw89_tx_common_ctrl_reg_be[] = {
R_TX_COMMON_CTRL_0_0_COMB_V1,
R_TX_COMMON_CTRL_0_1_COMB_V1
};
static const struct rtw89_reg_def rtw89_txpwr_be[] = {
{.addr = R_PATH0_TXPWR_V1, .mask = B_PATH0_TXPWR},
{.addr = R_PATH1_TXPWR_V1, .mask = B_PATH1_TXPWR}
};
static const struct rtw89_physts_regs rtw89_physts_regs_be = {
.setting_addr = R_PLCP_HISTOGRAM,
.dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
.dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
.mac_phy_intf_sel = {R_INTF_R_INTF_RPT_SEL, B_INTF_R_INTF_RPT_SEL},
.txpwr = rtw89_txpwr_be,
.tx_info = RTW89_REGS_DEF(rtw89_tx_info_reg_be),
.tx_common_ctrl = RTW89_REGS_DEF(rtw89_tx_common_ctrl_reg_be),
};
static const u32 rtw89_tx_info_reg_be_v1[] = {
R_TX_INFO_0_0_COMB_BE4,
R_TX_INFO_0_1_COMB_BE4,
R_TX_INFO_1_0_COMB_BE4,
R_TX_INFO_1_1_COMB_BE4,
R_TX_INFO_2_0_COMB_BE4,
R_TX_INFO_2_1_COMB_BE4
};
static const u32 rtw89_tx_common_ctrl_reg_be_v1[] = {
R_TX_COMMON_CTRL_0_0_COMB_BE4,
R_TX_COMMON_CTRL_0_1_COMB_BE4
};
static const struct rtw89_reg_def rtw89_txpwr_be_v1[] = {
{.addr = R_PATH0_TXPWR_BE4, .mask = B_PATH0_TXPWR},
{.addr = R_PATH1_TXPWR_BE4, .mask = B_PATH1_TXPWR}
};
static const struct rtw89_physts_regs rtw89_physts_regs_be_v1 = {
.setting_addr = R_PLCP_HISTOGRAM_BE_V1,
.dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
.dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
.mac_phy_intf_sel = {R_INTF_R_INTF_RPT_SEL_BE4, B_INTF_R_INTF_RPT_SEL},
.txpwr = rtw89_txpwr_be_v1,
.tx_info = RTW89_REGS_DEF(rtw89_tx_info_reg_be_v1),
.tx_common_ctrl = RTW89_REGS_DEF(rtw89_tx_common_ctrl_reg_be_v1),
};
static const struct rtw89_cfo_regs rtw89_cfo_regs_be = {
@ -533,8 +587,8 @@ static void rtw89_phy_bb_wrap_force_cr_init(struct rtw89_dev *rtwdev,
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FORCE_LMT, mac_idx);
rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_LMT_ON, 0);
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, mac_idx);
rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RATE_ON, 0);
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RATE_CTRL, mac_idx);
rtw89_write32_mask(rtwdev, addr, B_BE_FORCE_PWR_BY_RATE_EN, 0);
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_OFST_RULMT, mac_idx);
rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ENON, 0);
rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ON, 0);
@ -542,8 +596,8 @@ static void rtw89_phy_bb_wrap_force_cr_init(struct rtw89_dev *rtwdev,
rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_MACID_ALL, 0);
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_COEX_CTRL, mac_idx);
rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_COEX_ON, 0);
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RATE_CTRL, mac_idx);
rtw89_write32_mask(rtwdev, addr, B_BE_FORCE_PWR_BY_RATE_EN, 0);
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, mac_idx);
rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RATE_ON, 0);
}
static void rtw89_phy_bb_wrap_ftm_init(struct rtw89_dev *rtwdev,
@ -592,15 +646,23 @@ static u32 rtw89_phy_bb_wrap_be_bandedge_decision(struct rtw89_dev *rtwdev,
}
void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev,
enum rtw89_rfsi_ctrl_band rfsi_band,
enum rtw89_phy_idx phy_idx)
{
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const u32 *val;
u32 reg;
if (!d || !d->common)
return;
val = d->common->bands[rfsi_band].rfsi_ct_opt;
reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_0_BE4, phy_idx);
rtw89_write32(rtwdev, reg, 0x00010001);
rtw89_write32(rtwdev, reg, val[0]);
reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_8_BE4, phy_idx);
rtw89_write32(rtwdev, reg, 0x00010001);
rtw89_write32(rtwdev, reg, val[1]);
}
EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_ct_opt);
@ -630,42 +692,52 @@ EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_bandedge_ch);
static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
u8 th0, th1, th2;
if (!d || !d->common)
return;
th0 = d->common->qam_th[0];
th1 = d->common->qam_th[1];
th2 = d->common->qam_th[2];
/* TH0 */
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_0_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_3_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_1_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_4_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_7_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_0_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_3_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_6_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_0_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_3_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_1_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_4_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_7_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_0_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_3_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_6_BE4, th0, mac_idx);
/* TH1 */
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_1_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_4_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_2_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_5_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_8_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_1_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_4_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_7_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_1_BE4, th1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_4_BE4, th1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_2_BE4, th1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_5_BE4, th1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_8_BE4, th1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_1_BE4, th1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_4_BE4, th1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_7_BE4, th1, mac_idx);
/* TH2 */
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_2_BE4, 0x4, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_0_BE4, 0x4, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_3_BE4, 0x4, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_6_BE4, 0x4, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_9_BE4, 0x4, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_2_BE4, 0x4, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_5_BE4, 0x4, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_8_BE4, 0x4, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_2_BE4, th2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_0_BE4, th2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_3_BE4, th2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_6_BE4, th2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_9_BE4, th2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_2_BE4, th2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_5_BE4, th2, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_8_BE4, th2, mac_idx);
/* DPD 160M */
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_0_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_1_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_2_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_3_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_4_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_5_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_6_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_7_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_0_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_1_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_2_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_3_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_4_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_5_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_6_BE4, th0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_7_BE4, th0, mac_idx);
/* DPD 20M */
rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_0_BE4, 0x2, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_1_BE4, 0x2, mac_idx);
@ -697,16 +769,91 @@ static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(struct rtw89_dev *rtwdev,
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH2_BE4, 0x2, mac_idx);
}
static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_mac_idx mac_idx)
{
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
const u8 *ths;
if (!d || !d->common_gen3)
return;
common_gen3 = d->common_gen3;
ths = common_gen3->bands[chan->rfsi_band].qam_th;
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_0_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_1_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_2_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_3_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_4_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_5_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_6_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_7_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH1_0_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH1_1_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_2_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_3_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_4_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_5_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_6_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_7_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_0_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_1_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_2_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_3_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_4_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_5_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_6_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_7_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_0_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_1_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_2_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_3_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_4_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_5_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH3_6_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH3_7_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_0_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_1_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_2_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_3_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_4_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_5_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_6_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_7_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_0_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_1_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_2_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_3_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_4_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_5_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_6_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_7_BE4, ths[5], mac_idx);
}
static void rtw89_phy_bb_wrap_tx_rfsi_scenario_def(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
u8 pb_tb = 0;
if (d && d->common)
pb_tb = d->common->bands[0].pb_tb;
rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_ER_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SUBF_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_FTM_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SENS_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DEF_BE, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_PB_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_PB_BE4, pb_tb, mac_idx);
rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_WO_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_BF_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_MUMIMO_BE4, 0x0, mac_idx);
@ -717,147 +864,229 @@ static void rtw89_phy_bb_wrap_tx_rfsi_scenario_def(struct rtw89_dev *rtwdev,
static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, 0x4010, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKHWORD, 0x4410, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKHWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKHWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKHWORD, 0x0, mac_idx);
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const u16 *th;
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_L, 0x8, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_M, 0x8, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_H, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_L, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_M, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_H, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_L, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_M, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2L, 0x8, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2M, 0x8, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2H, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2L, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2M, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2H, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2L, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2M, 0x0, mac_idx);
if (!d || !d->common)
return;
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, 0x4010, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKHWORD, 0x4010, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKHWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKHWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKHWORD, 0x0, mac_idx);
th = d->bands[0].qam_comp_th0;
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, th[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKHWORD, th[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, th[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKHWORD, th[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, th[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKHWORD, th[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, th[6], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKHWORD, th[7], mac_idx);
th = d->bands[0].qam_comp_th1;
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_L, th[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_M, th[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_H, th[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_L, th[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_M, th[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_H, th[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_L, th[6], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_M, th[7], mac_idx);
th = d->bands[0].qam_comp_th2;
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2L, th[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2M, th[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2H, th[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2L, th[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2M, th[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2H, th[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2L, th[6], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2M, th[7], mac_idx);
th = d->bands[0].qam_comp_ow;
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, th[0], mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKHWORD, th[1], mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, th[2], mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKHWORD, th[3], mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, th[4], mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKHWORD, th[5], mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, th[6], mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKHWORD, th[7], mac_idx);
}
static void rtw89_phy_bb_set_oob_dpd_qam_comp_val(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK7_BE4, 0x0, mac_idx);
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
u8 th;
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK7_BE4, 0x0, mac_idx);
if (!d)
return;
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH7_BE4, 0x0, mac_idx);
th = d->bands[0].oob_dpd_by_cbw[0];
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK7_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH7_BE4, 0x0, mac_idx);
th = d->bands[0].oob_dpd_by_cbw[1];
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK7_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH7_BE4, 0x0, mac_idx);
th = d->bands[0].oob_dpd_by_cbw[2];
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH7_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW7_BE4, 0x0, mac_idx);
th = d->bands[0].oob_dpd_by_cbw[3];
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH7_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW7_BE4, 0x0, mac_idx);
th = d->bands[0].oob_dpd_by_cbw[4];
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH7_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW7_BE4, 0x0, mac_idx);
th = d->bands[0].oob_dpd_by_cbw[5];
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW7_BE4, th, mac_idx);
th = d->bands[0].oob_dpd_by_cbw[6];
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW7_BE4, th, mac_idx);
th = d->bands[0].oob_dpd_by_cbw[7];
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW7_BE4, th, mac_idx);
}
static void rtw89_phy_bb_set_mdpd_qam_comp_val(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH7_BE4, 0x0, mac_idx);
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
u8 th;
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW0_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW1_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW2_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW3_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW4_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW5_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW6_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW7_BE4, 0x0, mac_idx);
if (!d)
return;
th = d->mdpd_by_dbw[0];
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH7_BE4, th, mac_idx);
th = d->mdpd_by_dbw[2];
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW0_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW1_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW2_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW3_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW4_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW5_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW6_BE4, th, mac_idx);
rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW7_BE4, th, mac_idx);
}
static void rtw89_phy_bb_set_cim3k_val(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_OW_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_NONBE_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_BANDEDGE_BE4, 0x1, mac_idx);
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const struct rtw89_bb_wrap_data_cim3k *p;
if (!d || !d->common)
return;
p = &d->common->bands[0].cim3k;
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH_BE4, p->th, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_OW_BE4, p->ow, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_NONBE_BE4,
p->non_bandedge, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_BANDEDGE_BE4,
p->bandedge, mac_idx);
if (rtwdev->chip->chip_id != RTL8922D)
return;
rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_EN, 1, mac_idx);
rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_VAL, 0, mac_idx);
}
static void rtw89_phy_bb_set_cck_cfir_filter_val_gen3(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
u8 cck0, cck1;
if (!d || !d->common_gen3)
return;
common_gen3 = d->common_gen3;
cck0 = common_gen3->cck_val[0];
cck1 = common_gen3->cck_val[1];
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR0_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR1_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR2_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR3_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR4_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR5_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR6_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR7_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR0_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR1_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR2_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR3_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR4_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR5_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR6_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR7_BE4, cck1, mac_idx);
}
static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev,
@ -865,23 +1094,25 @@ static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev,
{
enum rtw89_phy_idx phy_idx = mac_idx != RTW89_MAC_0 ? RTW89_PHY_1 : RTW89_PHY_0;
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
struct rtw89_entity_conf conf;
const struct rtw89_chan *chan;
if (chip_id != RTL8922D)
return;
rtw89_entity_get_conf(rtwdev, &conf);
chan = conf.chans[phy_idx];
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(rtwdev, mac_idx);
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(rtwdev, chan, mac_idx);
rtw89_phy_bb_wrap_tx_rfsi_scenario_def(rtwdev, mac_idx);
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(rtwdev, mac_idx);
rtw89_phy_bb_set_oob_dpd_qam_comp_val(rtwdev, mac_idx);
rtw89_phy_bb_set_mdpd_qam_comp_val(rtwdev, mac_idx);
rtw89_phy_bb_set_cim3k_val(rtwdev, mac_idx);
rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, phy_idx);
chan = rtw89_mgnt_chan_get(rtwdev, phy_idx);
if (chan)
rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx);
rtw89_phy_bb_set_cck_cfir_filter_val_gen3(rtwdev, mac_idx);
rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, 0, phy_idx);
rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx);
}
static void rtw89_phy_bb_wrap_ul_pwr(struct rtw89_dev *rtwdev)
@ -1468,11 +1699,168 @@ static void rtw89_phy_fill_limit_ru_be(struct rtw89_dev *rtwdev,
}
}
static
void rtw89_phy_fill_limit_ru484_242_be(struct rtw89_dev *rtwdev,
s8 (*lmt)[RTW89_RU484_242_SEC_NUM_BE],
u8 ntx, u8 band, u8 ch, u8 bw)
{
switch (bw) {
case RTW89_CHANNEL_WIDTH_80:
(*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU484_242,
ntx, ch);
break;
case RTW89_CHANNEL_WIDTH_160:
(*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU484_242,
ntx, ch - 8);
(*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU484_242,
ntx, ch + 8);
break;
case RTW89_CHANNEL_WIDTH_320:
(*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU484_242,
ntx, ch - 24);
(*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU484_242,
ntx, ch - 8);
(*lmt)[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU484_242,
ntx, ch + 8);
(*lmt)[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU484_242,
ntx, ch + 24);
break;
}
}
static
void rtw89_phy_fill_limit_ru996_484_be(struct rtw89_dev *rtwdev,
s8 (*lmt)[RTW89_RU996_484_SEC_NUM_BE],
u8 ntx, u8 band, u8 ch, u8 bw)
{
switch (bw) {
case RTW89_CHANNEL_WIDTH_160:
(*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU996_484,
ntx, ch);
break;
case RTW89_CHANNEL_WIDTH_320:
(*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU996_484,
ntx, ch - 16);
(*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU996_484,
ntx, ch + 16);
break;
}
}
static
void rtw89_phy_fill_limit_ru996_484_242_be(struct rtw89_dev *rtwdev,
s8 (*lmt)[RTW89_RU996_484_242_SEC_NUM_BE],
u8 ntx, u8 band, u8 ch, u8 bw)
{
switch (bw) {
case RTW89_CHANNEL_WIDTH_160:
(*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU996_484_242,
ntx, ch);
break;
case RTW89_CHANNEL_WIDTH_320:
(*lmt)[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU996_484_242,
ntx, ch - 16);
(*lmt)[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
RTW89_RU996_484_242,
ntx, ch + 16);
break;
}
}
static
void rtw89_phy_fill_limit_large_mru_be(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
struct rtw89_txpwr_limit_large_mru_be *lmt,
bool has_bf)
{
u8 band = chan->band_type;
u8 ch = chan->channel;
u8 bw = chan->band_width;
int i;
memset(lmt, 0, sizeof(*lmt));
if (has_bf)
return;
for (i = 0; i <= RTW89_NSS_2; i++) {
rtw89_phy_fill_limit_ru484_242_be(rtwdev, &lmt->ru484_242[i],
i, band, ch, bw);
rtw89_phy_fill_limit_ru996_484_be(rtwdev, &lmt->ru996_484[i],
i, band, ch, bw);
rtw89_phy_fill_limit_ru996_484_242_be(rtwdev, &lmt->ru996_484_242[i],
i, band, ch, bw);
}
}
static
void rtw89_phy_conf_limit_large_mru_be(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx,
bool has_bf)
{
struct rtw89_txpwr_limit_large_mru_be lmt_lmru;
u32 addr, val;
rtw89_phy_fill_limit_large_mru_be(rtwdev, chan, &lmt_lmru, has_bf);
addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU484_242_0 :
R_BE_TXAGC_MAX_1TX_RU484_242_0;
val = u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][0], GENMASK(7, 0)) |
u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][1], GENMASK(15, 8)) |
u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][2], GENMASK(23, 16)) |
u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_1][3], GENMASK(31, 24));
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
val = u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][0], GENMASK(7, 0)) |
u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][1], GENMASK(15, 8)) |
u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][2], GENMASK(23, 16)) |
u32_encode_bits(lmt_lmru.ru484_242[RTW89_NSS_2][3], GENMASK(31, 24));
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr + 4, val);
addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU996_484_0 :
R_BE_TXAGC_MAX_1TX_RU996_484_0;
val = u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_1][0], GENMASK(7, 0)) |
u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_1][1], GENMASK(15, 8)) |
u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_2][0], GENMASK(23, 16)) |
u32_encode_bits(lmt_lmru.ru996_484[RTW89_NSS_2][1], GENMASK(31, 24));
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
addr = has_bf ? R_BE_TXAGC_MAX_1TX_BF_RU996_484_242_0 :
R_BE_TXAGC_MAX_1TX_RU996_484_242_0;
val = u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_1][0], GENMASK(7, 0)) |
u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_1][1], GENMASK(15, 8)) |
u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_2][0], GENMASK(23, 16)) |
u32_encode_bits(lmt_lmru.ru996_484_242[RTW89_NSS_2][1], GENMASK(31, 24));
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
}
static void rtw89_phy_set_txpwr_limit_ru_be(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_txpwr_limit_ru_be lmt_ru;
struct rtw89_hal *hal = &rtwdev->hal;
const s8 *ptr;
u32 addr, val;
u8 i, j;
@ -1499,12 +1887,22 @@ static void rtw89_phy_set_txpwr_limit_ru_be(struct rtw89_dev *rtwdev,
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
}
}
if (!(chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090))
return;
rtw89_phy_conf_limit_large_mru_be(rtwdev, chan, phy_idx, false);
rtw89_phy_conf_limit_large_mru_be(rtwdev, chan, phy_idx, true);
}
const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
.cr_base = 0x20000,
.physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START,
.physt_bmp_eht = R_PHY_STS_BITMAP_EHT,
.physt_ie_len = {32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN,
VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32},
.physt_gen = 1,
.ccx = &rtw89_ccx_regs_be,
.physts = &rtw89_physts_regs_be,
.cfo = &rtw89_cfo_regs_be,
@ -1526,6 +1924,10 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = {
.cr_base = 0x0,
.physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START_BE4,
.physt_bmp_eht = R_PHY_STS_BITMAP_EHT_BE4,
.physt_ie_len = {32, 40, 24, 24, 16, 16, 16, 16, VAR_LEN, VAR_LEN, VAR_LEN, 168,
VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 32, 56,
96, VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32},
.physt_gen = 2,
.ccx = &rtw89_ccx_regs_be_v1,
.physts = &rtw89_physts_regs_be_v1,
.cfo = &rtw89_cfo_regs_be_v1,

6
drivers/net/wireless/realtek/rtw89/ps.c
View File

@ -234,8 +234,14 @@ void rtw89_enter_ips(struct rtw89_dev *rtwdev)
{
struct rtw89_vif_link *rtwvif_link;
struct rtw89_vif *rtwvif;
struct rtw89_hal *hal = &rtwdev->hal;
unsigned int link_id;
if (hal->disabled_dm_bitmap & BIT(RTW89_DM_INACTIVE_PS)) {
rtw89_debug(rtwdev, RTW89_DBG_PS, "skip enter IPS due to disabled_dm\n");
return;
}
set_bit(RTW89_FLAG_INACTIVE_PS, rtwdev->flags);
if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))

289
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -164,6 +164,19 @@
#define R_AX_DBG_PORT_SEL 0x00C0
#define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
#define R_AX_PAD_CTRL2 0x00C4
#define B_AX_FORCE_U3_CK BIT(23)
#define B_AX_USB2_FORCE BIT(22)
#define B_AX_USB3_FORCE BIT(21)
#define B_AX_USB3_USB2_TRANSITION BIT(20)
#define B_AX_USB23_SW_MODE_V1 GENMASK(19, 18)
#define USB_MODE_U2 0x1
#define USB_MODE_U3 0x2
#define B_AX_NO_PDN_CHIPOFF_V1 BIT(17)
#define B_AX_RSM_EN_V1 BIT(16)
#define B_AX_MATCH_CNT GENMASK(15, 8)
#define USB_SWITCH_DELAY 0xF
#define R_AX_PMC_DBG_CTRL2 0x00CC
#define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2)
@ -4235,6 +4248,20 @@
#define B_BE_TOGGLE BIT(31)
#define B_BE_DATA_LINE_MASK GENMASK(30, 0)
#define R_BE_PAD_CTRL2 0x00C4
#define B_BE_USB23_SW_MODE BIT(31)
#define B_BE_USB3_GEN_MODE BIT(30)
#define B_BE_USB3_LANE_MODE BIT(29)
#define B_BE_USB_AUTO_INSTALL_MASK BIT(28)
#define B_BE_FORCE_CLK_U2 BIT(25)
#define B_BE_FORCE_U2_CK BIT(24)
#define B_BE_FORCE_U3_CK BIT(23)
#define B_BE_USB2_FORCE BIT(22)
#define B_BE_USB3_FORCE BIT(21)
#define B_BE_NO_PDN_CHIPOFF_V1 BIT(17)
#define B_BE_RSM_EN_V1 BIT(16)
#define B_BE_MATCH_CNT GENMASK(15, 8)
#define R_BE_PMC_DBG_CTRL2 0x00CC
#define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
#define B_BE_DIS_IOWRAP_TIMEOUT BIT(16)
@ -4329,6 +4356,10 @@
#define R_BE_SECURE_BOOT_MALLOC_INFO 0x0184
#define R_BE_FW_AUTO_CAL_DELAY 0x0188
#define B_BE_WCPU_FW_DELAY_COUNT_VALID BIT(15)
#define B_BE_WCPU_FW_DELAY_COUNT_MASK GENMASK(14, 0)
#define R_BE_FWS0IMR 0x0190
#define B_BE_FS_HALT_H2C_INT_EN BIT(31)
#define B_BE_FS_FSM_HIOE_TO_EVENT_INT_EN BIT(30)
@ -4806,6 +4837,10 @@
#define R_BE_LTR_LATENCY_IDX2_V1 0x361C
#define R_BE_LTR_LATENCY_IDX3_V1 0x3620
#define R_BE_USB2_WLAN_TRX_OPT_PAR2 0x41BC
#define B_BE_USB2_USBRX_RST BIT(1)
#define B_BE_USB2_USBTX_RST BIT(0)
#define R_BE_HCI_BUF_IMR 0x6018
#define B_BE_HCI_BUF_IMR_CLR 0xC0000303
#define B_BE_HCI_BUF_IMR_SET 0xC0000301
@ -8354,6 +8389,11 @@
#define R_BE_PWR_LISTEN_PATH 0x11988
#define B_BE_PWR_LISTEN_PATH_EN GENMASK(31, 28)
#define R_BE_TXAGC_MAX_1TX_RU484_242_0 0x11990
#define R_BE_TXAGC_MAX_1TX_RU996_484_0 0x119A4
#define R_BE_TXAGC_MAX_1TX_RU996_484_242_0 0x119AC
#define R_BE_TXAGC_MAX_1TX_BF_RU484_242_0 0x119DC
#define R_BE_PWR_REF_CTRL 0x11A20
#define B_BE_PWR_REF_CTRL_OFDM GENMASK(9, 1)
#define B_BE_PWR_REF_CTRL_CCK GENMASK(18, 10)
@ -8391,6 +8431,8 @@
B_BE_PWR_FORCE_MACID_EN_VAL | \
B_BE_PWR_FORCE_MACID_EN_ON)
#define R_BE_TXAGC_MAX_1TX_BF_RU996_484_0 0x11A4C
#define R_BE_PWR_REG_CTRL 0x11A50
#define B_BE_PWR_BT_EN BIT(23)
@ -8404,6 +8446,8 @@
#define R_BE_PWR_TH 0x11A78
#define R_BE_PWR_RSSI_TARGET_LMT 0x11A84
#define R_BE_TXAGC_MAX_1TX_BF_RU996_484_242_0 0x11ADC
#define R_BE_PWR_OFST_SW 0x11AE8
#define B_BE_PWR_OFST_SW_DB GENMASK(27, 24)
@ -8462,6 +8506,8 @@
#define RR_MODOPT_V1 0x10001
#define RR_SW_SEL BIT(19)
#define RR_TXG_SEL GENMASK(19, 17)
#define RR_TBL_SEL_IDX1 GENMASK(9, 8)
#define RR_TBL_SEL_IDX0 GENMASK(7, 6)
#define RR_MODOPT_M_TXPWR GENMASK(5, 0)
#define RR_WLSEL 0x02
#define RR_WLSEL_AG GENMASK(18, 16)
@ -8735,6 +8781,9 @@
#define B_DFS_FFT_EN BIT(0)
#define R_CHINFO_DATA 0x00C0
#define B_CHINFO_DATA_BITMAP GENMASK(22, 0)
#define R_INTF_R_INTF_RPT_SEL 0x0200
#define R_INTF_R_INTF_RPT_SEL_BE4 0x20200
#define B_INTF_R_INTF_RPT_SEL BIT(12)
#define R_ANAPAR_PW15 0x030C
#define B_ANAPAR_PW15 GENMASK(31, 24)
#define B_ANAPAR_PW15_H GENMASK(27, 24)
@ -8793,6 +8842,12 @@
#define R_P0_ANT_SW 0x0728
#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12)
#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
#define R_RST_ALL_CNT 0x0730
#define R_RST_ALL_CNT_BE4 0x20730
#define B_RST_ALL_CNT BIT(0)
#define R_ENABLE_ALL_CNT 0x0730
#define R_ENABLE_ALL_CNT_BE4 0x20730
#define B_ENABLE_ALL_CNT BIT(1)
#define R_MAC_PIN_SEL 0x0734
#define R_MAC_PIN_SEL_BE4 0x20734
#define B_CH_IDX_SEG0 GENMASK(23, 16)
@ -8943,6 +8998,8 @@
#define B_RXHT_MCS_LIMIT GENMASK(9, 8)
#define R_RXVHT_MCS_LIMIT 0x0D18
#define B_RXVHT_MCS_LIMIT GENMASK(22, 21)
#define R_BRK_OPT 0x0D44
#define B_BRK_OPT BIT(31)
#define R_P0_EN_SOUND_WO_NDP 0x0D7C
#define B_P0_EN_SOUND_WO_NDP BIT(1)
#define R_RXHE 0x0D80
@ -8998,6 +9055,21 @@
#define R_CFO_COMP_SEG0_L 0x1384
#define R_CFO_COMP_SEG0_H 0x1388
#define R_CFO_COMP_SEG0_CTRL 0x138C
#define R_CNT_CCKTXEN 0x1700
#define R_CNT_CCKTXEN_V1 0x2E00
#define R_CNT_CCKTXEN_BE4 0x2CF00
#define B_CNT_CCKTXEN GENMASK(31, 16)
#define R_CNT_CCKTXON 0x1704
#define R_CNT_CCKTXON_V1 0x2E04
#define R_CNT_CCKTXON_BE4 0x2CF04
#define B_CNT_CCKTXON GENMASK(15, 0)
#define R_CNT_CCK_CCA_P0 0x1710
#define R_CNT_CCK_CCA_P0_V1 0x2E10
#define B_CNT_CCK_CCA_P0 GENMASK(15, 0)
#define R_CNT_CCK_CRC32_P0 0x1714
#define R_CNT_CCK_CRC32_P0_V1 0x2E14
#define B_CNT_CCK_CRC32OK_P0 GENMASK(15, 0)
#define B_CNT_CCK_CRC32FAIL_P0 GENMASK(31, 16)
#define R_DBG32_D 0x1730
#define R_EDCCA_RPT_A 0x1738
#define R_EDCCA_RPT_B 0x173c
@ -9013,7 +9085,87 @@
#define B_SWSI_W_BUSY_V1 BIT(24)
#define B_SWSI_R_BUSY_V1 BIT(25)
#define B_SWSI_R_DATA_DONE_V1 BIT(26)
#define R_TX_INFO_0_0_COMB 0x1800
#define R_TX_INFO_0_0_COMB_V1 0x3E00
#define R_TX_INFO_0_1_COMB 0x1804
#define R_TX_INFO_0_1_COMB_V1 0x3E04
#define R_TX_INFO_1_0_COMB 0x1808
#define R_TX_INFO_1_0_COMB_V1 0x3E08
#define R_TX_INFO_1_1_COMB 0x180C
#define R_TX_INFO_1_1_COMB_V1 0x3E0C
#define R_TX_INFO_2_0_COMB_V1 0x3E10
#define R_TX_INFO_2_1_COMB_V1 0x3E14
#define R_TX_COMMON_CTRL_0_0_COMB 0x1810
#define R_TX_COMMON_CTRL_0_0_COMB_V1 0x3E20
#define R_TX_COMMON_CTRL_0_1_COMB 0x1814
#define R_TX_COMMON_CTRL_0_1_COMB_V1 0x3E24
#define R_CNT_LSIG_BRK_S_TH 0x1A00
#define R_CNT_LSIG_BRK_S_TH_V1 0x0E00
#define R_CNT_LSIG_BRK_S_TH_BE4 0x20E00
#define B_CNT_LSIG_BRK_S_TH GENMASK(31, 16)
#define R_CNT_CCA_SPOOFING 0x1A00
#define R_CNT_CCA_SPOOFING_V1 0x0E00
#define R_CNT_CCA_SPOOFING_BE4 0x20E00
#define B_CNT_CCA_SPOOFING GENMASK(15, 0)
#define R_CNT_LSIG_BRK_L_TH 0x1A04
#define R_CNT_LSIG_BRK_L_TH_V1 0x0E04
#define R_CNT_LSIG_BRK_L_TH_BE4 0x20E04
#define B_CNT_LSIG_BRK_L_TH GENMASK(15, 0)
#define R_CNT_BRK 0x1A08
#define R_CNT_BRK_V1 0x0E08
#define R_CNT_BRK_BE4 0x20E08
#define B_CNT_BRK GENMASK(31, 16)
#define R_CNT_RXL_ERR_PARITY 0x1A0C
#define R_CNT_RXL_ERR_PARITY_V1 0x0E0C
#define R_CNT_RXL_ERR_PARITY_BE4 0x20E0C
#define B_CNT_RXL_ERR_PARITY GENMASK(31, 16)
#define R_CNT_RXL_ERR_RATE 0x1A10
#define R_CNT_RXL_ERR_RATE_V1 0x0E10
#define R_CNT_RXL_ERR_RATE_BE4 0x20E10
#define B_CNT_RXL_ERR_RATE GENMASK(15, 0)
#define R_CNT_SEARCH_FAIL 0x1A20
#define R_CNT_SEARCH_FAIL_V1 0x0E20
#define R_CNT_SEARCH_FAIL_BE4 0x20E20
#define B_CNT_SEARCH_FAIL GENMASK(31, 16)
#define R_CNT_OFDM_CCA 0x1A24
#define R_CNT_OFDM_CCA_V1 0x0E24
#define R_CNT_OFDM_CCA_BE4 0x20E24
#define B_CNT_OFDM_CCA GENMASK(15, 0)
#define R_TX_COUNTER 0x1A40
#define R_CNT_OFDMTXON 0x1A40
#define R_CNT_OFDMTXON_V1 0x0E40
#define R_CNT_OFDMTXON_BE4 0x20E40
#define B_CNT_OFDMTXON GENMASK(15, 0)
#define B_CNT_OFDMTXEN GENMASK(31, 16)
#define R_CNT_HE_CRC 0x1A58
#define R_CNT_HE_CRC_V1 0x0E58
#define R_CNT_HE_CRC_BE4 0x20E58
#define B_CNT_HE_CRC_OK GENMASK(15, 0)
#define B_CNT_HE_CRC_ERR GENMASK(31, 16)
#define R_CNT_VHT_CRC 0x1A5C
#define R_CNT_VHT_CRC_V1 0x0E5C
#define R_CNT_VHT_CRC_BE4 0x20E5C
#define B_CNT_VHT_CRC_OK GENMASK(15, 0)
#define B_CNT_VHT_CRC_ERR GENMASK(31, 16)
#define R_CNT_HT_CRC 0x1A60
#define R_CNT_HT_CRC_V1 0x0E60
#define R_CNT_HT_CRC_BE4 0x20E60
#define B_CNT_HT_CRC_OK GENMASK(15, 0)
#define B_CNT_HT_CRC_ERR GENMASK(31, 16)
#define R_CNT_L_CRC 0x1A64
#define R_CNT_L_CRC_V1 0x0E64
#define R_CNT_L_CRC_BE4 0x20E64
#define B_CNT_L_CRC_OK GENMASK(15, 0)
#define B_CNT_L_CRC_ERR GENMASK(31, 16)
#define R_CNT_AMPDU_MISS 0x1A7C
#define R_CNT_AMPDU_MISS_V1 0x0E7C
#define R_CNT_AMPDU_MISS_BE4 0x20E7C
#define B_CNT_AMPDU_MISS GENMASK(31, 16)
#define R_CNT_AMPDU_RX_CRC32 0x1A80
#define R_CNT_AMPDU_RX_CRC32_V1 0x0E80
#define R_CNT_AMPDU_RX_CRC32_BE4 0x20E80
#define B_CNT_AMPDU_RX_CRC32_OK GENMASK(15, 0)
#define B_CNT_AMPDU_RX_CRC32_ERR GENMASK(31, 16)
#define R_NHM_CNT0 0x1A88
#define B_NHM_CNT0_MSK GENMASK(15, 0)
#define B_NHM_CNT1_MSK GENMASK(31, 16)
@ -9034,6 +9186,14 @@
#define B_NHM_CNT11_MSK GENMASK(31, 16)
#define R_NHM_AX 0x1AA4
#define B_NHM_READY_MSK BIT(16)
#define R_CLM_EDCCA_RESULT 0x1AC8
#define R_CLM_EDCCA_RESULT_V1 0x0EC8
#define R_CLM_EDCCA_RESULT_BE4 0x20EC8
#define B_CLM_EDCCA_RESULT GENMASK(15, 0)
#define R_CLM_EDCCA_RDY 0x1AC8
#define R_CLM_EDCCA_RDY_V1 0x0EC8
#define R_CLM_EDCCA_RDY_BE4 0x20EC8
#define B_CLM_EDCCA_RDY BIT(16)
#define R_IFS_CLM_TX_CNT 0x1ACC
#define R_IFS_CLM_TX_CNT_V1 0x0ECC
#define R_IFS_CLM_TX_CNT_BE4 0x20ECC
@ -9089,6 +9249,8 @@
#define B_TXAGC_BB GENMASK(31, 24)
#define B_TXAGC_RF GENMASK(5, 0)
#define R_PATH0_TXPWR 0x1C78
#define R_PATH0_TXPWR_V1 0xEE0C
#define R_PATH0_TXPWR_BE4 0x2F90C
#define B_PATH0_TXPWR GENMASK(8, 0)
#define R_S0_ADDCK 0x1E00
#define B_S0_ADDCK_I GENMASK(9, 0)
@ -9131,12 +9293,41 @@
#define B_RXCCA_DIS_V1 BIT(0)
#define R_RXSC 0x237C
#define B_RXSC_EN BIT(0)
#define R_R1B_RR_SEL 0x2388
#define B_R1B_RR_SEL GENMASK(24, 23)
#define R_R1B_RX_RPT_RST 0x2388
#define R_R1B_RX_RPT_RST_V1 0x2340
#define R_R1B_RX_RPT_RST_BE 0x0540
#define R_R1B_RX_RPT_RST_BE4 0x20540
#define B_R1B_RX_RPT_RST BIT(15)
#define B_R1B_RX_RPT_RST_V1 BIT(7)
#define R_BRK_CNT 0x239C
#define R_BRK_CNT_V1 0x059C
#define R_BRK_CNT_BE4 0x2059C
#define B_BRK_CNT GENMASK(31, 16)
#define R_RX_RPL_OFST 0x23AC
#define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
#define R_RXSCOBC 0x23B0
#define B_RXSCOBC_TH GENMASK(18, 0)
#define R_RXSCOCCK 0x23B4
#define B_RXSCOCCK_TH GENMASK(18, 0)
#define R_SFD_GG_CNT 0x23E0
#define R_SFD_GG_CNT_V1 0x23A0
#define R_SFD_GG_CNT_V2 0x05A0
#define R_SFD_GG_CNT_BE4 0x205A0
#define B_SFD_GG_CNT GENMASK(15, 0)
#define R_SIG_GG_CNT 0x23E8
#define R_SIG_GG_CNT_V1 0x23AC
#define R_SIG_GG_CNT_V2 0x05AC
#define R_SIG_GG_CNT_BE4 0x205AC
#define B_SIG_GG_CNT GENMASK(15, 0)
#define B_SIG_GG_CNT_V1 GENMASK(15, 8)
#define R_SPOOF_CNT 0x23EC
#define R_SPOOF_CNT_V1 0x23A8
#define R_SPOOF_CNT_V2 0x05A8
#define R_SPOOF_CNT_BE4 0x205A8
#define B_SPOOF_CNT GENMASK(7, 0)
#define B_SPOOF_CNT_V1 GENMASK(31, 16)
#define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410
#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1 BIT(14)
#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13)
@ -9173,6 +9364,10 @@
#define R_EDCCA_RPT_B_BE4_C1 0x2FE34
#define R_EDCCA_RPT_P1_A_BE 0x2E40
#define R_EDCCA_RPT_P1_B_BE 0x2E44
#define R_CNT_EHT_CRC 0x2F00
#define R_CNT_EHT_CRC_BE4 0x22F00
#define B_CNT_EHT_CRC_OK GENMASK(15, 0)
#define B_CNT_EHT_CRC_ERR GENMASK(31, 16)
#define R_S1_HW_SI_DIS 0x3200
#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
#define R_P1_RXCK 0x32A0
@ -9200,6 +9395,8 @@
#define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
#define B_TXAGC_BB_S1 GENMASK(31, 24)
#define R_PATH1_TXPWR 0x3C78
#define R_PATH1_TXPWR_V1 0xEF0C
#define R_PATH1_TXPWR_BE4 0x2FA0C
#define B_PATH1_TXPWR GENMASK(8, 0)
#define R_S1_ADDCK 0x3E00
#define B_S1_ADDCK_I GENMASK(9, 0)
@ -10439,9 +10636,25 @@
#define B_FBTB_CT_MUMIMO_BE4 GENMASK(19, 16)
#define B_FBTB_CT_FTM_BE4 GENMASK(23, 20)
#define B_FBTB_CT_SENS_BE4 GENMASK(27, 24)
#define R_CIM3K_SU_FORCE 0x119F8
#define B_CIM3K_SU_FORCE_EN BIT(17)
#define B_CIM3K_SU_FORCE_VAL BIT(18)
#define R_QAM3_TH0_BE4 0x119FC
#define B_QAM3_TH0_0_BE4 GENMASK(2, 0)
#define B_QAM3_TH0_1_BE4 GENMASK(5, 3)
#define B_QAM3_TH0_2_BE4 GENMASK(8, 6)
#define B_QAM3_TH0_3_BE4 GENMASK(11, 9)
#define B_QAM3_TH0_4_BE4 GENMASK(14, 12)
#define B_QAM3_TH0_5_BE4 GENMASK(17, 15)
#define B_QAM3_TH0_6_BE4 GENMASK(20, 18)
#define B_QAM3_TH0_7_BE4 GENMASK(23, 21)
#define B_QAM3_TH1_0_BE4 GENMASK(26, 24)
#define B_QAM3_TH1_1_BE4 GENMASK(29, 27)
#define R_RFSI_CT_OPT_0_BE4 0x11A94
#define R_RFSI_CT_OPT_8_BE4 0x11A98
#define R_QAM_COMP_TH0_BE4 0x11A9C
#define B_QAM_COMP_TH_TRIANGULAR_L GENMASK(11, 10)
#define B_QAM_COMP_TH_TRIANGULAR_H GENMASK(27, 26)
#define R_QAM_COMP_TH1_BE4 0x11AA0
#define R_QAM_COMP_TH2_BE4 0x11AA4
#define R_QAM_COMP_TH3_BE4 0x11AA8
@ -10465,6 +10678,8 @@
#define B_QAM_COMP_TH6_2L GENMASK(9, 5)
#define B_QAM_COMP_TH6_2M GENMASK(19, 15)
#define R_OW_VAL_0_BE4 0x11AAC
#define B_OW_VAL_TRIANGULAR_L GENMASK(11, 10)
#define B_OW_VAL_TRIANGULAR_H GENMASK(27, 26)
#define R_OW_VAL_1_BE4 0x11AB0
#define R_OW_VAL_2_BE4 0x11AB4
#define R_OW_VAL_3_BE4 0x11AB8
@ -10474,6 +10689,65 @@
#define B_BANDEDGE_DBW80_BE4 BIT(31)
#define R_BANDEDGE_DBWY_BE4 0x11AD0
#define B_BANDEDGE_DBW160_BE4 BIT(0)
#define R_QAM3_TH1_BE4 0x11BE8
#define B_QAM3_TH1_2_BE4 GENMASK(2, 0)
#define B_QAM3_TH1_3_BE4 GENMASK(5, 3)
#define B_QAM3_TH1_4_BE4 GENMASK(8, 6)
#define B_QAM3_TH1_5_BE4 GENMASK(11, 9)
#define B_QAM3_TH1_6_BE4 GENMASK(14, 12)
#define B_QAM3_TH1_7_BE4 GENMASK(17, 15)
#define B_QAM3_TH2_0_BE4 GENMASK(20, 18)
#define B_QAM3_TH2_1_BE4 GENMASK(23, 21)
#define B_QAM3_TH2_2_BE4 GENMASK(26, 24)
#define B_QAM3_TH2_3_BE4 GENMASK(29, 27)
#define R_QAM3_TH2_BE4 0x11BEC
#define B_QAM3_TH2_4_BE4 GENMASK(2, 0)
#define B_QAM3_TH2_5_BE4 GENMASK(5, 3)
#define B_QAM3_TH2_6_BE4 GENMASK(8, 6)
#define B_QAM3_TH2_7_BE4 GENMASK(11, 9)
#define B_QAM3_TH3_0_BE4 GENMASK(14, 12)
#define B_QAM3_TH3_1_BE4 GENMASK(17, 15)
#define B_QAM3_TH3_2_BE4 GENMASK(20, 18)
#define B_QAM3_TH3_3_BE4 GENMASK(23, 21)
#define B_QAM3_TH3_4_BE4 GENMASK(26, 24)
#define B_QAM3_TH3_5_BE4 GENMASK(29, 27)
#define R_QAM3_TH3_BE4 0x11BF4
#define B_QAM3_TH3_6_BE4 GENMASK(2, 0)
#define B_QAM3_TH3_7_BE4 GENMASK(5, 3)
#define B_QAM3_TH5_0_BE4 GENMASK(8, 6)
#define B_QAM3_TH5_1_BE4 GENMASK(11, 9)
#define B_QAM3_TH5_2_BE4 GENMASK(14, 12)
#define B_QAM3_TH5_3_BE4 GENMASK(17, 15)
#define B_QAM3_TH5_4_BE4 GENMASK(20, 18)
#define B_QAM3_TH5_5_BE4 GENMASK(23, 21)
#define B_QAM3_TH5_6_BE4 GENMASK(26, 24)
#define B_QAM3_TH5_7_BE4 GENMASK(29, 27)
#define R_QAM3_TH4_BE4 0x11BF8
#define B_QAM3_TH4_0_BE4 GENMASK(2, 0)
#define B_QAM3_TH4_1_BE4 GENMASK(5, 3)
#define B_QAM3_TH4_2_BE4 GENMASK(8, 6)
#define B_QAM3_TH4_3_BE4 GENMASK(11, 9)
#define B_QAM3_TH4_4_BE4 GENMASK(14, 12)
#define B_QAM3_TH4_5_BE4 GENMASK(17, 15)
#define B_QAM3_TH4_6_BE4 GENMASK(20, 18)
#define B_QAM3_TH4_7_BE4 GENMASK(23, 21)
#define B_QAM3_CFIR0_BE4 BIT(24)
#define B_QAM3_CFIR1_BE4 BIT(25)
#define B_QAM3_CFIR2_BE4 BIT(26)
#define B_QAM3_CFIR3_BE4 BIT(27)
#define B_QAM3_CFIR4_BE4 BIT(28)
#define B_QAM3_CFIR5_BE4 BIT(29)
#define B_QAM3_CFIR6_BE4 BIT(30)
#define B_QAM3_CFIR7_BE4 BIT(31)
#define R_QAM3_FLTR_BE4 0x11BFC
#define B_QAM3_FLTR0_BE4 GENMASK(1, 0)
#define B_QAM3_FLTR1_BE4 GENMASK(3, 2)
#define B_QAM3_FLTR2_BE4 GENMASK(5, 4)
#define B_QAM3_FLTR3_BE4 GENMASK(7, 6)
#define B_QAM3_FLTR4_BE4 GENMASK(9, 8)
#define B_QAM3_FLTR5_BE4 GENMASK(11, 10)
#define B_QAM3_FLTR6_BE4 GENMASK(13, 12)
#define B_QAM3_FLTR7_BE4 GENMASK(15, 14)
#define R_SYS_DBCC_BE4 0x20000
#define B_SYS_DBCC_BE4 BIT(0)
@ -10541,6 +10815,11 @@
#define R_IFS_T3_HIS_BE4 0x20F54
#define B_IFS_T3_HIS_BE4 GENMASK(15, 0)
#define B_IFS_T4_HIS_BE4 GENMASK(31, 16)
#define R_CNT_CCK_CCA_BE4 0x20FE8
#define B_CNT_CCK_CCA_BE4 GENMASK(15, 0)
#define R_CNT_CCK_CRC32_BE4 0x20FEC
#define B_CNT_CCK_CRC32OK_BE4 GENMASK(15, 0)
#define B_CNT_CCK_CRC32FAIL_BE4 GENMASK(31, 16)
#define R_TX_ERROR_SEL_BE4 0x21254
#define B_TX_ERROR_PSDU_BE4 BIT(11)
@ -10680,6 +10959,14 @@
#define B_SW_SI_R_BUSY_BE4 BIT(25)
#define B_SW_SI_READ_DATA_DONE_BE4 BIT(26)
#define R_TX_INFO_0_0_COMB_BE4 0x2DF00
#define R_TX_INFO_0_1_COMB_BE4 0x2DF04
#define R_TX_INFO_1_0_COMB_BE4 0x2DF08
#define R_TX_INFO_1_1_COMB_BE4 0x2DF0C
#define R_TX_INFO_2_0_COMB_BE4 0x2DF10
#define R_TX_INFO_2_1_COMB_BE4 0x2DF14
#define R_TX_COMMON_CTRL_0_0_COMB_BE4 0x2DF20
#define R_TX_COMMON_CTRL_0_1_COMB_BE4 0x2DF24
#define R_RX_PATH0_TBL0_BE4 0x2E028
#define R_RX_PATH1_TBL0_BE4 0x2E128
@ -10687,6 +10974,8 @@
#define R_KTBL0B_BE4 0x38204
#define B_KTBL0_IDX0 GENMASK(1, 0)
#define B_KTBL0_IDX1 GENMASK(9, 8)
#define B_KTBL0_MLD_IDX0 GENMASK(25, 24)
#define B_KTBL0_MLD_IDX1 GENMASK(27, 26)
#define B_KTBL0_RST BIT(31)
#define R_KTBL1A_BE4 0x38154
#define R_KTBL1B_BE4 0x38254

24
drivers/net/wireless/realtek/rtw89/regd.c
View File

@ -360,6 +360,7 @@ static void rtw89_regd_setup_unii4(struct rtw89_dev *rtwdev,
struct wiphy *wiphy)
{
struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
bool skip_acpi_dsm = rtwdev->hci.type == RTW89_HCI_TYPE_USB;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct ieee80211_supported_band *sband;
struct rtw89_acpi_dsm_result res = {};
@ -377,6 +378,9 @@ static void rtw89_regd_setup_unii4(struct rtw89_dev *rtwdev,
return;
}
if (skip_acpi_dsm)
return;
bitmap_fill(regulatory->block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_UNII4_SUP, &res);
@ -426,6 +430,7 @@ static void __rtw89_regd_setup_policy_6ghz(struct rtw89_dev *rtwdev, bool block,
static void rtw89_regd_setup_policy_6ghz(struct rtw89_dev *rtwdev)
{
struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
bool skip_acpi_dsm = rtwdev->hci.type == RTW89_HCI_TYPE_USB;
const struct rtw89_acpi_country_code *country;
const struct rtw89_acpi_policy_6ghz *ptr;
struct rtw89_acpi_dsm_result res = {};
@ -433,6 +438,9 @@ static void rtw89_regd_setup_policy_6ghz(struct rtw89_dev *rtwdev)
int i, j;
int ret;
if (skip_acpi_dsm)
return;
ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_6G_BP, &res);
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_REGD,
@ -478,12 +486,16 @@ static void rtw89_regd_setup_policy_6ghz(struct rtw89_dev *rtwdev)
static void rtw89_regd_setup_policy_6ghz_sp(struct rtw89_dev *rtwdev)
{
struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
bool skip_acpi_dsm = rtwdev->hci.type == RTW89_HCI_TYPE_USB;
const struct rtw89_acpi_policy_6ghz_sp *ptr;
struct rtw89_acpi_dsm_result res = {};
bool enable;
u8 index;
int ret;
if (skip_acpi_dsm)
return;
ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_6GHZ_SP_SUP, &res);
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_REGD,
@ -524,6 +536,7 @@ static void rtw89_regd_setup_policy_6ghz_sp(struct rtw89_dev *rtwdev)
static void rtw89_regd_setup_policy_6ghz_vlp(struct rtw89_dev *rtwdev)
{
struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
bool skip_acpi_dsm = rtwdev->hci.type == RTW89_HCI_TYPE_USB;
const struct rtw89_acpi_policy_6ghz_vlp *ptr = NULL;
struct rtw89_acpi_dsm_result res = {};
bool enable;
@ -531,6 +544,9 @@ static void rtw89_regd_setup_policy_6ghz_vlp(struct rtw89_dev *rtwdev)
int ret;
u8 val;
if (skip_acpi_dsm)
return;
/* By default, allow 6 GHz VLP on all countries except US and CA. */
val = ~(RTW89_ACPI_CONF_6GHZ_VLP_US | RTW89_ACPI_CONF_6GHZ_VLP_CA);
@ -574,6 +590,7 @@ static void rtw89_regd_setup_6ghz(struct rtw89_dev *rtwdev, struct wiphy *wiphy)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
bool chip_support_6ghz = chip->support_bands & BIT(NL80211_BAND_6GHZ);
bool skip_acpi_dsm = rtwdev->hci.type == RTW89_HCI_TYPE_USB;
bool regd_allow_6ghz = chip_support_6ghz;
struct ieee80211_supported_band *sband;
struct rtw89_acpi_dsm_result res = {};
@ -583,6 +600,9 @@ static void rtw89_regd_setup_6ghz(struct rtw89_dev *rtwdev, struct wiphy *wiphy)
if (!chip_support_6ghz)
goto bottom;
if (skip_acpi_dsm)
goto bottom;
ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_6G_DIS, &res);
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_REGD,
@ -661,10 +681,14 @@ const char *rtw89_regd_get_string(enum rtw89_regulation_type regd)
static void rtw89_regd_setup_reg_rules(struct rtw89_dev *rtwdev)
{
struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
bool skip_acpi_dsm = rtwdev->hci.type == RTW89_HCI_TYPE_USB;
const struct rtw89_acpi_policy_reg_rules *ptr;
struct rtw89_acpi_dsm_result res = {};
int ret;
if (skip_acpi_dsm)
return;
regulatory->txpwr_uk_follow_etsi = true;
ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_REG_RULES_EN, &res);

58
drivers/net/wireless/realtek/rtw89/rtw8851b.c
View File

@ -307,6 +307,54 @@ static const struct rtw89_edcca_regs rtw8851b_edcca_regs = {
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
};
static const struct rtw89_pmac_regs rtw8851b_pmac_regs = {
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
.cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
.cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
.cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
.cck_brk = {},
.brk = {R_CNT_BRK, B_CNT_BRK},
.brk_option = {},
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
.r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
.cck_crc32 = R_CNT_CCK_CRC32_P0,
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
.ofdm_txon = R_CNT_OFDMTXON,
.ofdm_txon_mask = B_CNT_OFDMTXON,
.ofdm_txen_mask = B_CNT_OFDMTXEN,
.l_crc = R_CNT_L_CRC,
.l_crc_ok_mask = B_CNT_L_CRC_OK,
.l_crc_err_mask = B_CNT_L_CRC_ERR,
.ht_crc = R_CNT_HT_CRC,
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
.vht_crc = R_CNT_VHT_CRC,
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
.he_crc = R_CNT_HE_CRC,
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
.eht_crc = 0,
.eht_crc_ok_mask = 0,
.eht_crc_err_mask = 0,
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
};
static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = {
{255, 0, 0, 7}, /* 0 -> original */
{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
@ -2508,6 +2556,7 @@ static const struct rtw89_chip_ops rtw8851b_chip_ops = {
.read_efuse = rtw8851b_read_efuse,
.read_phycap = rtw8851b_read_phycap,
.fem_setup = NULL,
.data_setup = NULL,
.rfe_gpio = rtw8851b_rfe_gpio,
.rfk_hw_init = NULL,
.rfk_init = rtw8851b_rfk_init,
@ -2599,13 +2648,16 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
.max_rx_agg_num = 64,
.dis_2g_40m_ul_ofdma = true,
.rsvd_ple_ofst = 0x2f800,
.hfc_param_ini = {rtw8851b_hfc_param_ini_pcie,
.qta_def = {
.hfc_param_ini = {rtw8851b_hfc_param_ini_pcie,
rtw8851b_hfc_param_ini_usb,
rtw8851b_hfc_param_ini_usb,
NULL},
.dle_mem = {rtw8851b_dle_mem_pcie,
.dle_mem = {rtw8851b_dle_mem_pcie,
rtw8851b_dle_mem_usb2,
rtw8851b_dle_mem_usb3,
NULL},
},
.wde_qempty_acq_grpnum = 4,
.wde_qempty_mgq_grpsel = 4,
.rf_base_addr = {0xe000},
@ -2639,6 +2691,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
.support_tas = false,
.support_sar_by_ant = false,
.support_noise = false,
.support_fw_cmd_ofld = false,
.ul_tb_waveform_ctrl = true,
.ul_tb_pwr_diff = false,
.rx_freq_from_ie = true,
@ -2720,6 +2773,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
.edcca_regs = &rtw8851b_edcca_regs,
.pmac_regs = &rtw8851b_pmac_regs,
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8851b,
#endif

1
drivers/net/wireless/realtek/rtw89/rtw8851be.c
View File

@ -73,6 +73,7 @@ static const struct rtw89_driver_info rtw89_8851be_info = {
.chip = &rtw8851b_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8851b_pci_info,
},

4
drivers/net/wireless/realtek/rtw89/rtw8851bu.c
View File

@ -31,6 +31,7 @@ static const struct rtw89_driver_info rtw89_8851bu_info = {
.chip = &rtw8851b_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.usb = &rtw8851b_usb_info,
}
@ -44,6 +45,9 @@ static const struct usb_device_id rtw_8851bu_id_table[] = {
/* D-Link AX9U rev. A1 */
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x332a, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8851bu_info },
/* Mercusys MA60XNB */
{ USB_DEVICE_AND_INTERFACE_INFO(0x2C4E, 0x0128, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8851bu_info },
/* TP-Link Archer TX10UB Nano */
{ USB_DEVICE_AND_INTERFACE_INFO(0x3625, 0x010b, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8851bu_info },

63
drivers/net/wireless/realtek/rtw89/rtw8852a.c
View File

@ -621,6 +621,54 @@ static const struct rtw89_edcca_regs rtw8852a_edcca_regs = {
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
};
static const struct rtw89_pmac_regs rtw8852a_pmac_regs = {
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
.cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
.cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
.cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
.cck_brk = {},
.brk = {R_CNT_BRK, B_CNT_BRK},
.brk_option = {},
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
.r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
.cck_crc32 = R_CNT_CCK_CRC32_P0,
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
.ofdm_txon = R_CNT_OFDMTXON,
.ofdm_txon_mask = B_CNT_OFDMTXON,
.ofdm_txen_mask = B_CNT_OFDMTXEN,
.l_crc = R_CNT_L_CRC,
.l_crc_ok_mask = B_CNT_L_CRC_OK,
.l_crc_err_mask = B_CNT_L_CRC_ERR,
.ht_crc = R_CNT_HT_CRC,
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
.vht_crc = R_CNT_VHT_CRC,
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
.he_crc = R_CNT_HE_CRC,
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
.eht_crc = 0,
.eht_crc_ok_mask = 0,
.eht_crc_err_mask = 0,
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
};
static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
struct rtw8852a_efuse *map)
{
@ -2158,13 +2206,14 @@ static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
struct rtw89_rx_phy_ppdu *phy_ppdu,
struct ieee80211_rx_status *status)
{
u8 path;
struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, phy_ppdu->phy_idx);
u8 *rx_power = phy_ppdu->rssi;
u8 path;
u8 raw;
if (!status->signal) {
if (phy_ppdu->to_self)
raw = ewma_rssi_read(&rtwdev->phystat.bcn_rssi);
raw = ewma_rssi_read(&bb->bcn_rssi);
else
raw = max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]);
@ -2253,6 +2302,7 @@ static const struct rtw89_chip_ops rtw8852a_chip_ops = {
.read_efuse = rtw8852a_read_efuse,
.read_phycap = rtw8852a_read_phycap,
.fem_setup = rtw8852a_fem_setup,
.data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = NULL,
.rfk_init = rtw8852a_rfk_init,
@ -2335,13 +2385,16 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.max_rx_agg_num = 64,
.dis_2g_40m_ul_ofdma = true,
.rsvd_ple_ofst = 0x6f800,
.hfc_param_ini = {rtw8852a_hfc_param_ini_pcie,
.qta_def = {
.hfc_param_ini = {rtw8852a_hfc_param_ini_pcie,
rtw8852a_hfc_param_ini_usb,
rtw8852a_hfc_param_ini_usb,
NULL},
.dle_mem = {rtw8852a_dle_mem_pcie,
.dle_mem = {rtw8852a_dle_mem_pcie,
rtw8852a_dle_mem_usb,
rtw8852a_dle_mem_usb,
NULL},
},
.wde_qempty_acq_grpnum = 16,
.wde_qempty_mgq_grpsel = 16,
.rf_base_addr = {0xc000, 0xd000},
@ -2376,6 +2429,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.support_tas = false,
.support_sar_by_ant = false,
.support_noise = true,
.support_fw_cmd_ofld = false,
.ul_tb_waveform_ctrl = false,
.ul_tb_pwr_diff = false,
.rx_freq_from_ie = true,
@ -2456,6 +2510,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
.dma_ch_mask = 0,
.edcca_regs = &rtw8852a_edcca_regs,
.pmac_regs = &rtw8852a_pmac_regs,
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8852a,
#endif

1
drivers/net/wireless/realtek/rtw89/rtw8852ae.c
View File

@ -71,6 +71,7 @@ static const struct rtw89_driver_info rtw89_8852ae_info = {
.chip = &rtw8852a_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8852a_pci_info,
},

1
drivers/net/wireless/realtek/rtw89/rtw8852au.c
View File

@ -33,6 +33,7 @@ static const struct rtw89_driver_info rtw89_8852au_info = {
.chip = &rtw8852a_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.usb = &rtw8852a_usb_info,
}

58
drivers/net/wireless/realtek/rtw89/rtw8852b.c
View File

@ -259,6 +259,54 @@ static const struct rtw89_edcca_regs rtw8852b_edcca_regs = {
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
};
static const struct rtw89_pmac_regs rtw8852b_pmac_regs = {
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
.cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
.cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
.cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
.cck_brk = {},
.brk = {R_CNT_BRK, B_CNT_BRK},
.brk_option = {},
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
.r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
.cck_crc32 = R_CNT_CCK_CRC32_P0,
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
.ofdm_txon = R_CNT_OFDMTXON,
.ofdm_txon_mask = B_CNT_OFDMTXON,
.ofdm_txen_mask = B_CNT_OFDMTXEN,
.l_crc = R_CNT_L_CRC,
.l_crc_ok_mask = B_CNT_L_CRC_OK,
.l_crc_err_mask = B_CNT_L_CRC_ERR,
.ht_crc = R_CNT_HT_CRC,
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
.vht_crc = R_CNT_VHT_CRC,
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
.he_crc = R_CNT_HE_CRC,
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
.eht_crc = 0,
.eht_crc_ok_mask = 0,
.eht_crc_err_mask = 0,
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
};
static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = {
{255, 0, 0, 7}, /* 0 -> original */
{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
@ -835,6 +883,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
.read_efuse = rtw8852bx_read_efuse,
.read_phycap = rtw8852bx_read_phycap,
.fem_setup = NULL,
.data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = NULL,
.rfk_init = rtw8852b_rfk_init,
@ -930,13 +979,16 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.max_rx_agg_num = 64,
.dis_2g_40m_ul_ofdma = true,
.rsvd_ple_ofst = 0x2f800,
.hfc_param_ini = {rtw8852b_hfc_param_ini_pcie,
.qta_def = {
.hfc_param_ini = {rtw8852b_hfc_param_ini_pcie,
rtw8852b_hfc_param_ini_usb,
rtw8852b_hfc_param_ini_usb,
NULL},
.dle_mem = {rtw8852b_dle_mem_pcie,
.dle_mem = {rtw8852b_dle_mem_pcie,
rtw8852b_dle_mem_usb3,
rtw8852b_dle_mem_usb3,
NULL},
},
.wde_qempty_acq_grpnum = 4,
.wde_qempty_mgq_grpsel = 4,
.rf_base_addr = {0xe000, 0xf000},
@ -972,6 +1024,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.support_tas = false,
.support_sar_by_ant = true,
.support_noise = false,
.support_fw_cmd_ofld = false,
.ul_tb_waveform_ctrl = true,
.ul_tb_pwr_diff = false,
.rx_freq_from_ie = true,
@ -1054,6 +1107,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
.edcca_regs = &rtw8852b_edcca_regs,
.pmac_regs = &rtw8852b_pmac_regs,
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8852b,
#endif

6
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
View File

@ -4167,11 +4167,15 @@ void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
void rtw8852b_mcc_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, 0);
struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V0] = {};
struct rtw89_entity_conf conf;
const struct rtw89_chan *chan;
u8 idx;
rtw89_entity_get_conf(rtwdev, &conf);
chan = conf.chans[0];
for (idx = 0; idx < ARRAY_SIZE(desc); idx++) {
struct rtw89_rfk_chan_desc *p = &desc[idx];

1
drivers/net/wireless/realtek/rtw89/rtw8852be.c
View File

@ -73,6 +73,7 @@ static const struct rtw89_driver_info rtw89_8852be_info = {
.chip = &rtw8852b_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8852b_pci_info,
},

58
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
View File

@ -202,6 +202,54 @@ static const struct rtw89_edcca_regs rtw8852bt_edcca_regs = {
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
};
static const struct rtw89_pmac_regs rtw8852bt_pmac_regs = {
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
.cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
.cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
.cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
.cck_brk = {},
.brk = {R_CNT_BRK, B_CNT_BRK},
.brk_option = {},
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
.r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
.cck_crc32 = R_CNT_CCK_CRC32_P0,
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
.ofdm_txon = R_CNT_OFDMTXON,
.ofdm_txon_mask = B_CNT_OFDMTXON,
.ofdm_txen_mask = B_CNT_OFDMTXEN,
.l_crc = R_CNT_L_CRC,
.l_crc_ok_mask = B_CNT_L_CRC_OK,
.l_crc_err_mask = B_CNT_L_CRC_ERR,
.ht_crc = R_CNT_HT_CRC,
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
.vht_crc = R_CNT_VHT_CRC,
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
.he_crc = R_CNT_HE_CRC,
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
.eht_crc = 0,
.eht_crc_ok_mask = 0,
.eht_crc_err_mask = 0,
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
};
static const struct rtw89_btc_rf_trx_para rtw89_btc_8852bt_rf_ul[] = {
{255, 0, 0, 7}, /* 0 -> original */
{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
@ -681,6 +729,7 @@ static const struct rtw89_chip_ops rtw8852bt_chip_ops = {
.read_efuse = rtw8852bx_read_efuse,
.read_phycap = rtw8852bx_read_phycap,
.fem_setup = NULL,
.data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = NULL,
.rfk_init = rtw8852bt_rfk_init,
@ -776,8 +825,10 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
.max_rx_agg_num = 64,
.dis_2g_40m_ul_ofdma = true,
.rsvd_ple_ofst = 0x6f800,
.hfc_param_ini = {rtw8852bt_hfc_param_ini_pcie, NULL, NULL},
.dle_mem = {rtw8852bt_dle_mem_pcie, NULL, NULL, NULL},
.qta_def = {
.hfc_param_ini = {rtw8852bt_hfc_param_ini_pcie, NULL, NULL, NULL},
.dle_mem = {rtw8852bt_dle_mem_pcie, NULL, NULL, NULL},
},
.wde_qempty_acq_grpnum = 4,
.wde_qempty_mgq_grpsel = 4,
.rf_base_addr = {0xe000, 0xf000},
@ -811,6 +862,8 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
.support_ant_gain = true,
.support_tas = false,
.support_sar_by_ant = true,
.support_noise = false,
.support_fw_cmd_ofld = false,
.ul_tb_waveform_ctrl = true,
.ul_tb_pwr_diff = false,
.rx_freq_from_ie = true,
@ -891,6 +944,7 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
.edcca_regs = &rtw8852bt_edcca_regs,
.pmac_regs = &rtw8852bt_pmac_regs,
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8852bt,
#endif

6
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c
View File

@ -4234,11 +4234,15 @@ void rtw8852bt_set_channel_rf(struct rtw89_dev *rtwdev,
void rtw8852bt_mcc_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, 0);
struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V0] = {};
struct rtw89_entity_conf conf;
const struct rtw89_chan *chan;
u8 idx;
rtw89_entity_get_conf(rtwdev, &conf);
chan = conf.chans[0];
for (idx = 0; idx < ARRAY_SIZE(desc); idx++) {
struct rtw89_rfk_chan_desc *p = &desc[idx];

1
drivers/net/wireless/realtek/rtw89/rtw8852bte.c
View File

@ -79,6 +79,7 @@ static const struct rtw89_driver_info rtw89_8852bte_info = {
.chip = &rtw8852bt_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8852bt_pci_info,
},

1
drivers/net/wireless/realtek/rtw89/rtw8852bu.c
View File

@ -31,6 +31,7 @@ static const struct rtw89_driver_info rtw89_8852bu_info = {
.chip = &rtw8852b_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.usb = &rtw8852b_usb_info,
}

68
drivers/net/wireless/realtek/rtw89/rtw8852c.c
View File

@ -270,6 +270,54 @@ static const struct rtw89_edcca_regs rtw8852c_edcca_regs = {
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
};
static const struct rtw89_pmac_regs rtw8852c_pmac_regs = {
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
.cck_sfd_gg = {R_SFD_GG_CNT_V1, B_SFD_GG_CNT},
.cck_sig_gg = {R_SIG_GG_CNT_V1, B_SIG_GG_CNT_V1},
.cck_spoofing = {R_SPOOF_CNT_V1, B_SPOOF_CNT_V1},
.cck_brk = {R_BRK_CNT, B_BRK_CNT},
.brk = {R_CNT_BRK, B_CNT_BRK},
.brk_option = {R_BRK_OPT, B_BRK_OPT},
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_V1, B_R1B_RX_RPT_RST_V1},
.r1b_rr_sel = {},
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
.cck_crc32 = R_CNT_CCK_CRC32_P0,
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
.ofdm_txon = R_CNT_OFDMTXON,
.ofdm_txon_mask = B_CNT_OFDMTXON,
.ofdm_txen_mask = B_CNT_OFDMTXEN,
.l_crc = R_CNT_L_CRC,
.l_crc_ok_mask = B_CNT_L_CRC_OK,
.l_crc_err_mask = B_CNT_L_CRC_ERR,
.ht_crc = R_CNT_HT_CRC,
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
.vht_crc = R_CNT_VHT_CRC,
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
.he_crc = R_CNT_HE_CRC,
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
.eht_crc = 0,
.eht_crc_ok_mask = 0,
.eht_crc_err_mask = 0,
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
};
static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
enum rtw89_phy_idx phy_idx);
@ -573,6 +621,15 @@ static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
gain->offset_valid = valid;
}
static void rtw8852c_efuse_copy_sn_uuid_usb(struct rtw89_dev *rtwdev,
const struct rtw8852c_efuse *map)
{
struct rtw89_efuse *efuse = &rtwdev->efuse;
memcpy(efuse->sn, map->u.sn, sizeof(efuse->sn));
memcpy(efuse->uuid, map->u.uuid, sizeof(efuse->uuid));
}
static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
enum rtw89_efuse_block block)
{
@ -592,6 +649,7 @@ static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
break;
case RTW89_HCI_TYPE_USB:
ether_addr_copy(efuse->addr, map->u.mac_addr);
rtw8852c_efuse_copy_sn_uuid_usb(rtwdev, map);
break;
default:
return -ENOTSUPP;
@ -3043,6 +3101,7 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
.read_efuse = rtw8852c_read_efuse,
.read_phycap = rtw8852c_read_phycap,
.fem_setup = NULL,
.data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = NULL,
.rfk_init = rtw8852c_rfk_init,
@ -3125,13 +3184,16 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.max_rx_agg_num = 64,
.dis_2g_40m_ul_ofdma = false,
.rsvd_ple_ofst = 0x6f800,
.hfc_param_ini = {rtw8852c_hfc_param_ini_pcie,
.qta_def = {
.hfc_param_ini = {rtw8852c_hfc_param_ini_pcie,
rtw8852c_hfc_param_ini_usb,
rtw8852c_hfc_param_ini_usb,
NULL},
.dle_mem = {rtw8852c_dle_mem_pcie,
.dle_mem = {rtw8852c_dle_mem_pcie,
rtw8852c_dle_mem_usb2,
rtw8852c_dle_mem_usb3,
NULL},
},
.wde_qempty_acq_grpnum = 16,
.wde_qempty_mgq_grpsel = 16,
.rf_base_addr = {0xe000, 0xf000},
@ -3169,6 +3231,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.support_tas = true,
.support_sar_by_ant = true,
.support_noise = false,
.support_fw_cmd_ofld = true,
.ul_tb_waveform_ctrl = false,
.ul_tb_pwr_diff = true,
.rx_freq_from_ie = false,
@ -3250,6 +3313,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
.dma_ch_mask = 0,
.edcca_regs = &rtw8852c_edcca_regs,
.pmac_regs = &rtw8852c_pmac_regs,
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8852c,
#endif

6
drivers/net/wireless/realtek/rtw89/rtw8852c.h
View File

@ -13,7 +13,11 @@
struct rtw8852c_u_efuse {
u8 rsvd[0x88];
u8 mac_addr[ETH_ALEN];
};
u8 rsvd1[8];
u8 sn[RTW89_EFUSE_SN_LEN];
u8 rsvd2[29];
u8 uuid[RTW89_EFUSE_UUID_LEN];
} __packed;
struct rtw8852c_e_efuse {
u8 mac_addr[ETH_ALEN];

1
drivers/net/wireless/realtek/rtw89/rtw8852ce.c
View File

@ -102,6 +102,7 @@ static const struct rtw89_driver_info rtw89_8852ce_info = {
.chip = &rtw8852c_chip_info,
.variant = NULL,
.quirks = rtw8852c_pci_quirks,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8852c_pci_info,
},

13
drivers/net/wireless/realtek/rtw89/rtw8852cu.c
View File

@ -33,6 +33,17 @@ static const struct rtw89_driver_info rtw89_8852cu_info = {
.chip = &rtw8852c_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.usb = &rtw8852c_usb_info,
},
};
static const struct rtw89_driver_info rtw89_8852cu_valve_info = {
.chip = &rtw8852c_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = BIT(RTW89_QUIRK_HW_INFO_SYSFS),
.bus = {
.usb = &rtw8852c_usb_info,
},
@ -52,6 +63,8 @@ static const struct usb_device_id rtw_8852cu_id_table[] = {
{ USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0x991d, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x28de, 0x2432, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_valve_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x2c7c, 0x8206, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x35b2, 0x0502, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },

335
drivers/net/wireless/realtek/rtw89/rtw8922a.c
View File

@ -57,6 +57,126 @@ static const struct rtw89_hfc_param_ini rtw8922a_hfc_param_ini_pcie[] = {
[RTW89_QTA_INVALID] = {NULL},
};
static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_ch7[] = {
{54, 222, grp_0}, /* ACH 0 */
{0, 0, grp_0}, /* ACH 1 */
{54, 222, grp_0}, /* ACH 2 */
{0, 0, grp_0}, /* ACH 3 */
{54, 222, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{54, 222, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{54, 222, grp_0}, /* B0MGQ */
{0, 0, grp_0}, /* B0HIQ */
{54, 222, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0}, /* FWCMDQ */
{0, 0, 0}, /* BMC */
{0, 0, 0}, /* H2D */
};
static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_p7 = {
492, /* Group 0 */
0, /* Group 1 */
492, /* Public Max */
0, /* WP threshold */
};
static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_ch8[] = {
{24, 196, grp_0}, /* ACH 0 */
{0, 0, grp_0}, /* ACH 1 */
{54, 226, grp_0}, /* ACH 2 */
{0, 0, grp_0}, /* ACH 3 */
{54, 196, grp_1}, /* ACH 4 */
{0, 0, grp_1}, /* ACH 5 */
{54, 196, grp_1}, /* ACH 6 */
{0, 0, grp_1}, /* ACH 7 */
{54, 226, grp_0}, /* B0MGQ */
{0, 0, grp_0}, /* B0HIQ */
{54, 196, grp_1}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0}, /* FWCMDQ */
{0, 0, 0}, /* BMC */
{0, 0, 0}, /* H2D */
};
static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_p8 = {
304, /* Group 0 */
304, /* Group 1 */
608, /* Public Max */
96, /* WP threshold */
};
static const struct rtw89_hfc_param_ini rtw8922a_hfc_param_ini_usb2[] = {
[RTW89_QTA_SCC] = {rtw8922a_hfc_chcfg_ch7, &rtw8922a_hfc_pubcfg_p7,
&rtw89_mac_size.hfc_prec_cfg_c5, RTW89_HCIFC_STF},
[RTW89_QTA_DBCC] = {rtw8922a_hfc_chcfg_ch8, &rtw8922a_hfc_pubcfg_p8,
&rtw89_mac_size.hfc_prec_cfg_c6, RTW89_HCIFC_STF},
[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
RTW89_HCIFC_POH},
[RTW89_QTA_INVALID] = {NULL},
};
static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_ch4[] = {
{54, 606, grp_0}, /* ACH 0 */
{0, 0, grp_0}, /* ACH 1 */
{54, 606, grp_0}, /* ACH 2 */
{0, 0, grp_0}, /* ACH 3 */
{54, 606, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{54, 606, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{54, 606, grp_0}, /* B0MGQ */
{0, 0, grp_0}, /* B0HIQ */
{54, 606, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0}, /* FWCMDQ */
{0, 0, 0}, /* BMC */
{0, 0, 0}, /* H2D */
};
static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_p4 = {
876, /* Group 0 */
0, /* Group 1 */
876, /* Public Max */
0, /* WP threshold */
};
static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_ch5[] = {
{54, 311, grp_0}, /* ACH 0 */
{0, 0, grp_0}, /* ACH 1 */
{54, 311, grp_0}, /* ACH 2 */
{0, 0, grp_0}, /* ACH 3 */
{54, 311, grp_1}, /* ACH 4 */
{0, 0, grp_1}, /* ACH 5 */
{54, 311, grp_1}, /* ACH 6 */
{0, 0, grp_1}, /* ACH 7 */
{54, 311, grp_0}, /* B0MGQ */
{0, 0, grp_0}, /* B0HIQ */
{54, 311, grp_1}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0}, /* FWCMDQ */
{0, 0, 0}, /* BMC */
{0, 0, 0}, /* H2D */
};
static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_p5 = {
419, /* Group 0 */
419, /* Group 1 */
838, /* Public Max */
0, /* WP threshold */
};
static const struct rtw89_hfc_param_ini rtw8922a_hfc_param_ini_usb3[] = {
[RTW89_QTA_SCC] = {rtw8922a_hfc_chcfg_ch4, &rtw8922a_hfc_pubcfg_p4,
&rtw89_mac_size.hfc_prec_cfg_c3, RTW89_HCIFC_STF},
[RTW89_QTA_DBCC] = {rtw8922a_hfc_chcfg_ch5, &rtw8922a_hfc_pubcfg_p5,
&rtw89_mac_size.hfc_prec_cfg_c3, RTW89_HCIFC_STF},
[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
RTW89_HCIFC_POH},
[RTW89_QTA_INVALID] = {NULL},
};
static const struct rtw89_dle_mem rtw8922a_dle_mem_pcie[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0_v1,
&rtw89_mac_size.ple_size0_v1, &rtw89_mac_size.wde_qt0_v1,
@ -68,7 +188,47 @@ static const struct rtw89_dle_mem rtw8922a_dle_mem_pcie[] = {
&rtw89_mac_size.wde_qt0_v1, &rtw89_mac_size.ple_qt0,
&rtw89_mac_size.ple_qt1, &rtw89_mac_size.ple_rsvd_qt0,
&rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4_v1,
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size3_v1,
&rtw89_mac_size.ple_size3_v1, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt9,
&rtw89_mac_size.ple_qt9, &rtw89_mac_size.ple_rsvd_qt1,
&rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
NULL},
};
static const struct rtw89_dle_mem rtw8922a_dle_mem_usb2[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7_v1,
&rtw89_mac_size.ple_size6_v1, &rtw89_mac_size.wde_qt7_v1,
&rtw89_mac_size.wde_qt7_v1, &rtw89_mac_size.ple_qt12_v1,
&rtw89_mac_size.ple_qt13_v1, &rtw89_mac_size.ple_rsvd_qt2,
&rtw89_mac_size.rsvd0_size5, &rtw89_mac_size.rsvd1_size0},
[RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size8_v1,
&rtw89_mac_size.ple_size7_v1, &rtw89_mac_size.wde_qt8_v1,
&rtw89_mac_size.wde_qt8_v1, &rtw89_mac_size.ple_qt14_v1,
&rtw89_mac_size.ple_qt15_v1, &rtw89_mac_size.ple_rsvd_qt2,
&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size0},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size3_v1,
&rtw89_mac_size.ple_size3_v1, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt9,
&rtw89_mac_size.ple_qt9, &rtw89_mac_size.ple_rsvd_qt1,
&rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
NULL},
};
static const struct rtw89_dle_mem rtw8922a_dle_mem_usb3[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size4_v1,
&rtw89_mac_size.ple_size4_v1, &rtw89_mac_size.wde_qt4_v1,
&rtw89_mac_size.wde_qt4_v1, &rtw89_mac_size.ple_qt6_v1,
&rtw89_mac_size.ple_qt7_v1, &rtw89_mac_size.ple_rsvd_qt2,
&rtw89_mac_size.rsvd0_size3, &rtw89_mac_size.rsvd1_size0},
[RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size5_v1,
&rtw89_mac_size.ple_size4_v1, &rtw89_mac_size.wde_qt5_v1,
&rtw89_mac_size.wde_qt5_v1, &rtw89_mac_size.ple_qt8_v1,
&rtw89_mac_size.ple_qt9_v1, &rtw89_mac_size.ple_rsvd_qt2,
&rtw89_mac_size.rsvd0_size3, &rtw89_mac_size.rsvd1_size0},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size3_v1,
&rtw89_mac_size.ple_size3_v1, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt9,
&rtw89_mac_size.ple_qt9, &rtw89_mac_size.ple_rsvd_qt1,
@ -223,6 +383,54 @@ static const struct rtw89_edcca_regs rtw8922a_edcca_regs = {
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_BE_M,
};
static const struct rtw89_pmac_regs rtw8922a_pmac_regs = {
.cck_txon = {R_CNT_CCKTXON_V1, B_CNT_CCKTXON},
.cck_txen = {R_CNT_CCKTXEN_V1, B_CNT_CCKTXEN},
.cck_cca = {R_CNT_CCK_CCA_P0_V1, B_CNT_CCK_CCA_P0},
.cck_sfd_gg = {R_SFD_GG_CNT_V2, B_SFD_GG_CNT},
.cck_sig_gg = {R_SIG_GG_CNT_V2, B_SIG_GG_CNT_V1},
.cck_spoofing = {R_SPOOF_CNT_V2, B_SPOOF_CNT_V1},
.cck_brk = {R_BRK_CNT_V1, B_BRK_CNT},
.brk = {R_CNT_BRK_V1, B_CNT_BRK},
.brk_option = {},
.search_fail = {R_CNT_SEARCH_FAIL_V1, B_CNT_SEARCH_FAIL},
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH_V1, B_CNT_LSIG_BRK_S_TH},
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH_V1, B_CNT_LSIG_BRK_L_TH},
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY_V1, B_CNT_RXL_ERR_PARITY},
.rxl_err_rate = {R_CNT_RXL_ERR_RATE_V1, B_CNT_RXL_ERR_RATE},
.ofdm_cca = {R_CNT_OFDM_CCA_V1, B_CNT_OFDM_CCA},
.cca_spoofing = {R_CNT_CCA_SPOOFING_V1, B_CNT_CCA_SPOOFING},
.ampdu_miss = {R_CNT_AMPDU_MISS_V1, B_CNT_AMPDU_MISS},
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_BE, B_R1B_RX_RPT_RST_V1},
.r1b_rr_sel = {},
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
.cck_crc32 = R_CNT_CCK_CRC32_P0_V1,
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
.ofdm_txon = R_CNT_OFDMTXON_V1,
.ofdm_txon_mask = B_CNT_OFDMTXON,
.ofdm_txen_mask = B_CNT_OFDMTXEN,
.l_crc = R_CNT_L_CRC_V1,
.l_crc_ok_mask = B_CNT_L_CRC_OK,
.l_crc_err_mask = B_CNT_L_CRC_ERR,
.ht_crc = R_CNT_HT_CRC_V1,
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
.vht_crc = R_CNT_VHT_CRC_V1,
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
.he_crc = R_CNT_HE_CRC_V1,
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
.eht_crc = R_CNT_EHT_CRC,
.eht_crc_ok_mask = B_CNT_EHT_CRC_OK,
.eht_crc_err_mask = B_CNT_EHT_CRC_ERR,
.ampdu_crc = R_CNT_AMPDU_RX_CRC32_V1,
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
};
static const struct rtw89_efuse_block_cfg rtw8922a_efuse_blocks[] = {
[RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
[RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
@ -298,17 +506,24 @@ static int rtw8922a_pwr_on_func(struct rtw89_dev *rtwdev)
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_R_SYM_ISO_ADDA_P02PP |
B_BE_R_SYM_ISO_ADDA_P12PP);
rtw89_write8_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_PLATFORM_EN);
rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_HAXIDMA_IO_ST,
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
if (ret)
return ret;
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
if (ret)
return ret;
ret = read_poll_timeout(rtw89_read32, val32,
val32 & B_BE_HAXIDMA_IO_ST,
1000, 3000000, false, rtwdev,
R_BE_HCI_OPT_CTRL);
if (ret)
return ret;
ret = read_poll_timeout(rtw89_read32, val32,
!(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
1000, 3000000, false, rtwdev,
R_BE_HCI_OPT_CTRL);
if (ret)
return ret;
}
rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
@ -317,7 +532,9 @@ static int rtw8922a_pwr_on_func(struct rtw89_dev *rtwdev)
if (ret)
return ret;
rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN);
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL,
B_BE_PCIE_FORCE_IBX_EN);
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0x02);
if (ret)
@ -371,6 +588,10 @@ static int rtw8922a_pwr_on_func(struct rtw89_dev *rtwdev)
if (ret)
return ret;
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
if (ret)
return ret;
if (hal->cv != CHIP_CAV) {
rtw89_write32_set(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_ISO_EB2CORE);
@ -382,14 +603,16 @@ static int rtw8922a_pwr_on_func(struct rtw89_dev *rtwdev)
rtw89_write32_clr(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
}
rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN | B_BE_MPDU_PROC_EN |
B_BE_WD_RLS_EN | B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN | B_BE_PKT_BUF_EN |
B_BE_DMAC_TBL_EN | B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
B_BE_DISPATCHER_EN | B_BE_BBRPT_EN | B_BE_MAC_SEC_EN |
B_BE_H_AXIDMA_EN | B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN | B_BE_LTR_CTL_EN);
val32 = B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN | B_BE_MPDU_PROC_EN |
B_BE_WD_RLS_EN | B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN | B_BE_PKT_BUF_EN |
B_BE_DMAC_TBL_EN | B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
B_BE_DISPATCHER_EN | B_BE_BBRPT_EN | B_BE_MAC_SEC_EN |
B_BE_H_AXIDMA_EN | B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN;
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
val32 |= B_BE_LTR_CTL_EN;
rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN, val32);
set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
@ -465,17 +688,23 @@ static int rtw8922a_pwr_off_func(struct rtw89_dev *rtwdev)
if (ret)
return ret;
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_IO_ST),
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
if (ret)
return ret;
ret = read_poll_timeout(rtw89_read32, val32,
!(val32 & B_BE_HAXIDMA_IO_ST),
1000, 3000000, false, rtwdev,
R_BE_HCI_OPT_CTRL);
if (ret)
return ret;
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
if (ret)
return ret;
ret = read_poll_timeout(rtw89_read32, val32,
!(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
1000, 3000000, false, rtwdev,
R_BE_HCI_OPT_CTRL);
if (ret)
return ret;
}
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
@ -491,9 +720,22 @@ static int rtw8922a_pwr_off_func(struct rtw89_dev *rtwdev)
if (ret)
return ret;
rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2);
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2);
else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_SOP_EASWR);
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
} else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) {
val32 = rtw89_read32(rtwdev, R_BE_SYS_PW_CTRL);
val32 |= B_BE_AFSM_WLSUS_EN;
val32 &= ~B_BE_AFSM_PCIE_SUS_EN;
rtw89_write32(rtwdev, R_BE_SYS_PW_CTRL, val32);
}
rtw89_write32(rtwdev, R_BE_UDM1, 0);
return 0;
@ -1860,7 +2102,7 @@ static void rtw8922a_digital_pwr_comp(struct rtw89_dev *rtwdev,
static int rtw8922a_ctrl_mlo(struct rtw89_dev *rtwdev, enum rtw89_mlo_dbcc_mode mode)
{
const struct rtw89_chan *chan0, *chan1;
struct rtw89_entity_conf conf;
if (mode == MLO_1_PLUS_1_1RF || mode == DBCC_LEGACY) {
rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x1);
@ -1873,19 +2115,10 @@ static int rtw8922a_ctrl_mlo(struct rtw89_dev *rtwdev, enum rtw89_mlo_dbcc_mode
return -EOPNOTSUPP;
}
if (mode == MLO_1_PLUS_1_1RF) {
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
} else if (mode == MLO_0_PLUS_2_1RF) {
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
chan0 = chan1;
} else {
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
chan1 = chan0;
}
rtw89_entity_get_conf(rtwdev, &conf);
rtw8922a_ctrl_afe_dac(rtwdev, chan0->band_width, RF_PATH_A);
rtw8922a_ctrl_afe_dac(rtwdev, chan1->band_width, RF_PATH_B);
rtw8922a_ctrl_afe_dac(rtwdev, conf.chans[0]->band_width, RF_PATH_A);
rtw8922a_ctrl_afe_dac(rtwdev, conf.chans[1]->band_width, RF_PATH_B);
rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180);
@ -2853,6 +3086,7 @@ static const struct rtw89_chip_ops rtw8922a_chip_ops = {
.read_efuse = rtw8922a_read_efuse,
.read_phycap = rtw8922a_read_phycap,
.fem_setup = NULL,
.data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = rtw8922a_rfk_hw_init,
.rfk_init = rtw8922a_rfk_init,
@ -2935,8 +3169,16 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.max_rx_agg_num = 64,
.dis_2g_40m_ul_ofdma = false,
.rsvd_ple_ofst = 0x8f800,
.hfc_param_ini = {rtw8922a_hfc_param_ini_pcie, NULL, NULL},
.dle_mem = {rtw8922a_dle_mem_pcie, NULL, NULL, NULL},
.qta_def = {
.hfc_param_ini = {rtw8922a_hfc_param_ini_pcie,
rtw8922a_hfc_param_ini_usb2,
rtw8922a_hfc_param_ini_usb3,
NULL},
.dle_mem = {rtw8922a_dle_mem_pcie,
rtw8922a_dle_mem_usb2,
rtw8922a_dle_mem_usb3,
NULL},
},
.wde_qempty_acq_grpnum = 4,
.wde_qempty_mgq_grpsel = 4,
.rf_base_addr = {0xe000, 0xf000},
@ -2973,6 +3215,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.support_tas = true,
.support_sar_by_ant = true,
.support_noise = false,
.support_fw_cmd_ofld = false,
.ul_tb_waveform_ctrl = false,
.ul_tb_pwr_diff = false,
.rx_freq_from_ie = false,
@ -3053,6 +3296,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.btc_sb = {{{R_BE_SCOREBOARD, R_BE_SCOREBOARD},}},
.dma_ch_mask = 0,
.edcca_regs = &rtw8922a_edcca_regs,
.pmac_regs = &rtw8922a_pmac_regs,
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8922a,
#endif
@ -3065,6 +3309,7 @@ const struct rtw89_chip_variant rtw8922ae_vs_variant = {
.no_mcs_12_13 = true,
.fw_min_ver_code = RTW89_FW_VER_CODE(0, 35, 54, 0),
.fw_def_override = NULL,
.qta_def_override = NULL,
};
EXPORT_SYMBOL(rtw8922ae_vs_variant);

22
drivers/net/wireless/realtek/rtw89/rtw8922a_rfk.c
View File

@ -278,27 +278,13 @@ static u8 rtw8922a_chlk_reload_sel_tbl(struct rtw89_dev *rtwdev,
static void rtw8922a_chlk_reload(struct rtw89_dev *rtwdev)
{
const struct rtw89_chan *chan0, *chan1;
struct rtw89_entity_conf conf;
u8 s0_tbl, s1_tbl;
switch (rtwdev->mlo_dbcc_mode) {
default:
case MLO_2_PLUS_0_1RF:
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
chan1 = chan0;
break;
case MLO_0_PLUS_2_1RF:
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
chan0 = chan1;
break;
case MLO_1_PLUS_1_1RF:
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
break;
}
rtw89_entity_get_conf(rtwdev, &conf);
s0_tbl = rtw8922a_chlk_reload_sel_tbl(rtwdev, chan0, 0);
s1_tbl = rtw8922a_chlk_reload_sel_tbl(rtwdev, chan1, 1);
s0_tbl = rtw8922a_chlk_reload_sel_tbl(rtwdev, conf.chans[0], 0);
s1_tbl = rtw8922a_chlk_reload_sel_tbl(rtwdev, conf.chans[1], 1);
rtw8922a_chlk_ktbl_sel(rtwdev, RF_A, s0_tbl);
rtw8922a_chlk_ktbl_sel(rtwdev, RF_B, s1_tbl);

2
drivers/net/wireless/realtek/rtw89/rtw8922ae.c
View File

@ -77,6 +77,7 @@ static const struct rtw89_driver_info rtw89_8922ae_info = {
.chip = &rtw8922a_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8922a_pci_info,
},
@ -86,6 +87,7 @@ static const struct rtw89_driver_info rtw89_8922ae_vs_info = {
.chip = &rtw8922a_chip_info,
.variant = &rtw8922ae_vs_variant,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8922a_pci_info,
},

86
drivers/net/wireless/realtek/rtw89/rtw8922au.c Normal file
View File

@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2026 Realtek Corporation
*/
#include <linux/module.h>
#include <linux/usb.h>
#include "rtw8922a.h"
#include "usb.h"
static const struct rtw89_usb_info rtw8922a_usb_info = {
.usb_host_request_2 = 0,
.usb_wlan0_1 = 0,
.hci_func_en = 0,
.usb3_mac_npi_config_intf_0 = 0,
.usb_endpoint_0 = 0,
.usb_endpoint_2 = 0,
.rx_agg_alignment = 16,
.bulkout_id = {
[RTW89_DMA_ACH0] = 3,
[RTW89_DMA_ACH2] = 5,
[RTW89_DMA_ACH4] = 4,
[RTW89_DMA_ACH6] = 6,
[RTW89_DMA_B0MG] = 0,
[RTW89_DMA_B0HI] = 0,
[RTW89_DMA_B1MG] = 1,
[RTW89_DMA_B1HI] = 1,
[RTW89_DMA_H2C] = 2,
},
};
static const struct rtw89_driver_info rtw89_8922au_info = {
.chip = &rtw8922a_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.usb = &rtw8922a_usb_info,
},
};
static const struct usb_device_id rtw_8922au_id_table[] = {
{ USB_DEVICE_AND_INTERFACE_INFO(0x0411, 0x03ef, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x0502, 0x76d7, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4025, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4026, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x1bcf, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x1bd2, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0x8912, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0xda0e, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x332b, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x3625, 0x010a, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x37ad, 0x0100, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x37ad, 0x0101, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x3822, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x4822, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x5822, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8922au_info },
{},
};
MODULE_DEVICE_TABLE(usb, rtw_8922au_id_table);
static struct usb_driver rtw_8922au_driver = {
.name = KBUILD_MODNAME,
.id_table = rtw_8922au_id_table,
.probe = rtw89_usb_probe,
.disconnect = rtw89_usb_disconnect,
};
module_usb_driver(rtw_8922au_driver);
MODULE_AUTHOR("Bitterblue Smith <rtl8821cerfe2@gmail.com>");
MODULE_DESCRIPTION("Realtek 802.11be wireless 8922AU driver");
MODULE_LICENSE("Dual BSD/GPL");

445
drivers/net/wireless/realtek/rtw89/rtw8922d.c
View File

@ -25,6 +25,62 @@
RTW89_GEN_MODULE_FWNAME(RTW8922DS_FW_BASENAME, RTW8922DS_FW_FORMAT_MAX)
static const struct rtw89_hfc_ch_cfg rtw8922d_hfc_chcfg_pcie[] = {
{2, 732, 0}, /* ACH 0 */
{0, 730, 0}, /* ACH 1 */
{2, 732, 0}, /* ACH 2 */
{0, 730, 0}, /* ACH 3 */
{2, 732, 0}, /* ACH 4 */
{0, 730, 0}, /* ACH 5 */
{2, 732, 0}, /* ACH 6 */
{0, 730, 0}, /* ACH 7 */
{2, 732, 0}, /* B0MGQ */
{0, 730, 0}, /* B0HIQ */
{2, 732, 0}, /* B1MGQ */
{0, 730, 0}, /* B1HIQ */
{0, 0, 0}, /* GCQ */
};
static const struct rtw89_hfc_pub_cfg rtw8922d_hfc_pubcfg_pcie = {
742, /* Group 0 */
0, /* Group 1 */
742, /* Public Max */
0, /* WP threshold */
};
static const struct rtw89_hfc_param_ini rtw8922d_hfc_param_ini_pcie[] = {
[RTW89_QTA_SCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
[RTW89_QTA_DBCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
RTW89_HCIFC_POH},
[RTW89_QTA_INVALID] = {NULL},
};
static const struct rtw89_dle_mem rtw8922d_dle_mem_pcie[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size22_v1,
&rtw89_mac_size.ple_size29_v1, &rtw89_mac_size.wde_qt23_v1,
&rtw89_mac_size.wde_qt23_v1, &rtw89_mac_size.ple_qt64_v2,
&rtw89_mac_size.ple_qt65_v2, &rtw89_mac_size.ple_rsvd_qt9,
&rtw89_mac_size.rsvd0_size17, &rtw89_mac_size.rsvd1_size3,
&rtw89_mac_size.dle_input28},
[RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size22_v1,
&rtw89_mac_size.ple_size29_v1, &rtw89_mac_size.wde_qt23_v1,
&rtw89_mac_size.wde_qt23_v1, &rtw89_mac_size.ple_qt64_v2,
&rtw89_mac_size.ple_qt65_v2, &rtw89_mac_size.ple_rsvd_qt9,
&rtw89_mac_size.rsvd0_size17, &rtw89_mac_size.rsvd1_size3,
&rtw89_mac_size.dle_input28},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18_v1,
&rtw89_mac_size.ple_size22_v1, &rtw89_mac_size.wde_qt3,
&rtw89_mac_size.wde_qt3, &rtw89_mac_size.ple_qt5_v2,
&rtw89_mac_size.ple_qt47_v2, &rtw89_mac_size.ple_rsvd_qt1,
&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
&rtw89_mac_size.dle_input3},
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
NULL},
};
static const struct rtw89_hfc_ch_cfg rtw8922ds_hfc_chcfg_pcie[] = {
{2, 603, 0}, /* ACH 0 */
{0, 601, 0}, /* ACH 1 */
{2, 603, 0}, /* ACH 2 */
@ -37,45 +93,43 @@ static const struct rtw89_hfc_ch_cfg rtw8922d_hfc_chcfg_pcie[] = {
{0, 601, 0}, /* B0HIQ */
{2, 603, 0}, /* B1MGQ */
{0, 601, 0}, /* B1HIQ */
{0, 0, 0}, /* FWCMDQ */
{0, 0, 0}, /* BMC */
{0, 0, 0}, /* H2D */
{0, 0, 0}, /* GCQ */
};
static const struct rtw89_hfc_pub_cfg rtw8922d_hfc_pubcfg_pcie = {
static const struct rtw89_hfc_pub_cfg rtw8922ds_hfc_pubcfg_pcie = {
613, /* Group 0 */
0, /* Group 1 */
613, /* Public Max */
0, /* WP threshold */
};
static const struct rtw89_hfc_param_ini rtw8922d_hfc_param_ini_pcie[] = {
[RTW89_QTA_SCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
static const struct rtw89_hfc_param_ini rtw8922ds_hfc_param_ini_pcie[] = {
[RTW89_QTA_SCC] = {rtw8922ds_hfc_chcfg_pcie, &rtw8922ds_hfc_pubcfg_pcie,
&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
[RTW89_QTA_DBCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
[RTW89_QTA_DBCC] = {rtw8922ds_hfc_chcfg_pcie, &rtw8922ds_hfc_pubcfg_pcie,
&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
RTW89_HCIFC_POH},
[RTW89_QTA_INVALID] = {NULL},
};
static const struct rtw89_dle_mem rtw8922d_dle_mem_pcie[] = {
static const struct rtw89_dle_mem rtw8922ds_dle_mem_pcie[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size16_v1,
&rtw89_mac_size.ple_size20_v1, &rtw89_mac_size.wde_qt19_v1,
&rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt42_v2,
&rtw89_mac_size.ple_qt43_v2, &rtw89_mac_size.ple_rsvd_qt9,
&rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt44_v2,
&rtw89_mac_size.ple_qt45_v2, &rtw89_mac_size.ple_rsvd_qt9,
&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
&rtw89_mac_size.dle_input18},
&rtw89_mac_size.dle_input20},
[RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size16_v1,
&rtw89_mac_size.ple_size20_v1, &rtw89_mac_size.wde_qt19_v1,
&rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt42_v2,
&rtw89_mac_size.ple_qt43_v2, &rtw89_mac_size.ple_rsvd_qt9,
&rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt44_v2,
&rtw89_mac_size.ple_qt45_v2, &rtw89_mac_size.ple_rsvd_qt9,
&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
&rtw89_mac_size.dle_input18},
&rtw89_mac_size.dle_input20},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18_v1,
&rtw89_mac_size.ple_size22_v1, &rtw89_mac_size.wde_qt3,
&rtw89_mac_size.wde_qt3, &rtw89_mac_size.ple_qt5_v2,
&rtw89_mac_size.ple_qt5_v2, &rtw89_mac_size.ple_rsvd_qt1,
&rtw89_mac_size.ple_qt47_v2, &rtw89_mac_size.ple_rsvd_qt1,
&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
&rtw89_mac_size.dle_input3},
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
@ -227,6 +281,54 @@ static const struct rtw89_edcca_regs rtw8922d_edcca_regs = {
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_BE_M,
};
static const struct rtw89_pmac_regs rtw8922d_pmac_regs = {
.cck_txon = {R_CNT_CCKTXON_BE4, B_CNT_CCKTXON},
.cck_txen = {R_CNT_CCKTXEN_BE4, B_CNT_CCKTXEN},
.cck_cca = {R_CNT_CCK_CCA_BE4, B_CNT_CCK_CCA_BE4},
.cck_sfd_gg = {R_SFD_GG_CNT_BE4, B_SFD_GG_CNT},
.cck_sig_gg = {R_SIG_GG_CNT_BE4, B_SIG_GG_CNT_V1},
.cck_spoofing = {R_SPOOF_CNT_BE4, B_SPOOF_CNT_V1},
.cck_brk = {R_BRK_CNT_BE4, B_BRK_CNT},
.brk = {R_CNT_BRK_BE4, B_CNT_BRK},
.brk_option = {},
.search_fail = {R_CNT_SEARCH_FAIL_BE4, B_CNT_SEARCH_FAIL},
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH_BE4, B_CNT_LSIG_BRK_S_TH},
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH_BE4, B_CNT_LSIG_BRK_L_TH},
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY_BE4, B_CNT_RXL_ERR_PARITY},
.rxl_err_rate = {R_CNT_RXL_ERR_RATE_BE4, B_CNT_RXL_ERR_RATE},
.ofdm_cca = {R_CNT_OFDM_CCA_BE4, B_CNT_OFDM_CCA},
.cca_spoofing = {R_CNT_CCA_SPOOFING_BE4, B_CNT_CCA_SPOOFING},
.ampdu_miss = {R_CNT_AMPDU_MISS_BE4, B_CNT_AMPDU_MISS},
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_BE4, B_R1B_RX_RPT_RST_V1},
.r1b_rr_sel = {},
.enable_all_cnt = {R_ENABLE_ALL_CNT_BE4, B_ENABLE_ALL_CNT},
.rst_all_cnt = {R_RST_ALL_CNT_BE4, B_RST_ALL_CNT},
.cck_crc32 = R_CNT_CCK_CRC32_BE4,
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_BE4,
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_BE4,
.ofdm_txon = R_CNT_OFDMTXON_BE4,
.ofdm_txon_mask = B_CNT_OFDMTXON,
.ofdm_txen_mask = B_CNT_OFDMTXEN,
.l_crc = R_CNT_L_CRC_BE4,
.l_crc_ok_mask = B_CNT_L_CRC_OK,
.l_crc_err_mask = B_CNT_L_CRC_ERR,
.ht_crc = R_CNT_HT_CRC_BE4,
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
.vht_crc = R_CNT_VHT_CRC_BE4,
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
.he_crc = R_CNT_HE_CRC_BE4,
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
.eht_crc = R_CNT_EHT_CRC_BE4,
.eht_crc_ok_mask = B_CNT_EHT_CRC_OK,
.eht_crc_err_mask = B_CNT_EHT_CRC_ERR,
.ampdu_crc = R_CNT_AMPDU_RX_CRC32_BE4,
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
};
static const struct rtw89_efuse_block_cfg rtw8922d_efuse_blocks[] = {
[RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
[RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
@ -238,6 +340,135 @@ static const struct rtw89_efuse_block_cfg rtw8922d_efuse_blocks[] = {
[RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
};
static const struct rtw89_bb_wrap_common_data rtw8922d_bb_wrap_common_data_7025 = {
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_ENABLE, CIM3K_ENABLE},
.rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
_8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
.pb_tb = 3,
},
[RFSI_CTRL_BAND_2GHZ] = {
.cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_ENABLE, CIM3K_ENABLE},
.rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
_8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
.pb_tb = 0,
}},
.qam_th = {RFSI_BPSK, RFSI_QPSK, RFSI_256QAM, RFSI_MAX, RFSI_MAX, RFSI_MAX},
};
static const struct rtw89_bb_wrap_common_data rtw8922d_bb_wrap_common_data_7090 = {
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_DISABLE, CIM3K_ENABLE},
.rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
_8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
.pb_tb = 3,
},
[RFSI_CTRL_BAND_2GHZ] = {
.cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_DISABLE, CIM3K_ENABLE},
.rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
_8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
.pb_tb = 0,
}},
.qam_th = {RFSI_BPSK, RFSI_QPSK, RFSI_256QAM, RFSI_MAX, RFSI_MAX, RFSI_MAX},
};
static const
struct rtw89_bb_wrap_common_data_gen3 rtw8922d_bb_wrap_common_data_gen3_7090 = {
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.qam_th = {RFSI_QPSK, RFSI_BPSK, RFSI_256QAM, RFSI_MAX,
RFSI_MAX, RFSI_MAX},
},
[RFSI_CTRL_BAND_2GHZ] = {
.qam_th = {RFSI_MAX, RFSI_MAX, RFSI_256QAM, RFSI_MAX,
RFSI_MAX, RFSI_MAX},
}},
.cck_val = {CFIR_OFF, FILTER_A_OFF},
};
static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7025_default = {
.common = &rtw8922d_bb_wrap_common_data_7025,
.common_gen3 = NULL,
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.qam_comp_th0 = {0x4000, 0x6400, 0x6500, 0x6000, 0, 0, 0, 0, 0, 0},
.qam_comp_th1 = {_10qam_comp_code(0x4000, 0x6400, 0x6500, 0x6000,
0, 0, 0, 0, 0, 0)},
.qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0x4000,
0, 0, 0, 0, 0, 0)},
.qam_comp_ow = {0x4000, 0x4400, 0x4400, 0x4000, 0, 0, 0, 0, 0, 0},
.oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
},
[RFSI_CTRL_BAND_2GHZ] = {
.qam_comp_th0 = {0x4000, 0x4400, 0x4500, 0, 0, 0, 0, 0, 0, 0},
.qam_comp_th1 = {_10qam_comp_code(0x4000, 0x4400, 0x4500, 0,
0, 0, 0, 0, 0, 0)},
.qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0,
0, 0, 0, 0, 0, 0)},
.qam_comp_ow = {0x4000, 0x4400, 0x4400, 0, 0, 0, 0, 0, 0, 0},
.oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
}},
.mdpd_by_dbw = {MDPD_ON, MDPD_ON, MDPD_ON, MDPD_ON},
};
static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_default = {
.common = &rtw8922d_bb_wrap_common_data_7090,
.common_gen3 = &rtw8922d_bb_wrap_common_data_gen3_7090,
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.qam_comp_th0 = {0x4000, 0x6420, 0x6520, 0x6000, 0, 0, 0, 0, 0, 0},
.qam_comp_th1 = {_10qam_comp_code(0x4000, 0x6400, 0x6500, 0x6000,
0, 0, 0, 0, 0, 0)},
.qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0x4000,
0, 0, 0, 0, 0, 0)},
.qam_comp_ow = {0x4000, 0x4000, 0x4000, 0x4000, 0, 0, 0, 0, 0, 0},
.oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
},
[RFSI_CTRL_BAND_2GHZ] = {
.qam_comp_th0 = {0x4000, 0x4400, 0x4500, 0, 0, 0, 0, 0, 0, 0},
.qam_comp_th1 = {_10qam_comp_code(0x4000, 0x4400, 0x4500, 0, 0,
0, 0, 0, 0, 0)},
.qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0, 0,
0, 0, 0, 0, 0)},
.qam_comp_ow = {0x4000, 0x4000, 0x4000, 0, 0, 0, 0, 0, 0, 0},
.oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
}},
.mdpd_by_dbw = {MDPD_OFF, MDPD_OFF, MDPD_ON, MDPD_ON},
};
static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_rfe35_41_44 = {
.common = &rtw8922d_bb_wrap_common_data_7090,
.common_gen3 = &rtw8922d_bb_wrap_common_data_gen3_7090,
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.qam_comp_th0 = {0x4000, 0x6420, 0x6520, 0x6000, 0, 0, 0, 0, 0, 0},
.qam_comp_th1 = {_10qam_comp_code(0x4000, 0x6400, 0x6500, 0x6000,
0, 0, 0, 0, 0, 0)},
.qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0x4000,
0, 0, 0, 0, 0, 0)},
.qam_comp_ow = {0x4000, 0x4000, 0x4000, 0x4000, 0, 0, 0, 0, 0, 0},
.oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
},
[RFSI_CTRL_BAND_2GHZ] = {
.qam_comp_th0 = {0x4000, 0x4400, 0x4500, 0, 0, 0, 0, 0, 0, 0},
.qam_comp_th1 = {_10qam_comp_code(0x4000, 0x4400, 0x4500, 0, 0,
0, 0, 0, 0, 0)},
.qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0, 0,
0, 0, 0, 0, 0)},
.qam_comp_ow = {0x4000, 0x4000, 0x4000, 0, 0, 0, 0, 0, 0, 0},
.oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
}},
.mdpd_by_dbw = {MDPD_OFF, MDPD_OFF, MDPD_ON, MDPD_ON},
};
static void rtw8922d_sel_bt_rx_path(struct rtw89_dev *rtwdev, u8 val,
enum rtw89_rf_path rx_path)
{
@ -870,6 +1101,34 @@ static void rtw8922d_power_trim(struct rtw89_dev *rtwdev)
rtw8922d_pad_bias_trim(rtwdev);
}
static int rtw8922d_data_setup(struct rtw89_dev *rtwdev)
{
const struct rtw89_bb_wrap_data *data;
struct rtw89_hal *hal = &rtwdev->hal;
bool rfe35_41_44 = false;
switch (rtwdev->efuse.rfe_type) {
case 35:
case 41:
case 44:
rfe35_41_44 = true;
break;
}
if (hal->cid == RTL8922D_CID7025) {
data = &rtw8922d_bb_wrap_data_7025_default;
} else {
if (rfe35_41_44)
data = &rtw8922d_bb_wrap_data_7090_rfe35_41_44;
else
data = &rtw8922d_bb_wrap_data_7090_default;
}
rtwdev->phy_info.bb_wrap_data = data;
return 0;
}
static void rtw8922d_set_channel_mac(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
u8 mac_idx)
@ -1913,29 +2172,52 @@ static void rtw8922d_set_digital_pwr_comp(struct rtw89_dev *rtwdev,
enum rtw89_rf_path path,
enum rtw89_phy_idx phy_idx)
{
#define DIGITAL_PWR_COMP_REG_NUM 22
#define DIGITAL_PWR_COMP_BASE_NUM 7
#define DIGITAL_PWR_COMP_VALS_NUM 15
static const u32 pw_comp_cr[2] = {R_RX_PATH0_TBL0_BE4, R_RX_PATH1_TBL0_BE4};
const __le32 (*pwr_comp_val)[2][RTW89_TX_COMP_BAND_NR]
[BB_PATH_NUM_8922D][DIGITAL_PWR_COMP_REG_NUM];
const struct {
struct {
__le32 base[DIGITAL_PWR_COMP_BASE_NUM];
__le32 vals[DIGITAL_PWR_COMP_VALS_NUM];
} sets[2][RTW89_TX_COMP_BAND_NR][BB_PATH_NUM_8922D];
} *pwr_comp_v0;
const struct {
__le32 base[DIGITAL_PWR_COMP_BASE_NUM];
struct {
__le32 vals[DIGITAL_PWR_COMP_VALS_NUM];
} sets[2][RTW89_TX_COMP_BAND_NR][BB_PATH_NUM_8922D];
} *pwr_comp;
struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
const struct rtw89_fw_element_hdr *txcomp_elm = elm_info->tx_comp;
const __le32 *digital_pwr_comp;
const __le32 (*comp_base)[DIGITAL_PWR_COMP_BASE_NUM];
const __le32 (*comp_vals)[DIGITAL_PWR_COMP_VALS_NUM];
u32 addr, val;
u32 i;
if (sizeof(*pwr_comp_val) != le32_to_cpu(txcomp_elm->size)) {
if (sizeof(*pwr_comp) == le32_to_cpu(txcomp_elm->size)) {
pwr_comp = (const void *)txcomp_elm->u.common.contents;
comp_base = &pwr_comp->base;
comp_vals = &pwr_comp->sets[nss][chan->tx_comp_band][path].vals;
} else if (sizeof(*pwr_comp_v0) == le32_to_cpu(txcomp_elm->size)) {
pwr_comp_v0 = (const void *)txcomp_elm->u.common.contents;
comp_base = &pwr_comp_v0->sets[nss][chan->tx_comp_band][path].base;
comp_vals = &pwr_comp_v0->sets[nss][chan->tx_comp_band][path].vals;
} else {
rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
"incorrect power comp size %d\n",
le32_to_cpu(txcomp_elm->size));
return;
}
pwr_comp_val = (const void *)txcomp_elm->u.common.contents;
digital_pwr_comp = (*pwr_comp_val)[nss][chan->tx_comp_band][path];
addr = pw_comp_cr[path];
for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) {
val = le32_to_cpu(digital_pwr_comp[i]);
for (i = 0; i < ARRAY_SIZE(*comp_base); i++, addr += 4) {
val = le32_to_cpu((*comp_base)[i]);
rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
}
for (i = 0; i < ARRAY_SIZE(*comp_vals); i++, addr += 4) {
val = le32_to_cpu((*comp_vals)[i]);
rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
}
}
@ -1943,10 +2225,19 @@ static void rtw8922d_set_digital_pwr_comp(struct rtw89_dev *rtwdev,
static void rtw8922d_digital_pwr_comp(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx)
{
const struct rtw89_chan *chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
const struct rtw89_chan *chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
const struct rtw89_chan *chan0, *chan1;
struct rtw89_entity_conf conf;
if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
rtw89_entity_get_conf(rtwdev, &conf);
chan0 = conf.chans[0];
chan1 = conf.chans[1];
if (conf.en_emlsr) {
rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 1, RF_PATH_A, RTW89_PHY_0);
rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 1, RF_PATH_B, RTW89_PHY_0);
rtw8922d_set_digital_pwr_comp(rtwdev, chan1, 1, RF_PATH_A, RTW89_PHY_1);
rtw8922d_set_digital_pwr_comp(rtwdev, chan1, 1, RF_PATH_B, RTW89_PHY_1);
} else if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 0, RF_PATH_A, RTW89_PHY_0);
rtw8922d_set_digital_pwr_comp(rtwdev, chan1, 0, RF_PATH_B, RTW89_PHY_1);
} else {
@ -1958,7 +2249,6 @@ static void rtw8922d_digital_pwr_comp(struct rtw89_dev *rtwdev,
static int rtw8922d_ctrl_mlo(struct rtw89_dev *rtwdev, enum rtw89_mlo_dbcc_mode mode,
bool pwr_comp)
{
const struct rtw89_chan *chan1;
u32 reg0, reg1;
u8 cck_phy_idx;
@ -2016,8 +2306,10 @@ static int rtw8922d_ctrl_mlo(struct rtw89_dev *rtwdev, enum rtw89_mlo_dbcc_mode
rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0);
rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0);
} else if ((mode == MLO_1_PLUS_1_1RF) || (mode == DBCC_LEGACY)) {
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
cck_phy_idx = chan1->band_type == RTW89_BAND_2G ?
struct rtw89_entity_conf conf;
rtw89_entity_get_conf(rtwdev, &conf);
cck_phy_idx = conf.chans[1]->band_type == RTW89_BAND_2G ?
RTW89_PHY_1 : RTW89_PHY_0;
rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
@ -2086,7 +2378,7 @@ static void rtw8922d_set_channel_bb(struct rtw89_dev *rtwdev,
u8 pri_sb = chan->pri_sb_idx;
u32 val;
rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, phy_idx);
rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, chan->rfsi_band, phy_idx);
rtw8922d_ctrl_ch(rtwdev, chan, phy_idx);
rtw8922d_ctrl_bw(rtwdev, pri_sb, chan->band_width, phy_idx);
rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx);
@ -2322,12 +2614,16 @@ static void rtw8922d_rfk_tssi(struct rtw89_dev *rtwdev,
static void rtw8922d_rfk_channel(struct rtw89_dev *rtwdev,
struct rtw89_vif_link *rtwvif_link)
{
struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif_link->rtwvif);
enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB, chanctx_idx);
u32 tx_en;
if (ieee80211_vif_is_mld(vif))
rtw8922d_chlk_ktbl_ctl_mld(rtwdev, phy_idx, true);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_START);
rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
_wait_rx_mode(rtwdev, RF_AB);
@ -2343,6 +2639,9 @@ static void rtw8922d_rfk_channel(struct rtw89_dev *rtwdev,
rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_STOP);
if (ieee80211_vif_is_mld(vif))
rtw8922d_chlk_ktbl_ctl_mld(rtwdev, phy_idx, false);
}
static void rtw8922d_rfk_band_changed(struct rtw89_dev *rtwdev,
@ -2435,6 +2734,66 @@ static void rtw8922d_set_txpwr_ref(struct rtw89_dev *rtwdev,
B_BE_PWR_REF_CTRL_CCK, ref_cck);
}
static void rtw8922d_set_tx_shape(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
const struct rtw89_tx_shape *tx_shape = &rfe_parms->tx_shape;
u8 tx_shape_idx;
u8 band, regd;
const u16 *th;
band = chan->band_type;
regd = rtw89_regd_get(rtwdev, band);
tx_shape_idx = (*tx_shape->lmt)[band][RTW89_RS_OFDM][regd];
if (tx_shape_idx == 0)
goto disable;
th = d->bands[chan->rfsi_band].qam_comp_th0;
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, th[0], phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKHWORD, th[1], phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, th[2], phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKHWORD, th[3], phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, th[4], phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKHWORD, th[5], phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, th[6], phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKHWORD, th[7], phy_idx);
th = d->bands[chan->rfsi_band].qam_comp_ow;
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, th[0], phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKHWORD, th[1], phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, th[2], phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKHWORD, th[3], phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, th[4], phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKHWORD, th[5], phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, th[6], phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKHWORD, th[7], phy_idx);
return;
disable:
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, B_OW_VAL_TRIANGULAR_L, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, B_OW_VAL_TRIANGULAR_H, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, B_OW_VAL_TRIANGULAR_L, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, B_OW_VAL_TRIANGULAR_H, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, B_OW_VAL_TRIANGULAR_L, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, B_OW_VAL_TRIANGULAR_H, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, B_OW_VAL_TRIANGULAR_L, 0, phy_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, B_OW_VAL_TRIANGULAR_H, 0, phy_idx);
}
static void rtw8922d_set_txpwr_sar_diff(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
@ -2466,6 +2825,7 @@ static void rtw8922d_set_txpwr(struct rtw89_dev *rtwdev,
{
rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
rtw8922d_set_tx_shape(rtwdev, chan, phy_idx);
rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
rtw8922d_set_txpwr_ref(rtwdev, chan, phy_idx);
@ -2475,9 +2835,11 @@ static void rtw8922d_set_txpwr(struct rtw89_dev *rtwdev,
static void rtw8922d_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx)
{
const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, phy_idx);
struct rtw89_entity_conf conf;
rtw8922d_set_txpwr_ref(rtwdev, chan, phy_idx);
rtw89_entity_get_conf(rtwdev, &conf);
rtw8922d_set_txpwr_ref(rtwdev, conf.chans[phy_idx], phy_idx);
}
static void rtw8922d_ctrl_trx_path(struct rtw89_dev *rtwdev,
@ -2866,6 +3228,7 @@ static const struct rtw89_chip_ops rtw8922d_chip_ops = {
.read_efuse = rtw8922d_read_efuse,
.read_phycap = rtw8922d_read_phycap,
.fem_setup = NULL,
.data_setup = rtw8922d_data_setup,
.rfe_gpio = NULL,
.rfk_hw_init = rtw8922d_rfk_hw_init,
.rfk_init = rtw8922d_rfk_init,
@ -2948,8 +3311,10 @@ const struct rtw89_chip_info rtw8922d_chip_info = {
.max_rx_agg_num = 256,
.dis_2g_40m_ul_ofdma = false,
.rsvd_ple_ofst = 0x5f800,
.hfc_param_ini = {rtw8922d_hfc_param_ini_pcie, NULL, NULL},
.dle_mem = {rtw8922d_dle_mem_pcie, NULL, NULL, NULL},
.qta_def = {
.hfc_param_ini = {rtw8922d_hfc_param_ini_pcie, NULL, NULL, NULL},
.dle_mem = {rtw8922d_dle_mem_pcie, NULL, NULL, NULL},
},
.wde_qempty_acq_grpnum = 8,
.wde_qempty_mgq_grpsel = 8,
.rf_base_addr = {0x3e000, 0x3f000},
@ -2986,9 +3351,10 @@ const struct rtw89_chip_info rtw8922d_chip_info = {
.support_tas = false,
.support_sar_by_ant = true,
.support_noise = false,
.support_fw_cmd_ofld = false,
.ul_tb_waveform_ctrl = false,
.ul_tb_pwr_diff = false,
.rx_freq_frome_ie = false,
.rx_freq_from_ie = false,
.hw_sec_hdr = true,
.hw_mgmt_tx_encrypt = true,
.hw_tkip_crypto = true,
@ -3065,6 +3431,7 @@ const struct rtw89_chip_info rtw8922d_chip_info = {
BIT(RTW89_DMA_ACH5) | BIT(RTW89_DMA_ACH7) |
BIT(RTW89_DMA_B0HI) | BIT(RTW89_DMA_B1HI),
.edcca_regs = &rtw8922d_edcca_regs,
.pmac_regs = &rtw8922d_pmac_regs,
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8922d,
#endif
@ -3079,10 +3446,16 @@ static const struct rtw89_fw_def rtw8922de_vs_fw_def = {
.fw_b_aid = RTL8922D_AID7060,
};
static const struct rtw89_qta_def rtw8922ds_qta_def = {
.hfc_param_ini = {rtw8922ds_hfc_param_ini_pcie, NULL, NULL},
.dle_mem = {rtw8922ds_dle_mem_pcie, NULL, NULL, NULL},
};
const struct rtw89_chip_variant rtw8922de_vs_variant = {
.no_mcs_12_13 = true,
.fw_min_ver_code = RTW89_FW_VER_CODE(0, 0, 0, 0),
.fw_def_override = &rtw8922de_vs_fw_def,
.qta_def_override = &rtw8922ds_qta_def,
};
EXPORT_SYMBOL(rtw8922de_vs_variant);

92
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.c
View File

@ -105,26 +105,60 @@ static void rtw8922d_set_syn01(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn)
}
}
static void rtw8922d_chlk_ktbl_sel(struct rtw89_dev *rtwdev, u8 kpath, u8 idx)
void rtw8922d_chlk_ktbl_ctl_mld(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool manual)
{
bool mlo_linking = false;
if (manual) {
struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
u8 path = phy_idx; /* numerical equal for target */
u8 idx = rfk_mcc[path].table_idx;
if (idx > 2) {
rtw89_warn(rtwdev, "[DBCC][ERROR]indx is out of limit!! index(%d)", idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_RST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_RST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_IDX0, idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_IDX1, idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_IDX0, idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_IDX1, idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL1A_BE4, B_KTBL1_TBL0, idx & BIT(0));
rtw89_phy_write32_mask(rtwdev, R_KTBL1A_BE4, B_KTBL1_TBL1, (idx & BIT(1)) >> 1);
rtw89_phy_write32_mask(rtwdev, R_KTBL1B_BE4, B_KTBL1_TBL0, idx & BIT(0));
rtw89_phy_write32_mask(rtwdev, R_KTBL1B_BE4, B_KTBL1_TBL1, (idx & BIT(1)) >> 1);
return;
}
if (mlo_linking) {
if (kpath & RF_A) {
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_SW_SEL, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_SW_SEL, 0x0);
}
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_RST, 0x0);
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_RST, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_SW_SEL, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_SW_SEL, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_SW_SEL, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_SW_SEL, 0x0);
}
if (kpath & RF_B) {
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_SW_SEL, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_SW_SEL, 0x0);
}
static void rtw8922d_chlk_ktbl_sel_mld(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx, u8 idx)
{
if (phy_idx == RTW89_PHY_0) {
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_MLD_IDX0, idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_MLD_IDX0, idx);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_TBL_SEL_IDX0, idx);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_TBL_SEL_IDX0, idx);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_TBL_SEL_IDX0, idx);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_TBL_SEL_IDX0, idx);
} else if (phy_idx == RTW89_PHY_1) {
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_MLD_IDX1, idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_MLD_IDX1, idx);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_TBL_SEL_IDX1, idx);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_TBL_SEL_IDX1, idx);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_TBL_SEL_IDX1, idx);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_TBL_SEL_IDX1, idx);
}
rtw8922d_chlk_ktbl_ctl_mld(rtwdev, phy_idx, false);
}
static void rtw8922d_chlk_ktbl_sel(struct rtw89_dev *rtwdev, u8 kpath, u8 idx)
{
if (idx > 2) {
rtw89_warn(rtwdev, "[DBCC][ERROR]indx is out of limit!! index(%d)", idx);
return;
}
@ -187,30 +221,26 @@ static u8 rtw8922d_chlk_reload_sel_tbl(struct rtw89_dev *rtwdev,
static void rtw8922d_chlk_reload(struct rtw89_dev *rtwdev)
{
const struct rtw89_chan *chan0, *chan1;
struct rtw89_entity_conf conf;
u8 s0_tbl, s1_tbl;
switch (rtwdev->mlo_dbcc_mode) {
default:
case MLO_2_PLUS_0_1RF:
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
chan1 = chan0;
break;
case MLO_0_PLUS_2_1RF:
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
chan0 = chan1;
break;
case MLO_1_PLUS_1_1RF:
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
break;
}
rtw89_entity_get_conf(rtwdev, &conf);
s0_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, chan0, 0);
s1_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, chan1, 1);
s0_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, conf.chans[0], 0);
s1_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, conf.chans[1], 1);
if (conf.is_mld)
goto mld;
rtw8922d_chlk_ktbl_sel(rtwdev, RF_A, s0_tbl);
rtw8922d_chlk_ktbl_sel(rtwdev, RF_B, s1_tbl);
return;
mld:
if (test_bit(RTW89_PHY_0, conf.hw_bitmap))
rtw8922d_chlk_ktbl_sel_mld(rtwdev, RTW89_PHY_0, s0_tbl);
if (test_bit(RTW89_PHY_1, conf.hw_bitmap))
rtw8922d_chlk_ktbl_sel_mld(rtwdev, RTW89_PHY_1, s1_tbl);
}
static enum _rf_syn_pow rtw8922d_get_syn_pow(struct rtw89_dev *rtwdev)

1
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.h
View File

@ -18,5 +18,6 @@ void rtw8922d_rfk_mlo_ctrl(struct rtw89_dev *rtwdev);
void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8922d_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8922d_lck_track(struct rtw89_dev *rtwdev);
void rtw8922d_chlk_ktbl_ctl_mld(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool manual);
#endif

2
drivers/net/wireless/realtek/rtw89/rtw8922de.c
View File

@ -73,6 +73,7 @@ static const struct rtw89_driver_info rtw89_8922de_vs_info = {
.chip = &rtw8922d_chip_info,
.variant = &rtw8922de_vs_variant,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8922d_pci_info,
},
@ -82,6 +83,7 @@ static const struct rtw89_driver_info rtw89_8922de_info = {
.chip = &rtw8922d_chip_info,
.variant = NULL,
.quirks = NULL,
.dev_id_quirks = 0,
.bus = {
.pci = &rtw8922d_pci_info,
},

4
drivers/net/wireless/realtek/rtw89/sar.c
View File

@ -693,6 +693,7 @@ static bool rtw89_tas_rolling_average(struct rtw89_dev *rtwdev)
static void rtw89_tas_init(struct rtw89_dev *rtwdev)
{
bool skip_acpi_dsm = rtwdev->hci.type == RTW89_HCI_TYPE_USB;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_tas_info *tas = &rtwdev->tas;
const struct rtw89_acpi_policy_tas *ptr;
@ -702,6 +703,9 @@ static void rtw89_tas_init(struct rtw89_dev *rtwdev)
if (!chip->support_tas)
return;
if (skip_acpi_dsm)
return;
ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_TAS_EN, &res);
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_SAR,

110
drivers/net/wireless/realtek/rtw89/txrx.h
View File

@ -634,8 +634,10 @@ struct rtw89_phy_sts_ie01 {
#define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0)
#define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8)
#define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16)
#define RTW89_PHY_STS_IE01_W2_SU BIT(27)
#define RTW89_PHY_STS_IE01_W2_LDPC BIT(28)
#define RTW89_PHY_STS_IE01_W2_STBC BIT(30)
#define RTW89_PHY_STS_IE01_W3_BF BIT(8)
struct rtw89_phy_sts_ie01_v2 {
__le32 w0;
@ -656,6 +658,114 @@ struct rtw89_phy_sts_ie01_v2 {
#define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C GENMASK(11, 4)
#define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D GENMASK(23, 16)
union rtw89_phy_sts_ie09 {
struct {
__le64 qw0;
} gen0;
struct {
__le64 qw0;
__le64 qw1;
} gen2;
} __packed;
#define RTW89_PHY_STS_IE09_L_SIG_MASK GENMASK(21, 5) /* Legacy/VHT/HE L-SIG */
#define RTW89_PHY_STS_IE09_L_SIG_MASK_GEN2 GENMASK(31, 15) /* Legacy/VHT/HE L-SIG for GEN2 */
#define RTW89_PHY_STS_IE09_L_SIG_RATE GENMASK(3, 0)
#define RTW89_PHY_STS_IE09_L_SIG_RSVD BIT(4)
#define RTW89_PHY_STS_IE09_L_SIG_LENGTH GENMASK(16, 5)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_MASK GENMASK_ULL(45, 22) /* VHT SIG-A1 */
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_MASK_GEN2 GENMASK_ULL(55, 32) /* VHT SIG-A1 for GEN2 */
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_BW GENMASK(1, 0)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_RSVD1 BIT(2)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_STBC BIT(3)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_GRP_ID GENMASK(9, 4)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_SU_NSTS GENMASK(12, 10)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_SU_PAID GENMASK(21, 13)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS0 GENMASK(12, 10)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS1 GENMASK(15, 13)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS2 GENMASK(18, 16)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS3 GENMASK(21, 19)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_TXOP_NOPS BIT(22)
#define RTW89_PHY_STS_IE09_VHT_SIG_A1_RSVD2 BIT(23)
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_MASK GENMASK_ULL(55, 46) /* VHT SIG-A2 */
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_MASK_GEN2_L0 GENMASK_ULL(63, 56) /* VHT SIG-A2 for GEN2 */
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_MASK_GEN2_H8 GENMASK_ULL(1, 0) /* VHT SIG-A2 for GEN2 */
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_SGI BIT(0)
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_SGI_DISA BIT(1)
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_SUMU_CODE0 BIT(2)
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_LDPC BIT(3)
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_SUMU_CODE3 GENMASK(7, 4)
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_BF BIT(8)
#define RTW89_PHY_STS_IE09_VHT_SIG_A2_RSVD3 BIT(9)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MASK GENMASK_ULL(47, 22) /* HE SU SIG-A1 */
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MASK_GEN2 GENMASK_ULL(57, 32) /* HE SU SIG-A1 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_FORMAT BIT(0)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_BEAM_CHANGE BIT(1)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_ULDL BIT(2)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MCS GENMASK(6, 3)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_DCM BIT(7)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_BSS_COLOR GENMASK(13, 8)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_RSVD1 BIT(14)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_SR GENMASK(18, 15)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_BW GENMASK(20, 19)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_GILTF GENMASK(22, 21)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_NSTS GENMASK(25, 23)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK GENMASK_ULL(63, 48) /* HE SU SIG-A2 */
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK_GEN2_L0 GENMASK_ULL(63, 58) /* HE SU SIG-A2 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK_GEN2_H6 GENMASK_ULL(9, 0) /* HE SU SIG-A2 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_TXOP GENMASK(6, 0)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_CODING BIT(7)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_LDPC_XSYMSEG BIT(8)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_STBC BIT(9)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_BEAMFORMED BIT(10)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_PREFEC GENMASK(12, 11)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_PE BIT(13)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_RSVD2 BIT(14)
#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_DOPPLER BIT(15)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_MASK GENMASK_ULL(47, 22) /* HE TB SIG-A1 */
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_MASK_GEN2 GENMASK_ULL(57, 32) /* HE TB SIG-A1 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_FORMAT BIT(0)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_BSS_COLOR GENMASK(6, 1)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB1 GENMASK(10, 7)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB2 GENMASK(14, 11)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB3 GENMASK(18, 15)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB4 GENMASK(22, 19)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_RSVD1 BIT(23)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_BW GENMASK(25, 24)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK GENMASK_ULL(63, 48) /* HE TB SIG-A2 */
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK_GEN2_L0 GENMASK_ULL(63, 58) /* HE TB SIG-A2 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK_GEN2_H6 GENMASK_ULL(9, 0) /* HE TB SIG-A2 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A2_TXOP GENMASK(6, 0)
#define RTW89_PHY_STS_IE09_HE_TB_SIG_A2_RSVD1 GENMASK(15, 7)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_MASK GENMASK_ULL(47, 22) /* HE MU SIG-A1 */
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_MASK_GEN2 GENMASK_ULL(57, 32) /* HE MU SIG-A1 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_ULDL BIT(0)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_MCS GENMASK(3, 1)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_DCM BIT(4)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_BSS_COLOR GENMASK(10, 5)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SR GENMASK(14, 11)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_BW GENMASK(17, 15)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_SYM_USR GENMASK(21, 18)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_COM BIT(22)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_GI_LTF GENMASK(24, 23)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_DOPPLER BIT(25)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK GENMASK_ULL(63, 48) /* HE MU SIG-A2 */
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK_GEN2_L0 GENMASK_ULL(63, 58) /* HE MU SIG-A2 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK_GEN2_H6 GENMASK_ULL(9, 0) /* HE MU SIG-A2 for GEN2 */
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_TXOP GENMASK(6, 0)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_RSVD BIT(7)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_LTF_MID GENMASK(10, 8)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MID BIT(10)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_LPDC_XSYMSEG BIT(11)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_STBC BIT(12)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_FEC GENMASK(14, 13)
#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_PE BIT(15)
struct rtw89_phy_sts_ie10 {
__le64 qw0;
u8 sigb[];
} __packed;
enum rtw89_tx_channel {
RTW89_TXCH_ACH0 = 0,
RTW89_TXCH_ACH1 = 1,

199
drivers/net/wireless/realtek/rtw89/usb.c
View File

@ -11,8 +11,8 @@
static void rtw89_usb_read_port_complete(struct urb *urb);
static void rtw89_usb_vendorreq(struct rtw89_dev *rtwdev, u32 addr,
void *data, u16 len, u8 reqtype)
static void __rtw89_usb_vendorreq(struct rtw89_dev *rtwdev, u32 addr,
void *data, u16 len, u8 reqtype, bool warn)
{
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
struct usb_device *udev = rtwusb->udev;
@ -52,7 +52,7 @@ static void rtw89_usb_vendorreq(struct rtw89_dev *rtwdev, u32 addr,
if (ret == -ESHUTDOWN || ret == -ENODEV)
set_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags);
else if (ret < 0)
else if (ret < 0 && warn)
rtw89_warn(rtwdev,
"usb %s%u 0x%x fail ret=%d value=0x%x attempt=%d\n",
str_read_write(reqtype == RTW89_USB_VENQT_READ),
@ -69,6 +69,12 @@ static void rtw89_usb_vendorreq(struct rtw89_dev *rtwdev, u32 addr,
}
}
static void rtw89_usb_vendorreq(struct rtw89_dev *rtwdev, u32 addr,
void *data, u16 len, u8 reqtype)
{
__rtw89_usb_vendorreq(rtwdev, addr, data, len, reqtype, true);
}
static u32 rtw89_usb_read_cmac(struct rtw89_dev *rtwdev, u32 addr)
{
u32 addr32, val32, shift;
@ -157,6 +163,14 @@ static void rtw89_usb_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 val)
rtw89_usb_vendorreq(rtwdev, addr, &data, 4, RTW89_USB_VENQT_WRITE);
}
static void rtw89_usb_write32_quiet(struct rtw89_dev *rtwdev, u32 addr, u32 val)
{
__le32 data = cpu_to_le32(val);
__rtw89_usb_vendorreq(rtwdev, addr, &data, 4,
RTW89_USB_VENQT_WRITE, false);
}
static u32
rtw89_usb_ops_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev,
u8 txch)
@ -511,7 +525,7 @@ static void rtw89_usb_rx_resubmit(struct rtw89_usb *rtwusb,
rxcb->rx_skb = rx_skb;
usb_fill_bulk_urb(rxcb->rx_urb, rtwusb->udev,
usb_rcvbulkpipe(rtwusb->udev, rtwusb->in_pipe),
usb_rcvbulkpipe(rtwusb->udev, rtwusb->in_pipe[0]),
rxcb->rx_skb->data, RTW89_USB_RECVBUF_SZ,
rtw89_usb_read_port_complete, rxcb);
@ -756,6 +770,9 @@ static int rtw89_usb_ops_mac_pre_init(struct rtw89_dev *rtwdev)
const struct rtw89_usb_info *info = rtwusb->info;
u32 val32;
if (rtwdev->chip->chip_id == RTL8922A)
return 0;
rtw89_write32_set(rtwdev, info->usb_host_request_2,
B_AX_R_USBIO_MODE);
@ -800,6 +817,17 @@ static void rtw89_usb_rx_agg_cfg_v2(struct rtw89_dev *rtwdev)
rtw89_write32(rtwdev, R_AX_RXAGG_1_V1, 0x1F);
}
static void rtw89_usb_rx_agg_cfg_v3(struct rtw89_dev *rtwdev)
{
const u32 rxagg_0 = FIELD_PREP_CONST(B_BE_RXAGG_0_EN, 1) |
FIELD_PREP_CONST(B_BE_RXAGG_0_NUM_TH, 255) |
FIELD_PREP_CONST(B_BE_RXAGG_0_TIME_32US_TH, 32) |
FIELD_PREP_CONST(B_BE_RXAGG_0_BUF_SZ_1K, 20);
rtw89_write32(rtwdev, R_BE_RXAGG_0_V1, rxagg_0);
rtw89_write32(rtwdev, R_BE_RXAGG_1_V1, 0x1F);
}
static void rtw89_usb_rx_agg_cfg(struct rtw89_dev *rtwdev)
{
switch (rtwdev->chip->chip_id) {
@ -811,6 +839,9 @@ static void rtw89_usb_rx_agg_cfg(struct rtw89_dev *rtwdev)
case RTL8852C:
rtw89_usb_rx_agg_cfg_v2(rtwdev);
break;
case RTL8922A:
rtw89_usb_rx_agg_cfg_v3(rtwdev);
break;
default:
rtw89_warn(rtwdev, "%s: USB RX agg not support\n", __func__);
return;
@ -824,6 +855,9 @@ static int rtw89_usb_ops_mac_post_init(struct rtw89_dev *rtwdev)
enum usb_device_speed speed;
u32 ep;
if (rtwdev->chip->chip_id == RTL8922A)
goto rx_agg_cfg;
rtw89_write32_clr(rtwdev, info->usb3_mac_npi_config_intf_0,
B_AX_SSPHY_LFPS_FILTER);
@ -845,6 +879,7 @@ static int rtw89_usb_ops_mac_post_init(struct rtw89_dev *rtwdev)
rtw89_write8(rtwdev, info->usb_endpoint_2 + 1, NUMP);
}
rx_agg_cfg:
rtw89_usb_rx_agg_cfg(rtwdev);
return 0;
@ -871,6 +906,10 @@ static int rtw89_usb_ops_mac_lv1_rcvy(struct rtw89_dev *rtwdev,
reg = R_AX_USB_WLAN0_1_V1;
mask = B_AX_USBRX_RST_V1 | B_AX_USBTX_RST_V1;
break;
case RTL8922A:
reg = R_BE_USB2_WLAN_TRX_OPT_PAR2;
mask = B_BE_USB2_USBRX_RST | B_BE_USB2_USBTX_RST;
break;
default:
rtw89_err(rtwdev, "%s: fix me\n", __func__);
return -EOPNOTSUPP;
@ -948,6 +987,7 @@ static int rtw89_usb_parse(struct rtw89_dev *rtwdev,
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
struct usb_endpoint_descriptor *endpoint;
int num_out_pipes = 0;
int num_in_pipes = 0;
u8 num;
int i;
@ -963,13 +1003,14 @@ static int rtw89_usb_parse(struct rtw89_dev *rtwdev,
if (usb_endpoint_dir_in(endpoint) &&
usb_endpoint_xfer_bulk(endpoint)) {
if (rtwusb->in_pipe) {
if (num_in_pipes >= RTW89_MAX_BULKIN_NUM) {
rtw89_err(rtwdev,
"found more than 1 bulk in endpoint\n");
"found more than %d bulk in endpoint\n",
RTW89_MAX_BULKIN_NUM);
return -EINVAL;
}
rtwusb->in_pipe = num;
rtwusb->in_pipe[num_in_pipes++] = num;
}
if (usb_endpoint_dir_out(endpoint) &&
@ -985,6 +1026,11 @@ static int rtw89_usb_parse(struct rtw89_dev *rtwdev,
}
}
if (num_in_pipes < 1) {
rtw89_err(rtwdev, "no bulk in endpoints found\n");
return -EINVAL;
}
if (num_out_pipes < 1) {
rtw89_err(rtwdev, "no bulk out endpoints found\n");
return -EINVAL;
@ -1027,6 +1073,133 @@ static void rtw89_usb_intf_deinit(struct rtw89_dev *rtwdev,
usb_set_intfdata(intf, NULL);
}
static int rtw89_usb_switch_mode_ax(struct rtw89_dev *rtwdev)
{
u32 pad_ctrl2;
/* No known USB 3 devices with this chip. */
if (rtwdev->chip->chip_id == RTL8851B)
return 0;
pad_ctrl2 = rtw89_usb_ops_read32(rtwdev, R_AX_PAD_CTRL2);
rtw89_debug(rtwdev, RTW89_DBG_HCI, "%s: pad_ctrl2: %#x\n",
__func__, pad_ctrl2);
/* Already tried to switch but it's a USB 2 port. */
if (u32_get_bits(pad_ctrl2, B_AX_MATCH_CNT) == USB_SWITCH_DELAY)
return 0;
/* Add delay to prevent some platforms would not detect USB switch */
u32p_replace_bits(&pad_ctrl2, USB_SWITCH_DELAY, B_AX_MATCH_CNT);
pad_ctrl2 &= ~(B_AX_FORCE_U3_CK | B_AX_USB2_FORCE |
B_AX_USB3_FORCE | B_AX_USB3_USB2_TRANSITION);
u32p_replace_bits(&pad_ctrl2, USB_MODE_U3, B_AX_USB23_SW_MODE_V1);
pad_ctrl2 |= B_AX_NO_PDN_CHIPOFF_V1 | B_AX_RSM_EN_V1;
rtw89_usb_write32_quiet(rtwdev, R_AX_PAD_CTRL2, pad_ctrl2);
return 1;
}
static int rtw89_usb_switch_mode_be(struct rtw89_dev *rtwdev)
{
u32 pad_ctrl2;
pad_ctrl2 = rtw89_usb_ops_read32(rtwdev, R_BE_PAD_CTRL2);
rtw89_debug(rtwdev, RTW89_DBG_HCI, "%s: pad_ctrl2: %#x\n",
__func__, pad_ctrl2);
/* Already tried to switch but it's a USB 2 port. */
if (u32_get_bits(pad_ctrl2, B_BE_MATCH_CNT) == USB_SWITCH_DELAY)
return 0;
/* Add delay to prevent some platforms would not detect USB switch */
u32p_replace_bits(&pad_ctrl2, USB_SWITCH_DELAY, B_BE_MATCH_CNT);
pad_ctrl2 |= B_BE_RSM_EN_V1 | B_BE_NO_PDN_CHIPOFF_V1 |
B_BE_USB_AUTO_INSTALL_MASK | B_BE_USB23_SW_MODE;
pad_ctrl2 &= ~(B_BE_USB3_FORCE | B_BE_USB2_FORCE |
B_BE_FORCE_U3_CK | B_BE_FORCE_U2_CK |
B_BE_FORCE_CLK_U2 | B_BE_USB3_GEN_MODE |
B_BE_USB3_LANE_MODE);
rtw89_usb_write32_quiet(rtwdev, R_BE_PAD_CTRL2, pad_ctrl2);
return 1;
}
static int rtw89_usb_switch_mode(struct rtw89_dev *rtwdev)
{
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
if (rtwusb->udev->speed == USB_SPEED_SUPER) {
rtw89_info(rtwdev,
"2.4 GHz performance may be better in a USB 2 port\n");
return 0;
}
if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
return rtw89_usb_switch_mode_ax(rtwdev);
return rtw89_usb_switch_mode_be(rtwdev);
}
static ssize_t serial_number_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct wiphy *wiphy = container_of(dev, struct wiphy, dev);
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
struct rtw89_dev *rtwdev = hw->priv;
struct rtw89_efuse *efuse = &rtwdev->efuse;
return sysfs_emit(buf, "%*phN\n",
(int)sizeof(efuse->sn), efuse->sn);
}
static DEVICE_ATTR_RO(serial_number);
static ssize_t uuid_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct wiphy *wiphy = container_of(dev, struct wiphy, dev);
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
struct rtw89_dev *rtwdev = hw->priv;
struct rtw89_efuse *efuse = &rtwdev->efuse;
return sysfs_emit(buf, "%pUb\n", efuse->uuid);
}
static DEVICE_ATTR_RO(uuid);
static struct attribute *rtw89_usb_attrs[] = {
&dev_attr_serial_number.attr,
&dev_attr_uuid.attr,
NULL,
};
static bool rtw89_usb_group_visible(struct kobject *kobj)
{
struct device *dev = kobj_to_dev(kobj);
struct wiphy *wiphy = container_of(dev, struct wiphy, dev);
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
struct rtw89_dev *rtwdev = hw->priv;
return test_bit(RTW89_QUIRK_HW_INFO_SYSFS, rtwdev->quirks);
}
DEFINE_SIMPLE_SYSFS_GROUP_VISIBLE(rtw89_usb);
static const struct attribute_group rtw89_usb_group = {
.name = "rtw89_usb",
.attrs = rtw89_usb_attrs,
.is_visible = SYSFS_GROUP_VISIBLE(rtw89_usb),
};
__ATTRIBUTE_GROUPS(rtw89_usb);
int rtw89_usb_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
@ -1038,8 +1211,7 @@ int rtw89_usb_probe(struct usb_interface *intf,
info = (const struct rtw89_driver_info *)id->driver_info;
rtwdev = rtw89_alloc_ieee80211_hw(&intf->dev,
sizeof(struct rtw89_usb),
info->chip, info->variant);
sizeof(struct rtw89_usb), info);
if (!rtwdev) {
dev_err(&intf->dev, "failed to allocate hw\n");
return -ENOMEM;
@ -1049,6 +1221,8 @@ int rtw89_usb_probe(struct usb_interface *intf,
rtwusb->rtwdev = rtwdev;
rtwusb->info = info->bus.usb;
rtwdev->hw->wiphy->dev.groups = rtw89_usb_groups;
rtwdev->hci.ops = &rtw89_usb_ops;
rtwdev->hci.type = RTW89_HCI_TYPE_USB;
rtwdev->hci.tx_rpt_enabled = true;
@ -1059,6 +1233,13 @@ int rtw89_usb_probe(struct usb_interface *intf,
goto err_free_hw;
}
ret = rtw89_usb_switch_mode(rtwdev);
if (ret) {
/* Not a fail, but we do need to skip rtw89_core_register. */
ret = 0;
goto err_intf_deinit;
}
if (rtwusb->udev->speed == USB_SPEED_SUPER)
rtwdev->hci.dle_type = RTW89_HCI_DLE_TYPE_USB3;
else

11
drivers/net/wireless/realtek/rtw89/usb.h
View File

@ -18,6 +18,7 @@
#define RTW89_USB_MOD512_PADDING 4
#define RTW89_MAX_ENDPOINT_NUM 9
#define RTW89_MAX_BULKIN_NUM 2
#define RTW89_MAX_BULKOUT_NUM 7
#define R_AX_RXAGG_0_V1 0x6000
@ -28,6 +29,14 @@
#define R_AX_RXAGG_1_V1 0x6004
#define R_BE_RXAGG_0_V1 0x6000
#define B_BE_RXAGG_0_EN BIT(31)
#define B_BE_RXAGG_0_NUM_TH GENMASK(23, 16)
#define B_BE_RXAGG_0_TIME_32US_TH GENMASK(15, 8)
#define B_BE_RXAGG_0_BUF_SZ_1K GENMASK(7, 0)
#define R_BE_RXAGG_1_V1 0x6004
#define R_AX_RXAGG_0 0x8900
#define B_AX_RXAGG_0_BUF_SZ_4K GENMASK(7, 0)
@ -65,7 +74,7 @@ struct rtw89_usb {
atomic_t continual_io_error;
u8 in_pipe;
u8 in_pipe[RTW89_MAX_BULKIN_NUM];
u8 out_pipe[RTW89_MAX_BULKOUT_NUM];
struct workqueue_struct *rxwq;