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drm/rcar-du: dsi: Convert register bits to BIT() macro
Convert register bits to BIT() macro where applicable. This is done automatically using regex 's@(1 << \([0-9]\+\))@BIT(\1)', except for bitfields which are manually updated to use GENMASK(). Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028232959.109936-11-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
This commit is contained in:
Marek Vasut
Tomi Valkeinen
parent
94fe479fae
commit
6ade1742e3
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@ -9,37 +9,37 @@
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#define __RCAR_MIPI_DSI_REGS_H__
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#define LINKSR 0x010
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#define LINKSR_LPBUSY (1 << 1)
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#define LINKSR_HSBUSY (1 << 0)
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#define LINKSR_LPBUSY BIT_U32(1)
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#define LINKSR_HSBUSY BIT_U32(0)
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#define TXSETR 0x100
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#define TXSETR_LANECNT_MASK (0x3 << 0)
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#define TXSETR_LANECNT_MASK GENMASK(1, 0)
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/*
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* DSI Command Transfer Registers
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*/
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#define TXCMSETR 0x110
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#define TXCMSETR_SPDTYP (1 << 8) /* 0:HS 1:LP */
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#define TXCMSETR_LPPDACC (1 << 0)
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#define TXCMSETR_SPDTYP BIT_U32(8) /* 0:HS 1:LP */
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#define TXCMSETR_LPPDACC BIT_U32(0)
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#define TXCMCR 0x120
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#define TXCMCR_BTATYP (1 << 2)
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#define TXCMCR_BTAREQ (1 << 1)
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#define TXCMCR_TXREQ (1 << 0)
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#define TXCMCR_BTATYP BIT_U32(2)
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#define TXCMCR_BTAREQ BIT_U32(1)
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#define TXCMCR_TXREQ BIT_U32(0)
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#define TXCMSR 0x130
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#define TXCMSR_CLSNERR (1 << 18)
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#define TXCMSR_AXIERR (1 << 16)
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#define TXCMSR_TXREQEND (1 << 0)
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#define TXCMSR_CLSNERR BIT_U32(18)
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#define TXCMSR_AXIERR BIT_U32(16)
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#define TXCMSR_TXREQEND BIT_U32(0)
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#define TXCMSCR 0x134
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#define TXCMSCR_CLSNERR (1 << 18)
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#define TXCMSCR_AXIERR (1 << 16)
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#define TXCMSCR_TXREQEND (1 << 0)
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#define TXCMSCR_CLSNERR BIT_U32(18)
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#define TXCMSCR_AXIERR BIT_U32(16)
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#define TXCMSCR_TXREQEND BIT_U32(0)
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#define TXCMIER 0x138
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#define TXCMIER_CLSNERR (1 << 18)
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#define TXCMIER_AXIERR (1 << 16)
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#define TXCMIER_TXREQEND (1 << 0)
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#define TXCMIER_CLSNERR BIT_U32(18)
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#define TXCMIER_AXIERR BIT_U32(16)
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#define TXCMIER_TXREQEND BIT_U32(0)
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#define TXCMADDRSET0R 0x140
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#define TXCMPHDR 0x150
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#define TXCMPHDR_FMT (1 << 24) /* 0:SP 1:LP */
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#define TXCMPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */
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#define TXCMPHDR_VC(n) (((n) & 0x3) << 22)
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#define TXCMPHDR_DT(n) (((n) & 0x3f) << 16)
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#define TXCMPHDR_DATA1(n) (((n) & 0xff) << 8)
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@ -53,63 +53,63 @@
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#define RXSETR_CRCEN(n) (((n) & 0xf) << 24)
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#define RXSETR_ECCEN(n) (((n) & 0xf) << 16)
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#define RXPSETR 0x210
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#define RXPSETR_LPPDACC (1 << 0)
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#define RXPSETR_LPPDACC BIT_U32(0)
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#define RXPSR 0x220
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#define RXPSR_ECCERR1B (1 << 28)
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#define RXPSR_UEXTRGERR (1 << 25)
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#define RXPSR_RESPTOERR (1 << 24)
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#define RXPSR_OVRERR (1 << 23)
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#define RXPSR_AXIERR (1 << 22)
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#define RXPSR_CRCERR (1 << 21)
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#define RXPSR_WCERR (1 << 20)
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#define RXPSR_UEXDTERR (1 << 19)
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#define RXPSR_UEXPKTERR (1 << 18)
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#define RXPSR_ECCERR (1 << 17)
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#define RXPSR_MLFERR (1 << 16)
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#define RXPSR_RCVACK (1 << 14)
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#define RXPSR_RCVEOT (1 << 10)
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#define RXPSR_RCVAKE (1 << 9)
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#define RXPSR_RCVRESP (1 << 8)
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#define RXPSR_BTAREQEND (1 << 0)
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#define RXPSR_ECCERR1B BIT_U32(28)
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#define RXPSR_UEXTRGERR BIT_U32(25)
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#define RXPSR_RESPTOERR BIT_U32(24)
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#define RXPSR_OVRERR BIT_U32(23)
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#define RXPSR_AXIERR BIT_U32(22)
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#define RXPSR_CRCERR BIT_U32(21)
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#define RXPSR_WCERR BIT_U32(20)
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#define RXPSR_UEXDTERR BIT_U32(19)
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#define RXPSR_UEXPKTERR BIT_U32(18)
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#define RXPSR_ECCERR BIT_U32(17)
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#define RXPSR_MLFERR BIT_U32(16)
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#define RXPSR_RCVACK BIT_U32(14)
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#define RXPSR_RCVEOT BIT_U32(10)
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#define RXPSR_RCVAKE BIT_U32(9)
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#define RXPSR_RCVRESP BIT_U32(8)
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#define RXPSR_BTAREQEND BIT_U32(0)
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#define RXPSCR 0x224
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#define RXPSCR_ECCERR1B (1 << 28)
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#define RXPSCR_UEXTRGERR (1 << 25)
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#define RXPSCR_RESPTOERR (1 << 24)
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#define RXPSCR_OVRERR (1 << 23)
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#define RXPSCR_AXIERR (1 << 22)
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#define RXPSCR_CRCERR (1 << 21)
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#define RXPSCR_WCERR (1 << 20)
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#define RXPSCR_UEXDTERR (1 << 19)
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#define RXPSCR_UEXPKTERR (1 << 18)
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#define RXPSCR_ECCERR (1 << 17)
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#define RXPSCR_MLFERR (1 << 16)
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#define RXPSCR_RCVACK (1 << 14)
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#define RXPSCR_RCVEOT (1 << 10)
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#define RXPSCR_RCVAKE (1 << 9)
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#define RXPSCR_RCVRESP (1 << 8)
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#define RXPSCR_BTAREQEND (1 << 0)
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#define RXPSCR_ECCERR1B BIT_U32(28)
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#define RXPSCR_UEXTRGERR BIT_U32(25)
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#define RXPSCR_RESPTOERR BIT_U32(24)
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#define RXPSCR_OVRERR BIT_U32(23)
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#define RXPSCR_AXIERR BIT_U32(22)
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#define RXPSCR_CRCERR BIT_U32(21)
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#define RXPSCR_WCERR BIT_U32(20)
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#define RXPSCR_UEXDTERR BIT_U32(19)
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#define RXPSCR_UEXPKTERR BIT_U32(18)
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#define RXPSCR_ECCERR BIT_U32(17)
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#define RXPSCR_MLFERR BIT_U32(16)
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#define RXPSCR_RCVACK BIT_U32(14)
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#define RXPSCR_RCVEOT BIT_U32(10)
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#define RXPSCR_RCVAKE BIT_U32(9)
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#define RXPSCR_RCVRESP BIT_U32(8)
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#define RXPSCR_BTAREQEND BIT_U32(0)
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#define RXPIER 0x228
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#define RXPIER_ECCERR1B (1 << 28)
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#define RXPIER_UEXTRGERR (1 << 25)
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#define RXPIER_RESPTOERR (1 << 24)
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#define RXPIER_OVRERR (1 << 23)
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#define RXPIER_AXIERR (1 << 22)
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#define RXPIER_CRCERR (1 << 21)
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#define RXPIER_WCERR (1 << 20)
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#define RXPIER_UEXDTERR (1 << 19)
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#define RXPIER_UEXPKTERR (1 << 18)
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#define RXPIER_ECCERR (1 << 17)
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#define RXPIER_MLFERR (1 << 16)
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#define RXPIER_RCVACK (1 << 14)
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#define RXPIER_RCVEOT (1 << 10)
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#define RXPIER_RCVAKE (1 << 9)
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#define RXPIER_RCVRESP (1 << 8)
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#define RXPIER_BTAREQEND (1 << 0)
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#define RXPIER_ECCERR1B BIT_U32(28)
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#define RXPIER_UEXTRGERR BIT_U32(25)
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#define RXPIER_RESPTOERR BIT_U32(24)
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#define RXPIER_OVRERR BIT_U32(23)
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#define RXPIER_AXIERR BIT_U32(22)
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#define RXPIER_CRCERR BIT_U32(21)
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#define RXPIER_WCERR BIT_U32(20)
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#define RXPIER_UEXDTERR BIT_U32(19)
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#define RXPIER_UEXPKTERR BIT_U32(18)
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#define RXPIER_ECCERR BIT_U32(17)
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#define RXPIER_MLFERR BIT_U32(16)
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#define RXPIER_RCVACK BIT_U32(14)
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#define RXPIER_RCVEOT BIT_U32(10)
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#define RXPIER_RCVAKE BIT_U32(9)
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#define RXPIER_RCVRESP BIT_U32(8)
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#define RXPIER_BTAREQEND BIT_U32(0)
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#define RXPADDRSET0R 0x230
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#define RXPSIZESETR 0x238
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#define RXPSIZESETR_SIZE(n) (((n) & 0xf) << 3)
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#define RXPHDR 0x240
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#define RXPHDR_FMT (1 << 24) /* 0:SP 1:LP */
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#define RXPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */
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#define RXPHDR_VC(n) (((n) & 0x3) << 22)
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#define RXPHDR_DT(n) (((n) & 0x3f) << 16)
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#define RXPHDR_DATA1(n) (((n) & 0xff) << 8)
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@ -128,39 +128,39 @@
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#define TASCR 0x514
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#define TAIER 0x518
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#define TOSR 0x610
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#define TOSR_TATO (1 << 2)
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#define TOSR_LRXHTO (1 << 1)
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#define TOSR_HRXTO (1 << 0)
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#define TOSR_TATO BIT_U32(2)
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#define TOSR_LRXHTO BIT_U32(1)
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#define TOSR_HRXTO BIT_U32(0)
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#define TOSCR 0x614
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#define TOSCR_TATO (1 << 2)
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#define TOSCR_LRXHTO (1 << 1)
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#define TOSCR_HRXTO (1 << 0)
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#define TOSCR_TATO BIT_U32(2)
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#define TOSCR_LRXHTO BIT_U32(1)
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#define TOSCR_HRXTO BIT_U32(0)
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/*
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* Video Mode Register
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*/
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#define TXVMSETR 0x180
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#define TXVMSETR_SYNSEQ_EVENTS (1 << 16) /* 0:Pulses 1:Events */
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#define TXVMSETR_VSTPM (1 << 15)
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#define TXVMSETR_PIXWDTH_MASK (7 << 8)
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#define TXVMSETR_PIXWDTH (1 << 8) /* Only allowed value */
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#define TXVMSETR_VSEN (1 << 4)
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#define TXVMSETR_HFPBPEN (1 << 2)
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#define TXVMSETR_HBPBPEN (1 << 1)
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#define TXVMSETR_HSABPEN (1 << 0)
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#define TXVMSETR_SYNSEQ_EVENTS BIT_U32(16) /* 0:Pulses 1:Events */
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#define TXVMSETR_VSTPM BIT_U32(15)
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#define TXVMSETR_PIXWDTH_MASK GENMASK(10, 8)
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#define TXVMSETR_PIXWDTH BIT_U32(8) /* Only allowed value */
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#define TXVMSETR_VSEN BIT_U32(4)
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#define TXVMSETR_HFPBPEN BIT_U32(2)
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#define TXVMSETR_HBPBPEN BIT_U32(1)
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#define TXVMSETR_HSABPEN BIT_U32(0)
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#define TXVMCR 0x190
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#define TXVMCR_VFCLR (1 << 12)
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#define TXVMCR_EN_VIDEO (1 << 0)
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#define TXVMCR_VFCLR BIT_U32(12)
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#define TXVMCR_EN_VIDEO BIT_U32(0)
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#define TXVMSR 0x1a0
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#define TXVMSR_STR (1 << 16)
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#define TXVMSR_VFRDY (1 << 12)
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#define TXVMSR_ACT (1 << 8)
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#define TXVMSR_RDY (1 << 0)
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#define TXVMSR_STR BIT_U32(16)
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#define TXVMSR_VFRDY BIT_U32(12)
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#define TXVMSR_ACT BIT_U32(8)
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#define TXVMSR_RDY BIT_U32(0)
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#define TXVMSCR 0x1a4
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#define TXVMSCR_STR (1 << 16)
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#define TXVMSCR_STR BIT_U32(16)
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#define TXVMPSPHSETR 0x1c0
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#define TXVMPSPHSETR_DT_MASK (0x3f << 16)
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@ -171,10 +171,10 @@
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#define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c)
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#define TXVMVPRMSET0R 0x1d0
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#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) /* 0:High 1:Low */
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#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) /* 0:High 1:Low */
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#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) /* 0:RGB 1:YCbCr */
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#define TXVMVPRMSET0R_BPP_MASK (7 << 0)
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#define TXVMVPRMSET0R_HSPOL_LOW BIT_U32(17) /* 0:High 1:Low */
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#define TXVMVPRMSET0R_VSPOL_LOW BIT_U32(16) /* 0:High 1:Low */
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#define TXVMVPRMSET0R_CSPC_YCbCr BIT_U32(4) /* 0:RGB 1:YCbCr */
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#define TXVMVPRMSET0R_BPP_MASK GENMASK(2, 0)
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#define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0)
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#define TXVMVPRMSET0R_BPP_18 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1)
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#define TXVMVPRMSET0R_BPP_24 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2)
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@ -199,51 +199,51 @@
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* PHY-Protocol Interface (PPI) Registers
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*/
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#define PPISETR 0x700
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#define PPISETR_DLEN_MASK (0xf << 0)
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#define PPISETR_CLEN (1 << 8)
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#define PPISETR_DLEN_MASK GENMASK(3, 0)
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#define PPISETR_CLEN BIT_U32(8)
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#define PPICLCR 0x710
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#define PPICLCR_TXREQHS (1 << 8)
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#define PPICLCR_TXULPSEXT (1 << 1)
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#define PPICLCR_TXULPSCLK (1 << 0)
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#define PPICLCR_TXREQHS BIT_U32(8)
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#define PPICLCR_TXULPSEXT BIT_U32(1)
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#define PPICLCR_TXULPSCLK BIT_U32(0)
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#define PPICLSR 0x720
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#define PPICLSR_HSTOLP (1 << 27)
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#define PPICLSR_TOHS (1 << 26)
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#define PPICLSR_STPST (1 << 0)
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#define PPICLSR_HSTOLP BIT_U32(27)
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#define PPICLSR_TOHS BIT_U32(26)
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#define PPICLSR_STPST BIT_U32(0)
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#define PPICLSCR 0x724
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#define PPICLSCR_HSTOLP (1 << 27)
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#define PPICLSCR_TOHS (1 << 26)
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#define PPICLSCR_HSTOLP BIT_U32(27)
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#define PPICLSCR_TOHS BIT_U32(26)
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#define PPIDL0SR 0x740
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#define PPIDL0SR_DIR (1 << 10)
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#define PPIDL0SR_STPST (1 << 6)
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#define PPIDL0SR_DIR BIT_U32(10)
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#define PPIDL0SR_STPST BIT_U32(6)
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#define PPIDLSR 0x760
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#define PPIDLSR_STPST (0xf << 0)
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#define PPIDLSR_STPST GENMASK(3, 0)
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/*
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* Clocks registers
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*/
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#define LPCLKSET 0x1000
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#define LPCLKSET_CKEN (1 << 8)
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#define LPCLKSET_CKEN BIT_U32(8)
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#define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0)
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#define CFGCLKSET 0x1004
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#define CFGCLKSET_CKEN (1 << 8)
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#define CFGCLKSET_CKEN BIT_U32(8)
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#define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0)
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#define DOTCLKDIV 0x1008
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#define DOTCLKDIV_CKEN (1 << 8)
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#define DOTCLKDIV_CKEN BIT_U32(8)
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#define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0)
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#define VCLKSET 0x100c
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#define VCLKSET_CKEN (1 << 16)
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#define VCLKSET_COLOR_YCC (1 << 8) /* 0:RGB 1:YCbCr */
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#define VCLKSET_CKEN BIT_U32(16)
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#define VCLKSET_COLOR_YCC BIT_U32(8) /* 0:RGB 1:YCbCr */
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#define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4)
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#define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4)
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#define VCLKSET_BPP_MASK (3 << 2)
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#define VCLKSET_BPP_MASK GENMASK(3, 2)
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#define VCLKSET_BPP_16 FIELD_PREP(VCLKSET_BPP_MASK, 0)
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#define VCLKSET_BPP_18 FIELD_PREP(VCLKSET_BPP_MASK, 1)
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#define VCLKSET_BPP_18L FIELD_PREP(VCLKSET_BPP_MASK, 2)
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#define VCLKSET_LANE(x) (((x) & 0x3) << 0)
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#define VCLKEN 0x1010
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#define VCLKEN_CKEN (1 << 0)
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#define VCLKEN_CKEN BIT_U32(0)
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#define PHYSETUP 0x1014
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#define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16)
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#define PHYSETUP_HSFREQRANGE_MASK (0x7f << 16)
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#define PHYSETUP_HSFREQRANGE_MASK GENMASK(22, 16)
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#define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8)
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#define PHYSETUP_SHUTDOWNZ (1 << 1)
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#define PHYSETUP_RSTZ (1 << 0)
|
||||
#define PHYSETUP_SHUTDOWNZ BIT_U32(1)
|
||||
#define PHYSETUP_RSTZ BIT_U32(0)
|
||||
|
||||
#define CLOCKSET1 0x101c
|
||||
#define CLOCKSET1_LOCK_PHY (1 << 17)
|
||||
#define CLOCKSET1_CLKSEL (1 << 8)
|
||||
#define CLOCKSET1_CLKINSEL_MASK (3 << 2)
|
||||
#define CLOCKSET1_LOCK_PHY BIT_U32(17)
|
||||
#define CLOCKSET1_CLKSEL BIT_U32(8)
|
||||
#define CLOCKSET1_CLKINSEL_MASK GENMASK(3, 2)
|
||||
#define CLOCKSET1_CLKINSEL_EXTAL FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 0)
|
||||
#define CLOCKSET1_CLKINSEL_DIG FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 1)
|
||||
#define CLOCKSET1_CLKINSEL_DU FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 2)
|
||||
#define CLOCKSET1_SHADOW_CLEAR (1 << 1)
|
||||
#define CLOCKSET1_UPDATEPLL (1 << 0)
|
||||
#define CLOCKSET1_SHADOW_CLEAR BIT_U32(1)
|
||||
#define CLOCKSET1_UPDATEPLL BIT_U32(0)
|
||||
|
||||
#define CLOCKSET2 0x1020
|
||||
#define CLOCKSET2_M(x) (((x) & 0xfff) << 16)
|
||||
|
|
@ -282,16 +282,16 @@
|
|||
#define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0)
|
||||
|
||||
#define PHTW 0x1034
|
||||
#define PHTW_DWEN (1 << 24)
|
||||
#define PHTW_DWEN BIT_U32(24)
|
||||
#define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16)
|
||||
#define PHTW_CWEN (1 << 8)
|
||||
#define PHTW_CWEN BIT_U32(8)
|
||||
#define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define PHTR 0x1038
|
||||
#define PHTR_TESTDOUT (0xff << 16)
|
||||
#define PHTR_TESTDOUT_TEST (1 << 16)
|
||||
#define PHTR_TESTDOUT GENMASK(23, 16)
|
||||
#define PHTR_TESTDOUT_TEST BIT_U32(16)
|
||||
|
||||
#define PHTC 0x103c
|
||||
#define PHTC_TESTCLR (1 << 0)
|
||||
#define PHTC_TESTCLR BIT_U32(0)
|
||||
|
||||
#endif /* __RCAR_MIPI_DSI_REGS_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user