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Armv8 Juno/FVP updates for v5.20
Just a small bunch of miscellaneous updates: addition of missing cache-level property to L2 caches on Juno, whitespace adjustments and removal of erroneous 'mbox-name' and 'panel-dpi' compatible in the device tree nodes. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmLFVroACgkQAEG6vDF+ 4phMGA/+LPM48FsZSAOyOQdt0fFPLEPcXBn92aRVkDDie2RN5EnlEbBG0fmQZwzJ dIEYlzs4KLxq8Ucj6ThdoVoW/POqPyyZjgzqGf32ltL6xs2KE/OO3Rtb1VSEOnQE s3UvbGZ9qHv0XXx4yRr+06jJZ7Ll7nhKG4HtRL+vs3sGe67aWa05hX/F+l+20XEg /PGhACF5W9do2e901JuUfAAw7vjTtyQFiC/JWGOzlzHqdC2x8+B5cyVvqeyfjdOj vkfo0KaGiLBveszhwENupdpqVY5MmEVGcMyPRFBujSKBTakLvk/RE4eFb7GDd14F f7xdZlgwjLYA5ihmbqwvtLif1F5a/zwvaH8yASN3K1sFMRdP90bOf1Bp9rKpqnBW GW/F40y7QhfraF+3FSSloJj9pGUSkndKjz2yJKeGmMbU036Vjps9M8Zof6IyyEA2 uVRuh2anaBQLipOaY86z+8MXtZ+Hmxt11jDPf6HhKAGjIkvqB8OQtrTB+u9pmMyl FDXehCVPng90P2d/8RYMvqq4yvHnGCdl3y9M1bhANH7yHqTsgFQSUkepZrKTY+hr xTKFeEaAjsMlfOi/6dChXtMGUElgGdUgFRxB2WQKZfetgz2rBGqImJsV/nJl+Fd7 m3/Hxx5dkDvvUApXhffomWiFdoYFmDm1PIZqHhZHEP8KfBNNnPQ= =ZJmi -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLFeBYACgkQmmx57+YA GNl55Q//eRNl4TfNOZHFfnHK4yEfVmiJ3mAqwoeHQog2YelAiT1hCDb9J4dvVwTT V4/JtUFUQuHFJVO0zFGob71XnxhgQzYTyJHbOhAxSHMrjNk20Fy+tJIv0D4AmG+S G15KPEbdSfECg1QkZCDAsPFXJeKzNmGklvtu9mBtod31A2eIaj7GQsFIsOFKfF+y MQUvo+DjE4SOxCZdjAxvSY3hV2fYgzFS5OIzmpI25KDlr/NnGS+6kJKWVEnc+HVT beAAqNbJUeH9Y4dmzYXMCmSQlS/L1peNZxXpJODZxw8zYLEmbDzHYONKLQ+38ASA FHAsbpgdrFPHZFAMDnLhaeBXAxGg3QhMG0ka5aGz3ro0j0nkhQUbf1hdP4roiZIN 7K6B1z8QmyPYGMo5EWsjiM/J4ePRllQrhENW1OKrXADJovVKya2bnNUOZI8VBB8g LKGr6lh0V2mdcoD7jJb33PB2x//10P6Ge+XlJWNxui360p8VzTtweUq4/7Z7tjzJ B3YOFCHB3qza0sqBSUGIE8SHhx4vf2RR31jx3Tael9xfjBpfYGRRQMLbKZEUfFoH bYH2IDyItvrdFazDsEcXcmWnelgY9kelIjv915cPY+Fr/XduVSHcJJ+E+JDGTcuN pGuj6eBR7kzRQjVXfySNxsdQ5TSNq0uw5xBcNM3flrip0AxrWJc= =OxuR -----END PGP SIGNATURE----- Merge tag 'juno-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt Armv8 Juno/FVP updates for v5.20 Just a small bunch of miscellaneous updates: addition of missing cache-level property to L2 caches on Juno, whitespace adjustments and removal of erroneous 'mbox-name' and 'panel-dpi' compatible in the device tree nodes. * tag 'juno-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: Add cache-level property to L2 caches arm64: dts: arm: adjust whitespace around '=' arm64: dts: arm/juno: Drop erroneous 'mbox-name' property arm64: dts: arm/fvp-base-revc: Remove 'panel-dpi' compatible Link: https://lore.kernel.org/r/20220706115026.2272643-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
6a65fc3614
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@ -186,7 +186,7 @@ smmu: iommu@2b400000 {
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};
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panel {
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compatible = "arm,rtsm-display", "panel-dpi";
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compatible = "arm,rtsm-display";
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port {
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panel_in: endpoint {
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remote-endpoint = <&clcd_pads>;
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@ -581,36 +581,36 @@ cti_sys0: cti@20020000 { /* sys_cti_0 */
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trig-conns@0 {
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reg = <0>;
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arm,trig-in-sigs=<2 3>;
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arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
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arm,trig-out-sigs=<0 1>;
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arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
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arm,trig-in-sigs = <2 3>;
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arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
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arm,trig-out-sigs = <0 1>;
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arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
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arm,cs-dev-assoc = <&etr_sys>;
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};
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trig-conns@1 {
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reg = <1>;
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arm,trig-in-sigs=<0 1>;
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arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
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arm,trig-out-sigs=<7 6>;
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arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
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arm,trig-in-sigs = <0 1>;
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arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
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arm,trig-out-sigs = <7 6>;
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arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
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arm,cs-dev-assoc = <&etf_sys0>;
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};
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trig-conns@2 {
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reg = <2>;
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arm,trig-in-sigs=<4 5 6 7>;
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arm,trig-in-types=<STM_TOUT_SPTE STM_TOUT_SW
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arm,trig-in-sigs = <4 5 6 7>;
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arm,trig-in-types = <STM_TOUT_SPTE STM_TOUT_SW
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STM_TOUT_HETE STM_ASYNCOUT>;
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arm,trig-out-sigs=<4 5>;
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arm,trig-out-types=<STM_HWEVENT STM_HWEVENT>;
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arm,trig-out-sigs = <4 5>;
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arm,trig-out-types = <STM_HWEVENT STM_HWEVENT>;
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arm,cs-dev-assoc = <&stm_sys>;
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};
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trig-conns@3 {
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reg = <3>;
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arm,trig-out-sigs=<2 3>;
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arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
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arm,trig-out-sigs = <2 3>;
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arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
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arm,cs-dev-assoc = <&tpiu_sys>;
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};
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};
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@ -628,24 +628,24 @@ cti_sys1: cti@20110000 { /* sys_cti_1 */
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trig-conns@0 {
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reg = <0>;
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arm,trig-in-sigs=<0>;
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arm,trig-in-types=<GEN_INTREQ>;
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arm,trig-out-sigs=<0>;
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arm,trig-out-types=<GEN_HALTREQ>;
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arm,trig-in-sigs = <0>;
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arm,trig-in-types = <GEN_INTREQ>;
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arm,trig-out-sigs = <0>;
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arm,trig-out-types = <GEN_HALTREQ>;
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arm,trig-conn-name = "sys_profiler";
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};
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trig-conns@1 {
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reg = <1>;
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arm,trig-out-sigs=<2 3>;
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arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
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arm,trig-out-sigs = <2 3>;
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arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
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arm,trig-conn-name = "watchdog";
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};
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trig-conns@2 {
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reg = <2>;
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arm,trig-out-sigs=<1 6>;
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arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
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arm,trig-out-sigs = <1 6>;
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arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
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arm,trig-conn-name = "g_counter";
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};
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};
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@ -96,24 +96,24 @@ cti_sys2: cti@20160000 { /* sys_cti_2 */
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trig-conns@0 {
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reg = <0>;
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arm,trig-in-sigs=<0 1>;
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arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
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arm,trig-out-sigs=<0 1>;
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arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
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arm,trig-in-sigs = <0 1>;
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arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
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arm,trig-out-sigs = <0 1>;
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arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
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arm,cs-dev-assoc = <&etf_sys1>;
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};
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trig-conns@1 {
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reg = <1>;
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arm,trig-in-sigs=<2 3 4>;
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arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
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arm,trig-in-sigs = <2 3 4>;
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arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
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arm,trig-conn-name = "ela_clus_0";
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};
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trig-conns@2 {
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reg = <2>;
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arm,trig-in-sigs=<5 6 7>;
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arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
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arm,trig-in-sigs = <5 6 7>;
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arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
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arm,trig-conn-name = "ela_clus_1";
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};
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};
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@ -192,6 +192,7 @@ A57_L2: l2-cache0 {
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-level = <2>;
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};
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A53_L2: l2-cache1 {
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@ -199,6 +200,7 @@ A53_L2: l2-cache1 {
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <2>;
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};
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};
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@ -198,6 +198,7 @@ A72_L2: l2-cache0 {
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-level = <2>;
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};
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A53_L2: l2-cache1 {
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@ -205,6 +206,7 @@ A53_L2: l2-cache1 {
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <2>;
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};
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};
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@ -187,7 +187,6 @@ &gpu {
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&mailbox {
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compatible = "arm,mhu-doorbell", "arm,primecell";
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#mbox-cells = <2>;
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mbox-name = "ARM-MHU";
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};
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&smmu_etr {
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@ -197,6 +197,7 @@ A57_L2: l2-cache0 {
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-level = <2>;
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};
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A53_L2: l2-cache1 {
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@ -204,6 +205,7 @@ A53_L2: l2-cache1 {
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <2>;
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};
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};
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