From 63b35a29d7ad2cafb0076f8b002b30fb74df053a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:21 +0100 Subject: [PATCH 001/131] dt-bindings: net: bluetooth: qualcomm: Fix WCN6855 regulator names Commit 5f4f954bba12 ("dt-bindings: bluetooth: bring the HW description closer to reality for wcn6855") changed the vddrfa1p7-supply to 1p8 for whatever reason. The schematics footprint for this chip definitely says 7 on the input leg and the driver still expects 1p7. Bring it back. Fixes: 5f4f954bba12 ("dt-bindings: bluetooth: bring the HW description closer to reality for wcn6855") Reviewed-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-1-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml index 45630067d3c8..0beda26ae8bb 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml @@ -50,9 +50,6 @@ properties: description: VDD_RFA_1P7 supply regulator handle deprecated: true - vddrfa1p8-supply: - description: VDD_RFA_1P8 supply regulator handle - vddrfacmn-supply: description: VDD_RFA_CMN supply regulator handle @@ -68,7 +65,7 @@ required: - vddbtcmx-supply - vddrfa0p8-supply - vddrfa1p2-supply - - vddrfa1p8-supply + - vddrfa1p7-supply - vddrfacmn-supply - vddwlcx-supply - vddwlmx-supply @@ -91,7 +88,7 @@ examples: vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; From 493cb869874cd301c370adf9a3f9577942c4f0f1 Mon Sep 17 00:00:00 2001 From: Yedaya Katsman Date: Sat, 14 Mar 2026 23:46:23 +0200 Subject: [PATCH 002/131] arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Enable MDSS and add panel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the MDSS nodes and add supplies and bindings for the Samsung S6E8FCO DSI controller for the M1906F9 panel. The ldo and iovcc gpio pins boot up with a current of 16 mA, but they work fine with 2mA, so I used that. mdss_dsi0_phy is powered by VDD_MX, see power-domains in sm6125.dtsi Co-developed-by: Kamil Gołda Signed-off-by: Kamil Gołda Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Yedaya Katsman Link: https://lore.kernel.org/r/20260314-panel-patches-v4-3-1ecbb2c0c3c8@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index 97f64cb5d570..b9d9439e230b 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -95,6 +95,33 @@ ts_vdd_supply: regulator-ts-vdd { pinctrl-names = "default"; }; + panel_vdd_1p8: regulator-panel-vdd { + compatible = "regulator-fixed"; + regulator-name = "panel_vdd_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + vin-supply = <&vreg_l9a>; + + enable-active-high; + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&panel_vdd_1p8_en>; + pinctrl-names = "default"; + }; + + panel_vci_3p0: regulator-panel-vci { + compatible = "regulator-fixed"; + regulator-name = "panel_vci_3p0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + + enable-active-high; + gpio = <&tlmm 124 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&panel_vci_3p0_en>; + pinctrl-names = "default"; + }; + thermal-zones { rf-pa0-thermal { thermal-sensors = <&pm6125_adc_tm 0>; @@ -162,6 +189,45 @@ touchscreen@38 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l18a>; + status = "okay"; + + panel@0 { + compatible = "samsung,s6e8fco-m1906f9"; + reg = <0>; + + reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&mdss_default>; + pinctrl-1 = <&mdss_sleep>; + pinctrl-names = "default", "sleep"; + + vdd-supply = <&panel_vdd_1p8>; + vci-supply = <&panel_vci_3p0>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + + +&mdss_dsi0_phy { + status = "okay"; +}; + &pm6125_adc { pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm>; @@ -426,6 +492,13 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <22 2>, <28 6>; + panel_vdd_1p8_en: panel-vdd-default-state { + pins = "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + ts_vdd_en: ts-vdd-default-state { pins = "gpio83"; function = "gpio"; @@ -460,6 +533,27 @@ ts_int_suspend: pmx-ts-int-suspend-state { drive-strength = <2>; bias-pull-down; }; + + mdss_default: mdss-default-state { + pins = "gpio90"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mdss_sleep: mdss-sleep-state { + pins = "gpio90"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + panel_vci_3p0_en: panel-vci-default-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &ufs_mem_hc { From c17e220946675232d383620ed9cff6685735ec48 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 23 Mar 2026 12:01:12 +0200 Subject: [PATCH 003/131] arm64: dts: qcom: hamoa: Fix OPP tables for all DisplayPort controllers According to internal documentation, the corners specific for each rate from the DP link clock are: - LOWSVS_D1 -> 19.2 MHz - LOWSVS -> 270 MHz - SVS -> 540 MHz (594 MHz in case of DP3) - SVS_L1 -> 594 MHz - NOM -> 810 MHz - NOM_L1 -> 810 MHz - TURBO -> 810 MHz So fix all tables for each of the four controllers according to the documentation, but since DP0 through DP2 have the same entries in their tables, lets drop the DP1 and DP2 and have all of them share the DP0 table instead. However keep a separate table for the DP3 as it is different for the SVS, compared to the rest of the controllers. The 19.2 MHz @ LOWSVS_D1 isn't needed as it's not an actual working frequency and the controller will never select it. So remove it. Cc: stable@vger.kernel.org # v6.9+ Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Suggested-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260323-hamoa-fix-dp3-opp-table-v3-1-a823776bd1b0@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 77 +++++------------------------ 1 file changed, 12 insertions(+), 65 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 051dee076416..4ba751a65142 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5744,18 +5744,18 @@ mdss_dp0_out: endpoint { mdss_dp0_opp_table: opp-table { compatible = "operating-points-v2"; - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - opp-270000000 { opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; + required-opps = <&rpmhpd_opp_low_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; @@ -5796,7 +5796,7 @@ mdss_dp1: displayport-controller@ae98000 { <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - operating-points-v2 = <&mdss_dp1_opp_table>; + operating-points-v2 = <&mdss_dp0_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -5829,30 +5829,6 @@ mdss_dp1_out: endpoint { }; }; }; - - mdss_dp1_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; }; mdss_dp2: displayport-controller@ae9a000 { @@ -5885,7 +5861,7 @@ mdss_dp2: displayport-controller@ae9a000 { <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - operating-points-v2 = <&mdss_dp2_opp_table>; + operating-points-v2 = <&mdss_dp0_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -5917,30 +5893,6 @@ mdss_dp2_out: endpoint { }; }; }; - - mdss_dp2_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; }; mdss_dp3: displayport-controller@aea0000 { @@ -6004,21 +5956,16 @@ mdss_dp3_out: endpoint { mdss_dp3_opp_table: opp-table { compatible = "operating-points-v2"; - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_low_svs>; }; - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; required-opps = <&rpmhpd_opp_svs>; }; - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; From 1f820571ca7c64d3fd5bd9bf653b571cb3350703 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Mon, 23 Mar 2026 13:54:42 +0000 Subject: [PATCH 004/131] arm64: dts: qcom: milos: Reduce rmtfs_mem size to 2.5MiB The rmtfs_mem region is currently sized at 6MiB but the default for milos downstream is 2.5MiB. This causes remoteproc crashes on devices that expect the smaller size: modem_ac.c:281:Access Control Error: Could not protect the region specified:Start:e1f00000 End:e2180000, PID:1 Reduce the default to 2.5MiB to match the QCOM downstream config, and override the size for FP6. Fixes: d9d59d105f98 ("arm64: dts: qcom: Add initial Milos dtsi") Reviewed-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich Link: https://lore.kernel.org/r/20260323-asteroids-v2-1-1a35fa9e178a@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 5 +++++ arch/arm64/boot/dts/qcom/milos.dtsi | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index c1899db46e71..5dc7c950e60d 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -786,6 +786,11 @@ &remoteproc_wpss { status = "okay"; }; +&rmtfs_mem { + /* Increase the size from 2.5 MiB to 6 MiB */ + reg = <0x0 0xe1f00000 0x0 0x600000>; +}; + &sdhc_2 { cd-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 4a64a98a434b..347afce18924 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -642,7 +642,7 @@ cpusys_vm_mem: cpusys-vm-region@e0600000 { rmtfs_mem: rmtfs@e1f00000 { compatible = "qcom,rmtfs-mem"; - reg = <0x0 0xe1f00000 0x0 0x600000>; + reg = <0x0 0xe1f00000 0x0 0x280000>; no-map; qcom,client-id = <1>; From 93be926a7f6dc89657d3e8488f353893841039ce Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Mon, 23 Mar 2026 13:54:53 +0000 Subject: [PATCH 005/131] dt-bindings: arm: qcom: Add the Nothing Phone (3a) Document the Milos-based Nothing Phone (3a) smartphone. Acked-by: Krzysztof Kozlowski Signed-off-by: Alexander Koskovich Link: https://lore.kernel.org/r/20260323-asteroids-v2-2-1a35fa9e178a@pm.me Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b4943123d2e4..24164ba70b6f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -79,6 +79,7 @@ properties: - items: - enum: - fairphone,fp6 + - nothing,asteroids - const: qcom,milos - items: From edbf03c9fb5ff72f8e7974b35f7ee2d9ae7cb371 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Mon, 23 Mar 2026 13:55:05 +0000 Subject: [PATCH 006/131] arm64: dts: qcom: Add the Nothing Phone (3a) Add a devicetree for the Nothing Phone (3a) smartphone, which is based on the Milos/SM7635 SoC. Supported functionality as of this initial submission: * Camera flash/torch LED * Debug UART * Glyph LEDs (AW20036) * PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching) * Assistant Key, Power Button, Volume Keys * Regulators (PM7550, PM8550VS, PMR735B) * Remoteprocs (ADSP, CDSP, MPSS, WPSS) * USB (USB2 + FSA4480) Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich Link: https://lore.kernel.org/r/20260323-asteroids-v2-3-1a35fa9e178a@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/milos-nothing-asteroids.dts | 964 ++++++++++++++++++ 2 files changed, 965 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4ba8e7306419..169cc9b9ccd3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -56,6 +56,7 @@ lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb +dtb-$(CONFIG_ARCH_QCOM) += milos-nothing-asteroids.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts b/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts new file mode 100644 index 000000000000..7393978926e4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#define PMIV0104_SID 7 + +#include +#include +#include + +#include "milos.dtsi" +#include "pm7550.dtsi" +#include "pm8550vs.dtsi" +#include "pmiv0104.dtsi" /* PMIV0102 */ +#include "pmk8550.dtsi" /* PMK7635 */ +#include "pmr735b.dtsi" + +/ { + model = "Nothing Phone (3a)"; + compatible = "nothing,asteroids", "qcom,milos"; + chassis-type = "handset"; + + aliases { + serial0 = &uart5; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@e3940000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xe3940000 0x0 (2392 * 1080 * 4)>; + width = <1080>; + height = <2392>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + panel = <&panel>; + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + + /* Dummy panel for simple-framebuffer dimension info */ + panel: dummy-panel { + compatible = "boe,bf068mwm-td0"; + height-mm = <157>; + width-mm = <71>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&assist_default>, <&volume_up_default>; + pinctrl-names = "default"; + + key-assist { + gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + label = "Assistant"; + linux,code = ; + }; + + key-volume-up { + gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>; + label = "Volume Up"; + linux,code = ; + }; + }; + + pmic-glink { + compatible = "qcom,milos-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 131 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + data-role = "dual"; + power-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@81f20000 { + compatible = "ramoops"; + reg = <0x0 0x81f20000 0x0 0x400000>; + console-size = <0x200000>; + mem-type = <2>; + pmsg-size = <0x200000>; + }; + + /* + * ABL is powering down display and controller if this node is + * not named exactly "splash_region". + */ + splash_region@e3940000 { + reg = <0x0 0xe3940000 0x0 0x2b00000>; + no-map; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1b>; + vdd-l2-l3-supply = <&vreg_s3b>; + vdd-l4-l5-supply = <&vreg_s2b>; + vdd-l7-supply = <&vreg_s1b>; + vdd-l8-supply = <&vreg_s1b>; + vdd-l9-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s1b>; + vdd-l12-l14-supply = <&vreg_bob>; + vdd-l13-l16-supply = <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-bob-supply = <&vph_pwr>; + + qcom,pmic-id = "b"; + + vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2080000>; + regulator-initial-mode = ; + }; + + vreg_s2b: smps2 { + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1408000>; + regulator-initial-mode = ; + }; + + vreg_s3b: smps3 { + regulator-name = "vreg_s3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1040000>; + regulator-initial-mode = ; + }; + + vreg_s4b: smps4 { + regulator-name = "vreg_s4b"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_l1b: ldo1 { + regulator-name = "vreg_l1b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l5b: ldo5 { + regulator-name = "vreg_l5b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10b: ldo10 { + regulator-name = "vreg_l10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l20b: ldo20 { + regulator-name = "vreg_l20b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l21b: ldo21 { + regulator-name = "vreg_l21b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l22b: ldo22 { + regulator-name = "vreg_l22b"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l23b: ldo23 { + regulator-name = "vreg_l23b"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3b>; + vdd-l2-supply = <&vreg_s3b>; + vdd-l3-supply = <&vreg_s3b>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "c"; + + vreg_s3c: smps3 { + regulator-name = "vreg_s3c"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_s4c: smps4 { + regulator-name = "vreg_s4c"; + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <812000>; + regulator-initial-mode = ; + }; + + vreg_s5c: smps5 { + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <540000>; + regulator-max-microvolt = <884000>; + regulator-initial-mode = ; + }; + + vreg_s6c: smps6 { + regulator-name = "vreg_s6c"; + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmr735b-rpmh-regulators"; + + vdd-l1-l2-supply = <&vreg_s3b>; + vdd-l3-supply = <&vreg_s3b>; + vdd-l4-supply = <&vreg_s1b>; + vdd-l5-supply = <&vreg_s2b>; + vdd-l7-l8-supply = <&vreg_s2b>; + vdd-l9-supply = <&vreg_s3b>; + vdd-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s3b>; + vdd-l12-supply = <&vreg_s3b>; + + qcom,pmic-id = "f"; + + vreg_l1f: ldo1 { + regulator-name = "vreg_l1f"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + }; + + vreg_l2f: ldo2 { + regulator-name = "vreg_l2f"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l3f: ldo3 { + regulator-name = "vreg_l3f"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l4f: ldo4 { + regulator-name = "vreg_l4f"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + }; + + vreg_l5f: ldo5 { + regulator-name = "vreg_l5f"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l7f: ldo7 { + regulator-name = "vreg_l7f"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + }; + + vreg_l9f: ldo9 { + regulator-name = "vreg_l9f"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l10f: ldo10 { + regulator-name = "vreg_l10f"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11f: ldo11 { + regulator-name = "vreg_l11f"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <864000>; + regulator-initial-mode = ; + }; + + vreg_l12f: ldo12 { + regulator-name = "vreg_l12f"; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <884000>; + regulator-initial-mode = ; + }; + }; +}; + +&dispcc { + /* Disable for now so simple-framebuffer continues working */ + status = "disabled"; +}; + +&gcc { + protected-clocks = , , + , , + , , + , , + , , + , ; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + led-controller@3a { + compatible = "awinic,aw20036"; + reg = <0x3a>; + #address-cells = <1>; + #size-cells = <0>; + + enable-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; + + led@0 { + reg = <0x0>; + color = ; + function = "glyph-1"; + function-enumerator = <0>; + led-max-microamp = <6560>; + }; + + led@1 { + reg = <0x1>; + color = ; + function = "glyph-1"; + function-enumerator = <1>; + led-max-microamp = <6560>; + }; + + led@2 { + reg = <0x2>; + color = ; + function = "glyph-1"; + function-enumerator = <2>; + led-max-microamp = <6560>; + }; + + led@3 { + reg = <0x3>; + color = ; + function = "glyph-1"; + function-enumerator = <3>; + led-max-microamp = <6560>; + }; + + led@4 { + reg = <0x4>; + color = ; + function = "glyph-1"; + function-enumerator = <4>; + led-max-microamp = <6560>; + }; + + led@5 { + reg = <0x5>; + color = ; + function = "glyph-1"; + function-enumerator = <5>; + led-max-microamp = <6560>; + }; + + led@6 { + reg = <0x6>; + color = ; + function = "glyph-1"; + function-enumerator = <6>; + led-max-microamp = <6560>; + }; + + led@7 { + reg = <0x7>; + color = ; + function = "glyph-2"; + function-enumerator = <0>; + led-max-microamp = <6560>; + }; + + led@8 { + reg = <0x8>; + color = ; + function = "glyph-3"; + function-enumerator = <0>; + led-max-microamp = <6560>; + }; + + led@9 { + reg = <0x9>; + color = ; + function = "glyph-3"; + function-enumerator = <1>; + led-max-microamp = <6560>; + }; + + led@a { + reg = <0xa>; + color = ; + function = "glyph-3"; + function-enumerator = <2>; + led-max-microamp = <6560>; + }; + + led@b { + reg = <0xb>; + color = ; + function = "glyph-3"; + function-enumerator = <3>; + led-max-microamp = <6560>; + }; + + led@c { + reg = <0xc>; + color = ; + function = "glyph-1"; + function-enumerator = <7>; + led-max-microamp = <6560>; + }; + + led@d { + reg = <0xd>; + color = ; + function = "glyph-1"; + function-enumerator = <8>; + led-max-microamp = <6560>; + }; + + led@e { + reg = <0xe>; + color = ; + function = "glyph-1"; + function-enumerator = <9>; + led-max-microamp = <6560>; + }; + + led@f { + reg = <0xf>; + color = ; + function = "glyph-1"; + function-enumerator = <10>; + led-max-microamp = <6560>; + }; + + led@10 { + reg = <0x10>; + color = ; + function = "glyph-1"; + function-enumerator = <11>; + led-max-microamp = <6560>; + }; + + led@11 { + reg = <0x11>; + color = ; + function = "glyph-1"; + function-enumerator = <12>; + led-max-microamp = <6560>; + }; + + led@12 { + reg = <0x12>; + color = ; + function = "glyph-1"; + function-enumerator = <13>; + led-max-microamp = <6560>; + }; + + led@13 { + reg = <0x13>; + color = ; + function = "glyph-2"; + function-enumerator = <1>; + led-max-microamp = <6560>; + }; + + led@14 { + reg = <0x14>; + color = ; + function = "glyph-2"; + function-enumerator = <2>; + led-max-microamp = <6560>; + }; + + led@15 { + reg = <0x15>; + color = ; + function = "glyph-3"; + function-enumerator = <4>; + led-max-microamp = <6560>; + }; + + led@16 { + reg = <0x16>; + color = ; + function = "glyph-3"; + function-enumerator = <5>; + led-max-microamp = <6560>; + }; + + led@17 { + reg = <0x17>; + color = ; + function = "glyph-3"; + function-enumerator = <6>; + led-max-microamp = <6560>; + }; + + led@18 { + reg = <0x18>; + color = ; + function = "glyph-1"; + function-enumerator = <14>; + led-max-microamp = <6560>; + }; + + led@19 { + reg = <0x19>; + color = ; + function = "glyph-1"; + function-enumerator = <15>; + led-max-microamp = <6560>; + }; + + led@1a { + reg = <0x1a>; + color = ; + function = "glyph-1"; + function-enumerator = <16>; + led-max-microamp = <6560>; + }; + + led@1b { + reg = <0x1b>; + color = ; + function = "glyph-1"; + function-enumerator = <17>; + led-max-microamp = <6560>; + }; + + led@1c { + reg = <0x1c>; + color = ; + function = "glyph-1"; + function-enumerator = <18>; + led-max-microamp = <6560>; + }; + + led@1d { + reg = <0x1d>; + color = ; + function = "glyph-1"; + function-enumerator = <19>; + led-max-microamp = <6560>; + }; + + led@1e { + reg = <0x1e>; + color = ; + function = "glyph-2"; + function-enumerator = <3>; + led-max-microamp = <6560>; + }; + + led@1f { + reg = <0x1f>; + color = ; + function = "glyph-2"; + function-enumerator = <4>; + led-max-microamp = <6560>; + }; + + led@20 { + reg = <0x20>; + color = ; + function = "glyph-3"; + function-enumerator = <7>; + led-max-microamp = <6560>; + }; + + led@21 { + reg = <0x21>; + color = ; + function = "glyph-3"; + function-enumerator = <8>; + led-max-microamp = <6560>; + }; + + led@22 { + reg = <0x22>; + color = ; + function = "glyph-3"; + function-enumerator = <9>; + led-max-microamp = <6560>; + }; + + led@23 { + reg = <0x23>; + color = ; + function = "glyph-3"; + function-enumerator = <10>; + led-max-microamp = <6560>; + }; + }; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vph_pwr>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&pm7550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <350000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; +}; + +&pm7550_gpios { + volume_up_default: volume-up-default-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + }; +}; + +&pm8550vs_c { + status = "okay"; +}; + +&pmiv0104_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; + + qcom,tune-res-fsdif = /bits/ 8 <0x5>; + qcom,tune-usb2-amplitude = /bits/ 8 <0x8>; + qcom,tune-usb2-disc-thres = /bits/ 8 <0x7>; + qcom,tune-usb2-preem = /bits/ 8 <0x6>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/milos/nothing/asteroids/adsp.mbn", + "qcom/milos/nothing/asteroids/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/milos/nothing/asteroids/cdsp.mbn", + "qcom/milos/nothing/asteroids/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/milos/nothing/asteroids/modem.mbn"; + + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/milos/nothing/asteroids/wpss.mbn"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <13 1>, /* Display */ + <63 2>; /* WLAN UART */ + + assist_default: assist-default-state { + pins = "gpio71"; + function = "gpio"; + bias-pull-up; + }; +}; + +&trusted_apps_mem { + reg = <0x0 0xe9500000 0x0 0x5500000>; +}; + +/* + * UART_RX and UART_TX are routed to test points on board, not + * available over USB. + */ +&uart5 { + status = "okay"; +}; + +&usb_1 { + /* USB 2.0 only, HW does not support USB 3.x */ + qcom,select-utmi-as-pipe-clk; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l2b>; + vdda12-supply = <&vreg_l4b>; + + phys = <&pmiv0104_eusb2_repeater>; + + status = "okay"; +}; From 244e064bc8ce848d40fe13451b6096a66b2bbdb2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:22 +0100 Subject: [PATCH 007/131] arm64: dts: qcom: qcs615-ride: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-2-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 7e05f873194a..831002789838 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -610,7 +610,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From d28f68b052780b945c35996d02adf2426ed0bff7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:23 +0100 Subject: [PATCH 008/131] arm64: dts: qcom: sc8280xp-crd: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-3-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index c53e00cae465..dcdeefd28728 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -787,7 +787,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From fa99d3af7edb8acd735e861446477afd64007af7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:24 +0100 Subject: [PATCH 009/131] arm64: dts: qcom: sc8280xp-gaokun3: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-4-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index 9819454abe13..f3c00be67081 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -1122,7 +1122,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; }; From de1a7dc3ccda556bef52185ae1d65ebb900b2925 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:25 +0100 Subject: [PATCH 010/131] arm64: dts: qcom: sc8280xp-x13s: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-5-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index d84ca010ab9d..abd9c5a67b9f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1331,7 +1331,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; }; From a25cd984f4078cb772179787cf78790bbcc2c543 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:26 +0100 Subject: [PATCH 011/131] arm64: dts: qcom: sc8280xp-blackrock: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-6-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 00bbeeef6f14..125af356e24b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -976,7 +976,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; }; From 557a49f764306ccf8155ca19970be78d90f8d3de Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:27 +0100 Subject: [PATCH 012/131] arm64: dts: qcom: sm8450-hdk: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-7-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 268ae0cd642a..b37998cd9a2c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -1172,7 +1172,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From e5a38ea7633853433295106650d008c1428d4d0e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:28 +0100 Subject: [PATCH 013/131] arm64: dts: qcom: x1-omnibook-x14: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-8-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi index b773a4976d1b..02708f23a865 100644 --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -1452,7 +1452,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From 8be58b9b8a10ac276d4058c66ebd6b2b9e5aa683 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:29 +0100 Subject: [PATCH 014/131] arm64: dts: qcom: x1-zenbook-a14: Fix BT RFA supply name Fix up the supply name to align with bindings. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-9-576ec5c4e631@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi index 22470a97e1e3..7f5860d2b6cc 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi @@ -128,7 +128,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; From d859095bcafc4c5e26c551350d2327aeb2e08e59 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 25 Feb 2026 13:23:30 +0100 Subject: [PATCH 015/131] arm64: dts: qcom: lemans-ride-common: Fix up WCN power grid Make the dt checker happy by filling out the required properties in line with the schematics. Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260225-topic-wcn6855_pmu_dtbdings-v3-10-576ec5c4e631@oss.qualcomm.com [bjorn: Remove reference to dropped 12V supply] Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/lemans-ride-common.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 31bd00546d55..679e045a6d49 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -53,6 +53,16 @@ vreg_3p0: vreg-3p0-regulator { regulator-max-microvolt = <3000000>; }; + vreg_3p3: vreg-3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VREG_3P3"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + vreg_conn_1p8: vreg_conn_1p8 { compatible = "regulator-fixed"; regulator-name = "vreg_conn_1p8"; @@ -69,6 +79,22 @@ vreg_conn_pa: vreg_conn_pa { gpio = <&pmm8654au_1_gpios 6 GPIO_ACTIVE_HIGH>; }; + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: vreg-wcn-0p95-regulator { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_3p3>; + }; + wcn6855-pmu { compatible = "qcom,wcn6855-pmu"; @@ -78,6 +104,8 @@ wcn6855-pmu { vddio-supply = <&vreg_conn_pa>; vddaon-supply = <&vreg_l2c>; vddpmu-supply = <&vreg_conn_1p8>; + vddpmumx-supply = <&vreg_wcn_0p95>; + vddpmucx-supply = <&vreg_wcn_0p95>; vddrfa0p95-supply = <&vreg_l2c>; vddrfa1p3-supply = <&vreg_l6e>; vddrfa1p9-supply = <&vreg_s5a>; @@ -956,6 +984,8 @@ bluetooth { vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; }; }; From cbdf1a61dde22c226a776d60ea5bff260b94f653 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 15:44:35 -0400 Subject: [PATCH 016/131] arm64: dts: qcom: sdm670: label the camss ports instead of endpoints Endpoints cannot be pre-defined since commit dcf6fb89e6f7 ("media: qcom: camss: remove a check for unavailable CAMSS endpoint") was applied, probing all endpoint nodes and requiring them to have a remote. There is no sensible remote in the SoC devicetree because camera sensors are board-specific. The ports are meant to be extended by a board devicetree in order to define fully configured endpoints and connect the ports to camera sensors. For nodes that are only meaningful if extended, labels are usually assigned. Label these ports so they can be extended directly. Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20260331194437.41041-2-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index c195c79c1c85..1613c66f92b3 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1787,28 +1787,16 @@ ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + camss_port0: port@0 { reg = <0>; - - camss_endpoint0: endpoint { - status = "disabled"; - }; }; - port@1 { + camss_port1: port@1 { reg = <1>; - - camss_endpoint1: endpoint { - status = "disabled"; - }; }; - port@2 { + camss_port2: port@2 { reg = <2>; - - camss_endpoint2: endpoint { - status = "disabled"; - }; }; }; }; From 86695909eab6bfa577bf68c615dbe852ba9c8197 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 15:44:36 -0400 Subject: [PATCH 017/131] arm64: dts: qcom: sdm670: add camera mclk pins The camera subsystem is added for the SoC common devicetree, but the mclk pins should also be common across the SoC. Add the mclk pins for the cameras. Suggested-by: Konrad Dybcio Link: https://lore.kernel.org/r/5135823c-f2e4-4873-9e3a-9d190cac0113@oss.qualcomm.com Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Reviewed-by: David Heidelberg Reviewed-by: Konrad Dybcio Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20260331194437.41041-3-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 1613c66f92b3..e13ced9479b7 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1207,6 +1207,34 @@ tlmm: pinctrl@3400000 { gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc>; + cam_mclk0_default: cam-mclk0-default-state { + pins = "gpio13"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk1_default: cam-mclk1-default-state { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk2_default: cam-mclk2-default-state { + pins = "gpio15"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk3_default: cam-mclk3-default-state { + pins = "gpio16"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + cci0_default: cci0-default-state { pins = "gpio17", "gpio18"; function = "cci_i2c"; From 8d3a34d7890faa4d968b16e29c5c80e559291fd2 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 15:44:37 -0400 Subject: [PATCH 018/131] arm64: dts: qcom: sdm670-google-sargo: add imx355 front camera The Sony IMX355 is the front camera on the Pixel 3a, mounted in portrait mode. It is connected to CSIPHY1 and CCI I2C1, and uses MCLK2. Add support for it. Co-developed-by: Robert Mader Signed-off-by: Robert Mader Signed-off-by: Richard Acayan Reviewed-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260331194437.41041-4-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm670-google-sargo.dts | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index ed55646ca419..eba2f3792dd0 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -172,6 +172,34 @@ vreg_s2b_1p05: vreg-s2b-regulator { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; + + cam_front_ldo: cam-front-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_front_ldo"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-enable-ramp-delay = <135>; + + gpios = <&pm660l_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_front_ldo_pin>; + pinctrl-names = "default"; + }; + + cam_vio_ldo: cam-vio-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_vio_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <233>; + + gpios = <&pm660_gpios 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_vio_pin>; + pinctrl-names = "default"; + }; }; &apps_rsc { @@ -392,6 +420,64 @@ vreg_bob: bob { }; }; +&camss { + vdda-phy-supply = <&vreg_l1a_1p225>; + vdda-pll-supply = <&vreg_s6a_0p87>; + + status = "okay"; +}; + +&camss_port1 { + camss_endpoint1: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_front_endpoint>; + }; +}; + +&cci { + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&cci_i2c1 { + camera@1a { + compatible = "sony,imx355"; + reg = <0x1a>; + + clocks = <&camcc CAM_CC_MCLK2_CLK>; + + /* + * The sensor can accept a 24 MHz clock, but 19.2 MHz has + * better driver compatibility. + */ + assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates = <19200000>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + avdd-supply = <&cam_front_ldo>; + dvdd-supply = <&cam_front_ldo>; + dovdd-supply = <&cam_vio_ldo>; + + pinctrl-0 = <&cam_mclk2_default>; + pinctrl-names = "default"; + + rotation = <270>; + orientation = <0>; + + port { + cam_front_endpoint: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <360000000>; + remote-endpoint = <&camss_endpoint1>; + }; + }; + }; +}; + &gcc { protected-clocks = , , @@ -490,6 +576,14 @@ &pm660_charger { status = "okay"; }; +&pm660_gpios { + cam_vio_pin: cam-vio-state { + pins = "gpio13"; + function = "normal"; + power-source = <0>; + }; +}; + &pm660_rradc { status = "okay"; }; @@ -508,6 +602,12 @@ led-0 { }; &pm660l_gpios { + cam_front_ldo_pin: cam-front-state { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + }; + vol_up_pin: vol-up-state { pins = "gpio7"; function = "normal"; From a4f6959661f0c8542e5a89aaaef27fc4ac9408a6 Mon Sep 17 00:00:00 2001 From: Petr Hodina Date: Thu, 2 Apr 2026 00:39:35 +0200 Subject: [PATCH 019/131] arm64: dts: qcom: sdm845-xiaomi-beryllium: Introduce framebuffer Add framebuffer for early console and u-boot support. Signed-off-by: Petr Hodina Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402-beryllium-fb-v4-1-46170004da28@ixit.cz Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 1298485c4214..a6ee3dd171de 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -39,6 +39,22 @@ aliases { serial1 = &uart6; }; + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&cont_splash_mem>; + + format = "a8r8g8b8"; + stride = <(1080 * 4)>; + height = <2246>; + width = <1080>; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; From b379bb1470d864659ae9522b72f241a15255dce6 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 2 Apr 2026 00:39:36 +0200 Subject: [PATCH 020/131] arm64: dts: qcom: sdm845-oneplus: Drop address from framebuffer node This node has no 'reg' property, so it shouldn't have a unit address (after '@') either Fixes: b0d5c96e860c ("arm64: dts: qcom: sdm845-oneplus: Add framebuffer") Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260402-beryllium-fb-v4-2-46170004da28@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 6b7378cf4d49..b0b9baf01ec2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -72,7 +72,7 @@ chosen { stdout-path = "serial0:115200n8"; - framebuffer: framebuffer@9d400000 { + framebuffer: framebuffer { compatible = "simple-framebuffer"; memory-region = <&cont_splash_mem>; From 15520f868651d6b03c603918bade78f4799df7ca Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 2 Apr 2026 00:39:37 +0200 Subject: [PATCH 021/131] arm64: dts: qcom: sdm845-shift-axolotl: Convert fb to use memory-region Instead of manually specifying reg, reuse the memory region. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260402-beryllium-fb-v4-3-46170004da28@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 7d81198bc499..d248d282ef7c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -23,7 +23,7 @@ / { qcom,board-id = <11 0>; aliases { - display0 = &framebuffer0; + display0 = &framebuffer; serial0 = &uart9; serial1 = &uart6; }; @@ -36,9 +36,9 @@ chosen { stdout-path = "serial0"; /* Use framebuffer setup by the bootloader. */ - framebuffer0: framebuffer@9d400000 { + framebuffer: framebuffer { compatible = "simple-framebuffer"; - reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; + memory-region = <&framebuffer_mem>; width = <1080>; height = <2160>; stride = <(1080 * 4)>; @@ -62,7 +62,7 @@ key-vol-up { }; reserved-memory { - framebuffer@9d400000 { + framebuffer_mem: framebuffer@9d400000 { reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; no-map; }; From 2eae029f7d38c5fc03a778f483b5079d0e355472 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 2 Apr 2026 00:39:38 +0200 Subject: [PATCH 022/131] arm64: dts: qcom: sdm845-samsung-starqltechn: Convert fb to use memory-region Instead of manually specifying reg, reuse the memory region. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260402-beryllium-fb-v4-4-46170004da28@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 77f5872de6f1..0d915ecb0444 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -43,9 +43,10 @@ chosen { #address-cells = <2>; #size-cells = <2>; ranges; - framebuffer: framebuffer@9d400000 { + + framebuffer { compatible = "simple-framebuffer"; - reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000 + memory-region = <&framebuffer_mem>; width = <1440>; height = <2960>; stride = <(1440 * 4)>; @@ -109,7 +110,7 @@ vreg_s4a_1p8: pm8998-smps4 { }; reserved-memory { - memory@9d400000 { + framebuffer_mem: memory@9d400000 { reg = <0x0 0x9d400000 0x0 0x02400000>; no-map; }; From 66fb209e6035ed90cbff71c48c60124803da5c63 Mon Sep 17 00:00:00 2001 From: Griffin Kroah-Hartman Date: Fri, 3 Apr 2026 10:21:33 +0200 Subject: [PATCH 023/131] arm64: dts: qcom: milos-fairphone-fp6: Add vibrator support Add the required node for haptic playback (Awinic AW86938) Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Griffin Kroah-Hartman Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260403-aw86938-driver-v5-1-0712909df423@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/milos-fairphone-fp6.dts | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index 5dc7c950e60d..ebdca0e2d2f3 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -687,7 +687,17 @@ vreg_l7p: ldo7 { }; /* VL53L3 ToF @ 0x29 */ - /* AW86938FCR vibrator @ 0x5a */ + + vibrator@5a { + compatible = "awinic,aw86938", "awinic,aw86927"; + reg = <0x5a>; + + interrupts-extended = <&tlmm 80 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&aw86938_int_default>, <&aw86938_reset_default>; + pinctrl-names = "default"; + }; }; &pm8550vs_c { @@ -829,6 +839,20 @@ hall_sensor_default: hall-sensor-default-state { bias-disable; }; + aw86938_reset_default: aw86938-reset-default-state { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + aw86938_int_default: aw86938-int-default-state { + pins = "gpio80"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + pm8008_int_default: pm8008-int-default-state { pins = "gpio125"; function = "gpio"; From 2552d5f2e51bd7e449b495d518e1f2e5252baf56 Mon Sep 17 00:00:00 2001 From: Aastha Pandey Date: Fri, 3 Apr 2026 17:26:33 +0530 Subject: [PATCH 024/131] arm64: dts: qcom: sm8750: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Aastha Pandey Reviewed-by: Dmitry Baryshkov Reviewed-by: Gaurav Kohli Link: https://lore.kernel.org/r/20260403-cpufreq-v1-1-9d465988c3f9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 18fb52c14acd..417f28d8c919 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -42,6 +42,7 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -58,6 +59,7 @@ cpu1: cpu@100 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -68,6 +70,7 @@ cpu2: cpu@200 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -78,6 +81,7 @@ cpu3: cpu@300 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -88,6 +92,7 @@ cpu4: cpu@400 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd4>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -98,6 +103,7 @@ cpu5: cpu@500 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd5>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu6: cpu@10000 { @@ -108,6 +114,7 @@ cpu6: cpu@10000 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -124,6 +131,7 @@ cpu7: cpu@10100 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu-map { From cd66b6d256f94e40922941e14d7f9390d35d072b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:28 +0200 Subject: [PATCH 025/131] arm64: dts: qcom: glymur: Fix USB simple_bus_reg warning Correct the unit address of USB node in Qualcomm Glymur SoC DTSI to fix W=1 DTC warning: glymur.dtsi:4027.23-4093.5: Warning (simple_bus_reg): /soc@0/usb@a2f8800: simple-bus unit address format error, expected "a200000" Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-1-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index f23cf81ddb77..3389103408b6 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4024,7 +4024,7 @@ usb_2_dwc3_ss: endpoint { }; }; - usb_hs: usb@a2f8800 { + usb_hs: usb@a200000 { compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; reg = <0x0 0x0a200000 0x0 0xfc100>; From 46eccc1034c3740b07b58c125190bbb99247c9de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:29 +0200 Subject: [PATCH 026/131] arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warnings Correct the unit address of cache controller and SRAM nodes in Qualcomm Glymur SoC DTSI to fix W=1 DTC warnings: glymur.dtsi:5876.36-5908.5: Warning (simple_bus_reg): /soc@0/system-cache-controller@20400000: simple-bus unit address format error, expected "21800000" glymur.dtsi:5917.23-5934.5: Warning (simple_bus_reg): /soc@0/sram@81e08000: simple-bus unit address format error, expected "81e08600" Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-2-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 3389103408b6..0c5cb8532b20 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5873,7 +5873,7 @@ oobm_ss_noc: interconnect@1f300000 { #interconnect-cells = <2>; }; - system-cache-controller@20400000 { + system-cache-controller@21800000 { compatible = "qcom,glymur-llcc"; reg = <0x0 0x21800000 0x0 0x100000>, <0x0 0x21a00000 0x0 0x100000>, @@ -5914,7 +5914,7 @@ nsp_noc: interconnect@320c0000 { #interconnect-cells = <2>; }; - imem: sram@81e08000 { + imem: sram@81e08600 { compatible = "mmio-sram"; reg = <0x0 0x81e08600 0x0 0x300>; From 864fde494aa1dd26c68254661f2ce973e9f03832 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:30 +0200 Subject: [PATCH 027/131] arm64: dts: qcom: ipq5424: Fix USB simple_bus_reg warnings Correct the unit address of USB nodes in Qualcomm IPQ5424 SoC DTSI to fix W=1 DTC warnings: ipq5424.dtsi:642.22-693.5: Warning (simple_bus_reg): /soc@0/usb2@1e00000: simple-bus unit address format error, expected "1ef8800" ipq5424.dtsi:733.22-786.5: Warning (simple_bus_reg): /soc@0/usb3@8a00000: simple-bus unit address format error, expected "8af8800" Fixes: 113d52bdc820 ("arm64: dts: qcom: ipq5424: Add USB controller and phy nodes") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-3-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index f20cda429094..876bf6a8b8ff 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -639,7 +639,7 @@ qusb_phy_1: phy@71000 { status = "disabled"; }; - usb2: usb2@1e00000 { + usb2: usb2@1ef8800 { compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; reg = <0 0x01ef8800 0 0x400>; #address-cells = <2>; @@ -730,7 +730,7 @@ ssphy_0: phy@7d000 { status = "disabled"; }; - usb3: usb3@8a00000 { + usb3: usb3@8af8800 { compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; reg = <0 0x08af8800 0 0x400>; From f319a5fc998e29699d325af0e461721b3768eeec Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:31 +0200 Subject: [PATCH 028/131] arm64: dts: qcom: sc8180x: Fix phy simple_bus_reg warning Correct the unit address of phy node in Qualcomm SC8180x SoC DTSI to fix W=1 DTC warning: sc8180x.dtsi:2650.31-2695.5: Warning (simple_bus_reg): /soc@0/phy@88ee000: simple-bus unit address format error, expected "88ed000" Fixes: 35e3a9c1afce ("arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-4-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index f45deb188c6c..e87e82fa73e9 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2647,7 +2647,7 @@ usb_mp_qmpphy1: phy@88ec000 { status = "disabled"; }; - usb_sec_qmpphy: phy@88ee000 { + usb_sec_qmpphy: phy@88ed000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; reg = <0 0x088ed000 0 0x3000>; From f20a82aacd7f381084391a8d1f0f58defa91974c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 15:39:32 +0200 Subject: [PATCH 029/131] arm64: dts: qcom: sdm845-mezzanine: Fix camss ports unit_address_vs_reg warning Add necessary properties for ports node in SDM845 DB845c Navigation mezzanine overlay to fix W=1 DTC warning: sdm845-db845c-navigation-mezzanine.dtso:19.10-24.5: Warning (unit_address_vs_reg): /fragment@0/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property Fixes: 30df676a31b7 ("arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso") Reviewed-by: Dmitry Baryshkov Reviewed-by: David Heidelberg Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-5-1f2c7b74a93f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso index dbe1911d8e47..678a17c805f7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso @@ -16,7 +16,12 @@ &camss { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csiphy0_ep: endpoint { data-lanes = <0 1 2 3>; remote-endpoint = <&ov8856_ep>; From e8fae9152e100b4bb30d38b25bc9c81623e8e91e Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Mon, 6 Apr 2026 19:05:55 +0530 Subject: [PATCH 030/131] arm64: dts: qcom: fix temp-alarm probe failure for PMH0104 on Glymur The temp-alarm driver probe is failing for the pmh0104 PMICs on glymur. [ 3.999713] spmi-temp-alarm c426000.spmi:pmic@8:temp-alarm@a00: error -ENODEV: failed to register sensor [ 4.015066] spmi-temp-alarm c426000.spmi:pmic@9:temp-alarm@a00: error -ENODEV: failed to register sensor [ 4.033908] spmi-temp-alarm c437000.spmi:pmic@b:temp-alarm@a00: error -ENODEV: failed to register sensor This happens because thermal zone associated with the temp alarm was defined under the thermal zones parent node which had a typo (used `_` in place of `-`). Correct the typo to fix probe failure. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Kamal Wadhwa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406-glymur-pmh0104-temp-alarm-fix-v1-1-4441b7b01f85@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi index 7a1e5f355c17..6b4747025b9f 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -7,7 +7,7 @@ #include /{ - thermal_zones { + thermal-zones { pmh0104_i0_thermal: pmh0104-i0-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmh0104_i_e0_temp_alarm>; From 50fc93244973f5ebc97eb06857fb6bed0e3cbd39 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 3 Apr 2026 15:58:47 +0200 Subject: [PATCH 031/131] arm64: dts: qcom: sdm845-oneplus: Enable NFC Enable NFC controller NXP PN553, which is part of the package NXP NQ330 (NFC + eSE). Based on work of biemster . Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-oneplus-nfc-v3-2-fbdce57d63c1@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index b0b9baf01ec2..04e11448b53a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -464,6 +464,26 @@ &gpu_zap_shader { firmware-name = "qcom/sdm845/OnePlus/enchilada/a630_zap.mbn"; }; +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + nfc@28 { + compatible = "nxp,pn553", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-1 = <&nfc_sleep>; + pinctrl-names = "default", "sleep"; + }; +}; + &i2c10 { status = "okay"; clock-frequency = <100000>; @@ -674,6 +694,11 @@ &qupv3_id_0 { status = "okay"; }; +&qup_i2c3_default { + drive-strength = <2>; + bias-disable; +}; + &qup_i2c10_default { drive-strength = <2>; bias-disable; @@ -1007,6 +1032,38 @@ speaker_default: speaker-default-state { bias-pull-up; output-high; }; + + nfc_default: nfc-default-state { + enable-pins { + pins = "gpio12", "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + int-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + nfc_sleep: nfc-sleep-state { + enable-pins { + pins = "gpio12", "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + int-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; &venus { From 0689aa70fe28ba13eb1d8b10d50e08157ade9670 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 3 Apr 2026 15:58:48 +0200 Subject: [PATCH 032/131] arm64: dts: qcom: sdm845-shift-axolotl: Correct touchscreen sleep state There is no suspend state in the mainline kernel, use the sleep state intended for this purpose. Fixes: 45882459159d ("arm64: dts: qcom: sdm845: add device tree for SHIFT6mq") Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-oneplus-nfc-v3-3-fbdce57d63c1@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index d248d282ef7c..de9ceb9d6ed4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -448,7 +448,7 @@ touchscreen@38 { pinctrl-0 = <&ts_int_active &ts_reset_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - pinctrl-names = "default", "suspend"; + pinctrl-names = "default", "sleep"; touchscreen-size-x = <1080>; touchscreen-size-y = <2160>; From f585772843ba6add712bbf2505055f34d07b8622 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 3 Apr 2026 15:58:49 +0200 Subject: [PATCH 033/131] arm64: dts: qcom: sdm845-shift-axolotl: Enable NFC Enable NFC controller NXP PN553. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-oneplus-nfc-v3-4-fbdce57d63c1@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index de9ceb9d6ed4..14a683ee3823 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -431,6 +431,26 @@ &gpu_zap_shader { firmware-name = "qcom/sdm845/SHIFT/axolotl/a630_zap.mbn"; }; +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + nfc@28 { + compatible = "nxp,pn553", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-1 = <&nfc_sleep>; + pinctrl-names = "default", "sleep"; + }; +}; + &i2c5 { clock-frequency = <400000>; @@ -668,6 +688,38 @@ sdc2_card_det_n: sd-card-det-n-state { bias-disable; }; + nfc_default: nfc-default-state { + enable-pins { + pins = "gpio12", "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + int-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + nfc_sleep: nfc-sleep-state { + enable-pins { + pins = "gpio12", "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + int-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + sde_dsi_active: sde-dsi-active-state { pins = "gpio6", "gpio11"; function = "gpio"; From 10f91b0dfaf6008e5b4f75a3f4d8a507f4c0d5ad Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 3 Apr 2026 15:58:50 +0200 Subject: [PATCH 034/131] arm64: dts: qcom: sdm845-google-common: Enable NFC Enable NFC controller NXP PN557. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-oneplus-nfc-v3-5-fbdce57d63c1@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-google-common.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi index 693006685776..b2dc0327dff8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -391,6 +391,23 @@ &gpu_zap_shader { firmware-name = "qcom/sdm845/Google/blueline/a630_zap.mbn"; }; +&i2c3 { + status = "okay"; + + nfc@28 { + compatible = "nxp,pn557", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_int_default &nfc_enable_default>; + pinctrl-names = "default"; + }; +}; + &i2c12 { /* Bottom spkr (right) CS35L36 @ 40 */ @@ -459,6 +476,20 @@ &tlmm { gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */ <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */ + nfc_int_default: nfc-int-default-state { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc_enable_default: nfc-enable-default-state { + pins = "gpio25", "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + touchscreen_reset: ts-reset-state { pins = "gpio99"; function = "gpio"; From aa7066248f1b6b2d000d3cc2f64a3fd4930e1b44 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 5 Apr 2026 12:54:55 +0200 Subject: [PATCH 035/131] dt-bindings: arm: qcom: Document Xiaomi Poco F1 Tianma variant Document the panel-specific compatible string for the Tianma variant of the Xiaomi Poco F1: - "xiaomi,beryllium-tianma" and require the generic fallback compatible: - "xiaomi,beryllium" Update the binding to clarify that all panel variants must list the variant-specific compatible first, followed by the generic device compatible, in accordance with DT matching rules. The previous binding documentation did not describe the Tianma variant and did not clearly specify the required fallback compatible, which resulted in inconsistent DTS implementations. No functional differences are currently exposed between Tianma and EBBG variants at the binding level; both rely on the same generic device compatibility for software support. Signed-off-by: David Heidelberg Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-beryllium-compat-string-v2-1-91149be07835@ixit.cz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 24164ba70b6f..d2b87d5eb3d9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -823,6 +823,14 @@ properties: - const: google,zombie-sku514 - const: qcom,sc7280 + - description: Xiaomi Poco F1 + items: + - enum: + - xiaomi,beryllium-ebbg + - xiaomi,beryllium-tianma + - const: xiaomi,beryllium + - const: qcom,sdm845 + - items: - enum: - lenovo,flex-5g @@ -973,8 +981,6 @@ properties: - sony,akatsuki-row - sony,apollo-row - thundercomm,db845c - - xiaomi,beryllium - - xiaomi,beryllium-ebbg - xiaomi,polaris - const: qcom,sdm845 From 68bfaa3fde985a227721b58b32283811d05d5c21 Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Sun, 5 Apr 2026 12:54:56 +0200 Subject: [PATCH 036/131] arm64: dts: qcom: sdm845-xiaomi-beryllium: Append compatible strings Add the generic "xiaomi,beryllium" compatible string after the panel-specific one, so the compatible list follows the required ordering from most specific to most generic. This allows userspace to fall back to the generic Poco F1 compatible when no panel-specific match is present. In particular, hexagonrpcd relies on trying all compatible entries to derive the HexagonFS path, and currently fails when the generic device string is missing. This change modifies the DT ABI: systems describing the EBBG variant will now also match on "xiaomi,beryllium", whereas previously only the panel-specific compatible was exposed. In practice, no upstream userspace distinguishes between Tianma and EBBG panel variants. All known consumers rely only on the generic device identification, and no panel-specific handling exists. Therefore, enabling the generic fallback does not change effective runtime behavior, but fixes userspace that depends on generic matching. The previous state was incomplete, as it omitted the generic device-compatible string required for proper fallback matching. Signed-off-by: Jens Reidel Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260405-beryllium-compat-string-v2-2-91149be07835@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts | 2 +- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts index 2d6f0e382a6c..d157622f84d1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts @@ -6,7 +6,7 @@ / { model = "Xiaomi Pocophone F1 (EBBG)"; - compatible = "xiaomi,beryllium-ebbg", "qcom,sdm845"; + compatible = "xiaomi,beryllium-ebbg", "xiaomi,beryllium", "qcom,sdm845"; }; &display_panel { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts index b58964cde834..71816a9f33b4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts @@ -6,7 +6,7 @@ / { model = "Xiaomi Pocophone F1 (Tianma)"; - compatible = "xiaomi,beryllium", "qcom,sdm845"; + compatible = "xiaomi,beryllium-tianma", "xiaomi,beryllium", "qcom,sdm845"; }; &display_panel { From 3d395de80a46cc2e046c106841c7aa4e1259010a Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Mon, 6 Apr 2026 23:16:11 +0530 Subject: [PATCH 037/131] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC Add the base USB devicetree definitions for Kaanapali platform. The overall chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY (rev. v8) and M31 eUSB2 PHY. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406174613.3388987-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 154 ++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 7cc326aa1a1a..bab654bbd6d0 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3138,6 +3138,77 @@ opp-202000000 { }; }; + usb_hsphy: phy@88e3000 { + compatible = "qcom,kaanapali-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x88e3000 0x0 0x29c>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,kaanapali-qmp-usb3-dp-phy", + "qcom,sm8750-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + camcc: clock-controller@956d000 { compatible = "qcom,kaanapali-camcc"; reg = <0x0 0x0956d000 0x0 0x80000>; @@ -3422,6 +3493,89 @@ dispcc: clock-controller@9ba2000 { #reset-cells = <1>; }; + usb: usb@a600000 { + compatible = "qcom,kaanapali-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + iommus = <&apps_smmu 0x40 0x0>; + + phys = <&usb_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + dma-coherent; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,kaanapali-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, From b2f036a675805812c475c917846320949c2b0c6c Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Mon, 6 Apr 2026 23:16:12 +0530 Subject: [PATCH 038/131] arm64: dts: qcom: kaanpaali: Add USB support for MTP platform Enable USB support on Kaanapali MTP variant. Enable USB controller in device mode till glink node is added. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406174613.3388987-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 07247dc98b70..f9b5b5718b90 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -952,6 +952,11 @@ wifi@0 { }; }; +&pmih0108_e1_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + &pmh0101_flash { status = "okay"; @@ -1321,3 +1326,25 @@ &ufs_mem_phy { status = "okay"; }; + +&usb { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l4f_0p8>; + vdda12-supply = <&vreg_l1d_1p2>; + + phys = <&pmih0108_e1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l1d_1p2>; + vdda-pll-supply = <&vreg_l4f_0p8>; + + status = "okay"; +}; From 01d15f5f69964de3d947abb5e4c550397db68c70 Mon Sep 17 00:00:00 2001 From: Ronak Raheja Date: Mon, 6 Apr 2026 23:16:13 +0530 Subject: [PATCH 039/131] arm64: dts: qcom: kaanpaali: Add USB support for QRD platform Enable USB support on Kaanapali QRD variant. Enable USB controller in device mode till glink node is added. Signed-off-by: Ronak Raheja Signed-off-by: Jingyi Wang Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406174613.3388987-4-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index da0e8f9091c3..55d02219ef4e 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -744,6 +744,11 @@ led@3 { }; }; +&pmih0108_e1_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + &pon_resin { linux,code = ; @@ -816,3 +821,25 @@ &ufs_mem_phy { status = "okay"; }; + +&usb { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l4f_0p8>; + vdda12-supply = <&vreg_l1d_1p2>; + + phys = <&pmih0108_e1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l1d_1p2>; + vdda-pll-supply = <&vreg_l4f_0p8>; + + status = "okay"; +}; From 15bdb0e14551c53fc0f9d0e82690510c88838c3b Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 6 Apr 2026 22:18:25 +0200 Subject: [PATCH 040/131] arm64: dts: qcom: sdm845-oneplus: Enable known blocks and add placeholders We know these devices are present; most of them are supported by downstream and are close to the mainline kernels. This adds placeholders for: - front camera (imx371) - rear cameras (imx519, imx376k) - actuators This is very handy when rebasing the integration tree with support for multiple different blocks at the same time. Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260406-placeholders-v2-1-9cdbe1fc9666@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 04e11448b53a..a6c2519a418d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -442,6 +442,26 @@ vreg_s3c_0p6: smps3 { }; }; +&cci { + status = "okay"; +}; + +&cci_i2c0 { + /* front sony,imx371 @10 */ + + /* rear sony,imx519 @1a */ + + /* rear onnn,lc898217xc @72 */ +}; + +&cci_i2c1 { + /* sa,sa3103 @0d */ + + /* rear sony,imx376k @10 */ + + /* onnn,lc898217xc @74 */ +}; + &cdsp_pas { firmware-name = "qcom/sdm845/OnePlus/enchilada/cdsp.mbn"; From 839d20f9f3da93f65c000187ee68387598bdecb5 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Fri, 3 Apr 2026 02:33:08 -0300 Subject: [PATCH 041/131] dt-bindings: arm: qcom: Add SM7325 Motorola Edge 30 (dubai) Motorola Edge 30 (motorola,dubai) is a smartphone based on the SM7325 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Val Packett Link: https://lore.kernel.org/r/20260403054417.167917-1-val@packett.cool Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d2b87d5eb3d9..2741c07e9f41 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1047,6 +1047,7 @@ properties: - items: - enum: + - motorola,dubai - nothing,spacewar - const: qcom,sm7325 From dd1316efdbc5a998b901b1c5f27da73d45060795 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Fri, 3 Apr 2026 02:33:09 -0300 Subject: [PATCH 042/131] arm64: dts: qcom: Add Motorola Edge 30 (dubai) DTS The Motorola Edge 30 is a smartphone released in 2022. This commit has the following features working: - Display (simplefb) - Touchscreen - Power and volume buttons - Storage (UFS 3.1) - Battery (ADSP battmgr) - USB (Type-C, 2.0, dual-role) - Wi-Fi and Bluetooth (WCN6750 hw1.0) Signed-off-by: Val Packett Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403054417.167917-2-val@packett.cool Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm7325-motorola-dubai.dts | 1456 +++++++++++++++++ 2 files changed, 1457 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 169cc9b9ccd3..cc42829f92eb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -341,6 +341,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts new file mode 100644 index 000000000000..3c836e196b19 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts @@ -0,0 +1,1456 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2026, Val Packett + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include +#include + +#include "sm7325.dtsi" +#include "pm7325.dtsi" +#include "pm7250b.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/ { + model = "Motorola Edge 30"; + compatible = "motorola,dubai", "qcom,sm7325"; + chassis-type = "handset"; + + aliases { + bluetooth0 = &bluetooth; + serial0 = &uart5; + serial1 = &uart7; + wifi0 = &wifi; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_mem>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&kypd_vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pmic-glink { + compatible = "qcom,sm7325-pmic-glink", + "qcom,qcm6490-pmic-glink", + "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@ae000000 { + compatible = "ramoops"; + reg = <0x0 0xae000000 0x0 0xc0000>; + console-size = <0x40000>; + mem-type = <2>; + pmsg-size = <0x40000>; + record-size = <0x3f800>; + }; + + removed@c0000000 { + reg = <0x0 0xc0000000 0x0 0x5100000>; + no-map; + }; + + framebuffer_mem: framebuffer@e1000000 { + reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + thermal-zones { + cam-flash-thermal { + thermal-sensors = <&pmk8350_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-skin-thermal { + thermal-sensors = <&pm7250b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-thermal { + thermal-sensors = <&pmk8350_adc_tm 4>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-thermal { + thermal-sensors = <&pm7250b_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-1-thermal { + thermal-sensors = <&pmk8350_adc_tm 5>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-2-thermal { + thermal-sensors = <&pmk8350_adc_tm 6>; + + /* Reports negative temperature. */ + status = "disabled"; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + + // S2B is really ebi.lvl but it's there for supply map completeness sake. + vreg_s2b_0p7: smpb2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2b_0p7"; + + regulator-min-microvolt = <65535>; + regulator-max-microvolt = <65535>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + wcn6750-pmu { + compatible = "qcom,wcn6750-pmu"; + pinctrl-0 = <&bt_en>; + pinctrl-names = "default"; + vddaon-supply = <&mos_0p95_aon_s10c>; + vddasd-supply = <&vreg_l11c_2p8>; + vddpmu-supply = <&mos_0p95_dig_s10c>; + vddio-supply = <&vdd18_io>; + vddrfa0p8-supply = <&vdd09_pmu_rfa_i>; + vddrfa1p2-supply = <&vdd13_pmu_rfa_i>; + vddrfa1p7-supply = <&vdd19_pmu_rfa_i>; + vddrfa2p2-supply = <&vdd22_wlpa_s1c>; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p952>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_s2b_0p7>; + vdd-l5-supply = <&vreg_s2b_0p7>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p256>; + vdd-l8-supply = <&vreg_s7b_0p952>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p856>; + vdd-l13-supply = <&vreg_s7b_0p952>; + vdd-l14-l16-supply = <&vreg_s8b_1p256>; + + /* + * S2, L4-L5 are ARCs: + * S2 - ebi.lvl, + * L4 - lmx.lvl, + * l5 - lcx.lvl. + * + * L10 are unused. + */ + + vdd19_pmu_rfa_i: + vreg_s1b_1p856: smps1 { + regulator-name = "vreg_s1b_1p856"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + mos_0p95_aon_s10c: + mos_0p95_dig_s10c: + vdd09_pmu_rfa_i: + vreg_s7b_0p952: smps7 { + regulator-name = "vreg_s7b_0p952"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vdd13_pmu_rfa_i: + vreg_s8b_1p256: smps8 { + regulator-name = "vreg_s8b_1p256"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vdd_a_usbhs_3p1: + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p6: ldo3 { + regulator-name = "vreg_l3b_0p6"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = ; + }; + + vdd_a_dsi_0_1p2: + vdd_a_ufs_0_1p2: + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p776: ldo11 { + regulator-name = "vreg_l11b_1p776"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p8: ldo12 { + regulator-name = "vreg_l12b_0p8"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p8: ldo13 { + regulator-name = "vreg_l13b_0p8"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p2: ldo14 { + regulator-name = "vreg_l14b_1p2"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p88: ldo15 { + regulator-name = "vreg_l15b_0p88"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p2: ldo16 { + regulator-name = "vreg_l16b_1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name = "vreg_l17b_1p8"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vdd18_io: + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_s1b_1p856>; + vdd-l2-l8-supply = <&vreg_s1b_1p856>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s7b_0p952>; + + vdd-bob-supply = <&vph_pwr>; + + /* + * S2, S5, S7, S10 are ARCs: + * S2 - cx.lvl, + * S5 - mss.lvl, + * S7 - gfx.lvl, + * S10 - mx.lvl. + */ + + vdd22_wlpa_s1c: + vreg_s1c_2p2: smps1 { + regulator-name = "vreg_s1c_2p2"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s9c_0p676: smps9 { + regulator-name = "vreg_s9c_0p676"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vdd_a_usbhs_1p8: + vdd_qfprom: + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + iovdd_ts: + vreg_l2c_1p8: ldo2 { + regulator-name = "vreg_l2c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdd_ts: + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8_3p0: ldo4 { + regulator-name = "vreg_l4c_1p8_3p0"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8_3p0: ldo5 { + regulator-name = "vreg_l5c_1p8_3p0"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_3p3: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vdd_a_dsi_0_0p9: + vdd_a_ufs_0_core: + vdd_a_usbhs_core: + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + disp_iovcc_1p8: + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + disp_vci_3p0: + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + audio_sw_vcc: + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sm7325/motorola/dubai/a660_zap.mbn"; +}; + +&i2c4 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + interrupts-extended = <&tlmm 6 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&audio_sw_vcc>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&ipa { + firmware-name = "qcom/sm7325/motorola/dubai/yupik_ipa_fws.mbn"; + memory-region = <&ipa_fw_mem>; + + qcom,gsi-loader = "self"; + + status = "okay"; +}; + +&pm7250b_adc { + channel@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "chg_skin_therm"; + }; + + channel@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "conn_therm"; + }; +}; + +&pm7250b_adc_tm { + status = "okay"; + + chg-skin-therm@0 { + reg = <0>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + conn-therm@1 { + reg = <1>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm7250b_gpios { + gpio-line-names = "FG_ALERT_N", /* GPIO_1 */ + "SLAVECP_INT", + "NC", + "NC", + "NC", + "DOUBLER_STAT", + "NC", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "NC"; +}; + +&pm7325_gpios { + gpio-line-names = "PA_THERM1", /* GPIO_1 */ + "NC", + "NC", + "PA_THERM2", + "CBL_PWR_N", + "KYPD_VOL_UP_N", + "NC", + "NC", + "NC", + "NC"; /* GPIO_10 */ + + kypd_vol_up_n: kypd-volp-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + power-source = <1>; + }; +}; + +&pm8350c_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; /* GPIO_9 */ +}; + +&pm8350c_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + cam-flash-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + chg-therm@4 { + reg = <4>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm-1@5 { + reg = <5>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm-2@6 { + reg = <6>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_gpios { + gpio-line-names = "NC", /* GPIO_0 */ + "NC", + "TP_PMK_GPIO_3", + "PMK_OPTION"; /* GPIO_4 */ +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@44 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_xo_therm"; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@145 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_cam_flash_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; + + channel@147 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_chg_therm"; + }; + + channel@14a { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_pa_therm1"; + }; + + channel@14d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_pa_therm2"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-pull-down; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-pull-down; +}; + +&qup_uart5_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7325/motorola/dubai/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7325/motorola/dubai/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7325/motorola/dubai/modem.mbn"; + + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/sm7325/motorola/dubai/wpss.mbn"; + + status = "okay"; +}; + +&rmtfs_mem { + qcom,vmid = , + ; +}; + +&spi13 { + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupts-extended = <&tlmm 81 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vdd_ts>; + vddio-supply = <&iovdd_ts>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_int_n>, <&ts_reset_n>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + gpio-line-names = "NC", /* GPIO_0 */ + "NC", + "NC", + "NC", + "SMARTPA_I2C_SDA", + "SMARTPA_I2C_SCK", + "AUD_4480_DET", + "AUD_4480_INT", + "FASTCHARGE_I2C_SDA", + "FASTCHARGE_I2C_SCL", + "SM_GPSLNA_EN_GPIO10", /* GPIO_10 */ + "NC", + "PERI_I2C_SDA", + "PERI_I2C_SCL", + "NC", + "NC", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "NC", + "DISP_LDO_EN", + "CAM_FW_RST_N", /* GPIO_20 */ + "CAM_RM_RST_N", + "DBG_UART_TXD", + "DBG_UART_RXD", + "TOPSB_INT_N", + "MCAM_LDO_EN", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "UART_BT_RTS_AP_CTS", + "UART_BT_CTS_AP_RTS", + "UART_BT_RX_AP_TX", /* GPIO_30 */ + "UART_BT_TX_AP_RX", + "FRONT_60M_INT", + "FRONT_60M_RST", + "FP_INT", + "FP_RST", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "NFC_SE_SPI_NREST", /* GPIO_40 */ + "NFC_IRQ", + "RF_LDO_GPIO42_EN", + "GOOGLE_KEY_INT", /* no such key exists */ + "DISP_RST_N", + "SB_INT_N", + "HAP_RST_N", + "HAP_INT", + "ESE_SPI_MISO", + "ESE_SPI_MOSI", + "ESE_SPI_CLK", /* GPIO_50 */ + "ESE_SPI_CS", + "TP_SPI_MISO", + "TP_SPI_MOSI", + "TP_SPI_CLK", + "TP_SPI_CS_N", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "HW_ID_1", /* GPIO_60 */ + "HW_ID_2", + "CAM_PMU_EN", + "WIDE_DVDD_LDO_EN", + "CAM_MCLK0", + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "NC", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", /* GPIO_70 */ + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CCI_I2C_SDA3", + "CCI_I2C_SCL3", + "CAM_RT_RST_N", + "CAM_RU_RST_N", + "FCAM_LDO_EN", + "DISP_TE", /* GPIO_80 */ + "TP_INT_N", + "FORCED_USB_BOOT", + "SM_CDC_RST_N", + "WLAN_EN", + "BT_EN", + "WCN_SW_CTRL", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "MOS_AS_EN", /* GPIO_90 */ + "NC", + "", + "NC", + "BT_FM_SLIMBUS_CLK", + "BT_FM_SLIMBUS_DATA", + "NC", + "RFCONN_DET_1", + "RF_CON_DET_2", + "RF_CON_DET_3", + "NC", /* GPIO_100 */ + "NC", + "NC", + "ACCEL_INT", + "NC", + "TP_RST_N", + "NC", + "NC", + "NC", + "UIM2_DATA", + "UIM2_CLK", /* GPIO_110 */ + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "UIM1_PRESENT", + "SM_RFFE0_CLK", + "SM_RFFE0_DATA", + "SM_RFFE1_CLK", + "SM_RFFE1_DATA", /* GPIO_120 */ + "PA_MUTING", + "SM_GRFC5", + "LAA_RX", + "SM_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", + "WLAN_COEX_UART_RX", + "WLAN_COEX_UART_TX", + "NC", + "NC", /* GPIO_130 */ + "SM_GRFC12", + "NC", + "QLINK0_REQUEST", + "QLINK0_ENABLE", + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "USB_CC_DIR", /* GPIO_140 */ + "SAR_INT_N", + "PROX_INT_N", + "", + "SM_SWR_TX_CLK", + "SM_SWR_TX_DATA0", + "SM_SWR_TX_DATA1", + "SM_SWR_RX_CLK", + "SM_SWR_RX_DATA0", + "SM_SWR_RX_DATA1", + "NC", /* GPIO_150 */ + "NC", + "NC", + "NC", + "SB_MI2S_SCK", + "SB_MI2S_WS", + "SB_MI2S_RXDAT_AP_TX", + "SB_MI2S_TXDAT_AP_RX", + "NC", + "SNS_I3C0_SDA", + "SNS_I3C0_SCL", /* GPIO_160 */ + "SSC_I2C4_SDA", + "SSC_I2C4_SCL", + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "NC", + "NC", + "", + "", + "", + "", /* GPIO_170 */ + "SSC_BT_UART4_TX", + "SSC_BT_UART4_RX", + "NC", + "NC"; + gpio-reserved-ranges = <48 4>, /* SPI (eSE - embedded Secure Element) */ + <56 4>; /* SPI (fingerprint reader) */ + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + oled_reset_n: oled-reset-n-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + aw86224_reset_default: aw86224-reset-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + aw86224_int_default: aw86224-int-default-state { + pins = "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + mdp_vsync_p: mdp-vsync-p-state { + pins = "gpio80"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_int_n: ts-int-n-state { + pins = "gpio81"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + bt_en: bt-en-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + ts_reset_n: ts-int-n-state { + pins = "gpio105"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&uart5 { + status = "okay"; +}; + +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + + max-speed = <3200000>; + + qcom,local-bd-address-broken; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p96>; + vcc-max-microamp = <800000>; + + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdd_a_ufs_0_core>; + vdda-pll-supply = <&vdd_a_ufs_0_1p2>; + + status = "okay"; +}; + +&usb_1 { + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + maximum-speed = "high-speed"; + + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vdd_a_usbhs_core>; + vdda18-supply = <&vdd_a_usbhs_1p8>; + vdda33-supply = <&vdd_a_usbhs_3p1>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sm7325/motorola/dubai/vpu20_1v.mbn"; + + status = "okay"; +}; + +&wifi { + qcom,calibration-variant = "Motorola_dubai"; + + status = "okay"; +}; From 3b28947ef1f7630d272c59c0251dfa4e5ce7eb63 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Fri, 3 Apr 2026 12:10:34 +0530 Subject: [PATCH 043/131] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform. The controller is connected via SPI3 and uses a 40 MHz oscillator. Signed-off-by: Viken Dadhaniya Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260403-can-spi-kodiak-dtsi-v1-1-4055e67dd3fc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e393ccf1884a..ceb68a890bf4 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -44,6 +44,14 @@ chosen { stdout-path = "serial0:115200n8"; }; + clocks { + mcp2518fd_osc: can-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + dp-connector { compatible = "dp-connector"; label = "DP"; @@ -1208,6 +1216,20 @@ platform { }; }; +&spi3 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mcp2518fd_osc>; + spi-max-frequency = <14000000>; + vdd-supply = <&vreg_l11c_2p8>; + microchip,xstbyen; + }; +}; + &swr2 { status = "okay"; From 1825ac5e2ad27ad72d1a550f6e19f8cc1ae90afe Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Fri, 3 Apr 2026 20:07:52 +0800 Subject: [PATCH 044/131] arm64: dts: qcom: sc8280xp: Add ADSP FastRPC node Add the FastRPC node to enable offloading compute tasks to the ADSP via the FastRPC framework. Signed-off-by: Pengyu Luo Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260403120753.105869-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 761f229e8f47..ee02acd18856 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2966,6 +2966,33 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "lpass"; qcom,remote-pid = <2>; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x0>; + }; + }; + gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; From 3e6cd0c43cdf678622c19210bd1a70b04c8a79af Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Thu, 2 Apr 2026 15:20:01 +0530 Subject: [PATCH 045/131] arm64: dts: qcom: lemans: add mdss1 display device nodes Add devicetree changes to enable second Mobile Display Subsystem (mdss1), Display Processing Unit(DPU), Display Port(DP), Display clock controller (dispcc1) and eDP PHYs on the Qualcomm Lemans platform. Signed-off-by: Mahadevan P Signed-off-by: Mani Chandana Ballary Kuntumalla Link: https://lore.kernel.org/r/20260402095003.3758176-2-quic_mkuntuma@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 289 ++++++++++++++++++++++++--- 1 file changed, 262 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index fe6e76351823..84a1e5ebbf5e 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5470,7 +5470,7 @@ mdss0_dp1: displayport-controller@af5c000 { phys = <&mdss0_dp1_phy>; phy-names = "dp"; - operating-points-v2 = <&dp1_opp_table>; + operating-points-v2 = <&dp_opp_table>; power-domains = <&rpmhpd SA8775P_MMCX>; #sound-dai-cells = <0>; @@ -5495,30 +5495,6 @@ port@1 { mdss0_dp1_out: endpoint { }; }; }; - - dp1_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; }; }; @@ -7051,6 +7027,265 @@ compute-cb@3 { }; }; + mdss1: display-subsystem@22000000 { + compatible = "qcom,sa8775p-mdss"; + reg = <0x0 0x22000000 0x0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1800 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + display-controller@22001000 { + compatible = "qcom,sa8775p-dpu"; + reg = <0x0 0x22001000 0x0 0x8f000>, + <0x0 0x220b0000 0x0 0x3000>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdss0_mdp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + interrupt-parent = <&mdss1>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu1_intf0_out: endpoint { + remote-endpoint = <&mdss1_dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu1_intf4_out: endpoint { + remote-endpoint = <&mdss1_dp1_in>; + }; + }; + }; + }; + + mdss1_dp0_phy: phy@220c2a00 { + compatible = "qcom,sa8775p-edp-phy"; + reg = <0x0 0x220c2a00 0x0 0x200>, + <0x0 0x220c2200 0x0 0xd0>, + <0x0 0x220c2600 0x0 0xd0>, + <0x0 0x220c2000 0x0 0x1c8>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp1_phy: phy@220c5a00 { + compatible = "qcom,sa8775p-edp-phy"; + reg = <0x0 0x220c5a00 0x0 0x200>, + <0x0 0x220c5200 0x0 0xd0>, + <0x0 0x220c5600 0x0 0xd0>, + <0x0 0x220c5000 0x0 0x1c8>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp0: displayport-controller@22154000 { + compatible = "qcom,sa8775p-dp"; + reg = <0x0 0x22154000 0x0 0x104>, + <0x0 0x22154200 0x0 0x0c0>, + <0x0 0x22155000 0x0 0x770>, + <0x0 0x22156000 0x0 0x09c>, + <0x0 0x22157000 0x0 0x09c>, + <0x0 0x22158000 0x0 0x09c>, + <0x0 0x22159000 0x0 0x09c>, + <0x0 0x2215a000 0x0 0x23c>, + <0x0 0x2215b000 0x0 0x23c>; + + interrupt-parent = <&mdss1>; + interrupts = <12>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>; + phys = <&mdss1_dp0_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss1_dp0_in: endpoint { + remote-endpoint = <&dpu1_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss1_dp0_out: endpoint { }; + }; + }; + }; + + mdss1_dp1: displayport-controller@2215c000 { + compatible = "qcom,sa8775p-dp"; + reg = <0x0 0x2215c000 0x0 0x104>, + <0x0 0x2215c200 0x0 0x0c0>, + <0x0 0x2215d000 0x0 0x770>, + <0x0 0x2215e000 0x0 0x09c>, + <0x0 0x2215f000 0x0 0x09c>, + <0x0 0x22160000 0x0 0x09c>, + <0x0 0x22161000 0x0 0x09c>, + <0x0 0x22162000 0x0 0x23c>, + <0x0 0x22163000 0x0 0x23c>; + + interrupt-parent = <&mdss1>; + interrupts = <13>; + + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp1_phy 1>; + phys = <&mdss1_dp1_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss1_dp1_in: endpoint { + remote-endpoint = <&dpu1_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss1_dp1_out: endpoint { }; + }; + }; + + }; + }; + dispcc1: clock-controller@22100000 { compatible = "qcom,sa8775p-dispcc1"; reg = <0x0 0x22100000 0x0 0x20000>; @@ -7058,13 +7293,13 @@ dispcc1: clock-controller@22100000 { <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>, + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd SA8775P_MMCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; ethernet1: ethernet@23000000 { From fcc1a19f5bd5623c448e54b2ea6d50249abea77a Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Thu, 2 Apr 2026 15:20:02 +0530 Subject: [PATCH 046/131] arm64: dts: qcom: lemans-ride: Enable mdss1 display Port This change enables DP controllers, DPTX0 and DPTX1 alongside their corresponding PHYs of mdss1 which corresponds to edp2 and edp3. Signed-off-by: Mani Chandana Ballary Kuntumalla Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402095003.3758176-3-quic_mkuntuma@quicinc.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/lemans-ride-common.dtsi | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 679e045a6d49..40f88498999b 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -182,6 +182,30 @@ dp1_connector_in: endpoint { }; }; + dp2-connector { + compatible = "dp-connector"; + label = "eDP2"; + type = "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "eDP3"; + type = "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_out>; + }; + }; + }; + dp-dsi0-connector { compatible = "dp-connector"; label = "DSI0"; @@ -641,6 +665,50 @@ &mdss0_dsi1_phy { status = "okay"; }; +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 = <&dp2_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp2_connector_in>; +}; + +&mdss1_dp0_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 = <&dp3_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp3_connector_in>; +}; + +&mdss1_dp1_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + &pmm8654au_0_gpios { gpio-line-names = "DS_EN", "POFF_COMPLETE", @@ -818,6 +886,18 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins = "gpio104"; + function = "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins = "gpio103"; + function = "edp3_hot"; + bias-disable; + }; + io_expander_intr_active: io-expander-intr-active-state { pins = "gpio98"; function = "gpio"; From f0b64466e2896020ff2bcaa512bbcc4fea847635 Mon Sep 17 00:00:00 2001 From: Vishnu Saini Date: Thu, 2 Apr 2026 15:20:03 +0530 Subject: [PATCH 047/131] arm64: dts: qcom: lemans-evk-ifp-mezzanine: Enable mdss1 display Port Enable DP controllers, DPTX0 and DPTX1 alongside their corresponding PHYs of mdss1 which corresponds to eDP2 and eDP3. Signed-off-by: Vishnu Saini Signed-off-by: Mani Chandana Ballary Kuntumalla Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402095003.3758176-4-quic_mkuntuma@quicinc.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 268fc6b05d4b..44bd9b1a1765 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -11,6 +11,30 @@ &{/} { model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine"; + dp2-connector { + compatible = "dp-connector"; + label = "eDP2"; + type = "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "eDP3"; + type = "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_out>; + }; + }; + }; + vreg_0p9: regulator-0v9 { compatible = "regulator-fixed"; regulator-name = "VREG_0P9"; @@ -141,6 +165,44 @@ mac_addr1: mac-addr@0 { }; }; +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 = <&dp2_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 = <&dp3_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss1_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp2_connector_in>; +}; + +&mdss1_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp3_connector_in>; +}; + +&mdss1_dp0_phy { + status = "okay"; +}; + +&mdss1_dp1_phy { + status = "okay"; +}; + &pcie0 { iommu-map = <0x0 &pcie_smmu 0x0 0x1>, <0x100 &pcie_smmu 0x1 0x1>, @@ -235,6 +297,18 @@ &serdes1 { }; &tlmm { + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins = "gpio104"; + function = "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins = "gpio103"; + function = "edp3_hot"; + bias-disable; + }; + ethernet1_default: ethernet1-default-state { ethernet1-mdc-pins { pins = "gpio20"; From f8874bc5792134b7bdda9706e2a48e6285da3664 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Thu, 7 May 2026 09:42:16 +0300 Subject: [PATCH 048/131] arm64: dts: qcom: agatti: add higher OPP levels Add additional OPP entries for the Agatti platform to support higher operating frequencies as specified in the hardware documentation. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Link: https://lore.kernel.org/r/20260507-iris-ar50lt-v1-16-d22cccedc3e2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 8a7337239b1e..fd40aa59878a 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -2455,6 +2455,16 @@ opp-240000000 { opp-hz = /bits/ 64 <240000000>; required-opps = <&rpmpd_opp_svs>; }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; }; }; From 5a95bd4771ffd591e810717e1c6dcc568ebf45d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Apr 2026 15:51:43 +0200 Subject: [PATCH 049/131] arm64: dts: qcom: eliza: Add QCE crypto Add nodes for the BAM DAM and QCE crypto engine. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Kuldeep Singh Reviewed-by: Konrad Dybcio Reviewed-by: Harshal Dev Link: https://lore.kernel.org/r/20260407-crypto-qcom-eliza-v1-2-40f61a1454a2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 4a7a0ac40ce6..24c680795481 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -846,6 +846,38 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + + interrupts = ; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,eliza-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From 208af18362e01f59bfe4a71a8606b09acb673cd0 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Mon, 6 Apr 2026 02:10:15 +0000 Subject: [PATCH 050/131] arm64: dts: qcom: milos: Add QCrypto nodes Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Alexander Koskovich Reviewed-by: Kuldeep Singh Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260405-milos-qce-v1-2-6996fb0b8a9c@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 347afce18924..f09b30ea96ee 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1278,6 +1278,38 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + + interrupts = ; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,milos-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From 93e08fdc55f227847dc9b249fd5eb43403e7e8b9 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 5 May 2026 13:10:04 +0530 Subject: [PATCH 051/131] arm64: dts: qcom: glymur: Add crypto engine and BAM On almost all Qualcomm platforms, including Glymur, there is a Crypto engine IP block to which the CPU can off-load cryptographic computations for achieving acceleration. The engine is also DMA capable due to the presence of an associated Bus Access Manager (BAM) module. Describe the Crypto engine and its BAM. Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 0c5cb8532b20..c8f7eab29606 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3675,6 +3675,32 @@ pcie3b_phy: phy@f10000 { status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu 0x80 0x0>, + <&apps_smmu 0x81 0x0>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <20>; + qcom,num-ees = <4>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", + "tx"; + iommus = <&apps_smmu 0x80 0x0>, + <&apps_smmu 0x81 0x0>; + interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From ef4d269e5566ec8d32de149c91f1c907ec9b9511 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 29 Apr 2026 22:31:39 +0530 Subject: [PATCH 052/131] arm64: dts: qcom: talos: Add QSPI support The Talos (QCS615) platform includes a QSPI controller used for accessing external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and the QSPI controller node to enable support for this hardware. Reviewed-by: Konrad Dybcio Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260429-spi-nor-v5-4-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index ff5afbfce2a4..8c7ea369a332 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -531,6 +531,25 @@ cdsp_smp2p_in: slave-kernel { }; + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-60000000 { + opp-hz = /bits/ 64 <60000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-133250000 { + opp-hz = /bits/ 64 <133250000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-266500000 { + opp-hz = /bits/ 64 <266500000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; @@ -1610,6 +1629,34 @@ cci_i2c1_default: cci-i2c1-default-state { bias-pull-up; }; + qspi_cs0: qspi-cs0-state { + pins = "gpio44"; + function = "qspi"; + bias-disable; + drive-strength = <6>; + }; + + qspi_data0123: qspi-data0123-state { + pins = "gpio45", "gpio46", "gpio47", "gpio49"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + + qspi_clk: qspi-clk-state { + pins = "gpio48"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + + qspi_cs1: qspi-cs1-state { + pins = "gpio50"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -3896,6 +3943,39 @@ opp-202000000 { }; }; + qspi: spi@88df000 { + compatible = "qcom,qcs615-qspi", + "qcom,qspi-v1"; + reg = <0x0 0x088df000 0x0 0x1000>; + + interrupts = ; + + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", + "core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qspi-config", + "qspi-memory"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qspi_opp_table>; + + iommus = <&apps_smmu 0x160 0x0>; + + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + dc_noc: interconnect@9160000 { reg = <0x0 0x09160000 0x0 0x3200>; compatible = "qcom,qcs615-dc-noc"; From d2ed3f777f81989a7af6029dee59decad9f488d2 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 29 Apr 2026 22:31:40 +0530 Subject: [PATCH 053/131] arm64: dts: qcom: qcs615-ride: Enable QSPI and NOR flash The QCS615 Ride board has a SPI-NOR flash connected to the QSPI controller on CS0. Enable the QSPI controller and add the corresponding SPI-NOR flash node to allow the system to access it. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260429-spi-nor-v5-5-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 831002789838..51b13b492472 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -498,6 +498,18 @@ &pon_resin { status = "okay"; }; +&qspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From 45287b9e5e28f10ec910480635d4f239154d4120 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 29 Apr 2026 22:31:41 +0530 Subject: [PATCH 054/131] arm64: dts: qcom: kodiak: Add QSPI memory interconnect path Add the missing QSPI-to-memory interconnect path alongside the existing configuration path. Without it, the interconnect framework cannot vote for the bandwidth required by QSPI DMA data transfers. Reviewed-by: Konrad Dybcio Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260429-spi-nor-v5-6-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 988ca5f7c8a0..2dbeb15c84b7 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -4418,9 +4418,12 @@ qspi: spi@88dc000 { clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; - interconnects = <&gem_noc MASTER_APPSS_PROC 0 - &cnoc2 SLAVE_QSPI_0 0>; - interconnect-names = "qspi-config"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc2 SLAVE_QSPI_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QSPI_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qspi-config", + "qspi-memory"; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qspi_opp_table>; status = "disabled"; From 8289feadbcbc1b0458a9e81d0eca42f97b28bbe3 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 29 Apr 2026 22:31:42 +0530 Subject: [PATCH 055/131] arm64: dts: qcom: sc7180: Add QSPI memory interconnect path Add the missing QSPI-to-memory interconnect path alongside the existing configuration path. Without this path, the interconnect framework cannot correctly vote for the bandwidth required by QSPI DMA data transfers. Reviewed-by: Konrad Dybcio Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20260429-spi-nor-v5-7-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a4b17564469e..8341a7c4a4c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2866,9 +2866,12 @@ qspi: spi@88dc000 { clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; - interconnects = <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QSPI_0 0>; - interconnect-names = "qspi-config"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QSPI_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qspi-config", + "qspi-memory"; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qspi_opp_table>; status = "disabled"; From db6ae6650cfdf085e21a477c25386125075b2351 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:08 +0300 Subject: [PATCH 056/131] dt-bindings: firmware: qcom: scm: add CP_ADSP_SHARED VMID CP_ADSP_SHARED is used in FastRPC driver for older SoC's such as sdm660 for interacting with ADSP memory region [1] [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/drivers/char/adsprpc.c#L3602 Acked-by: Krzysztof Kozlowski Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-1-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/firmware/qcom,scm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h index 6de8b08e1e79..0d29d8d4829c 100644 --- a/include/dt-bindings/firmware/qcom,scm.h +++ b/include/dt-bindings/firmware/qcom,scm.h @@ -35,5 +35,6 @@ #define QCOM_SCM_VMID_NAV 0x2B #define QCOM_SCM_VMID_TVM 0x2D #define QCOM_SCM_VMID_OEMVM 0x31 +#define QCOM_SCM_VMID_CP_ADSP_SHARED 0x33 #endif From 708ab9d3bc5b74eeee767c678366624d3c02a4ec Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:09 +0300 Subject: [PATCH 057/131] arm64: dts: qcom: sdm660: set cdsp compute-cbs' regs properly Changing FastRPC compute-cbs' reg values to matching iommu streams solves SMMU translation errors when trying to use FastRPC on CDSP so change FastRPC compute-cbs' reg values that way Fixes: c0c32a9e3493 ("arm64: dts: qcom: sdm630/660: Add CDSP-related nodes") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Ekansh Gupta Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-2-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 3fd6dd82a992..0fca9662c64a 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -350,57 +350,57 @@ fastrpc { #address-cells = <1>; #size-cells = <0>; + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&cdsp_smmu 3>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&cdsp_smmu 4>; + }; + compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; - iommus = <&cdsp_smmu 3>; + iommus = <&cdsp_smmu 5>; }; compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; - iommus = <&cdsp_smmu 4>; + iommus = <&cdsp_smmu 6>; }; compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; - iommus = <&cdsp_smmu 5>; + iommus = <&cdsp_smmu 7>; }; compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; - iommus = <&cdsp_smmu 6>; + iommus = <&cdsp_smmu 8>; }; compute-cb@9 { compatible = "qcom,fastrpc-compute-cb"; reg = <9>; - iommus = <&cdsp_smmu 7>; + iommus = <&cdsp_smmu 9>; }; compute-cb@10 { compatible = "qcom,fastrpc-compute-cb"; reg = <10>; - iommus = <&cdsp_smmu 8>; + iommus = <&cdsp_smmu 10>; }; compute-cb@11 { compatible = "qcom,fastrpc-compute-cb"; reg = <11>; - iommus = <&cdsp_smmu 9>; - }; - - compute-cb@12 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <12>; - iommus = <&cdsp_smmu 10>; - }; - - compute-cb@13 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <13>; iommus = <&cdsp_smmu 11>; }; }; From e8e1fb5c703fc6962103ffdc60830df99351c139 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:10 +0300 Subject: [PATCH 058/131] arm64: dts: qcom: sdm630: set adsp compute-cbs' regs properly Changing FastRPC compute-cbs' reg values to matching iommu streams solves SMMU translation errors when trying to use FastRPC on ADSP so change FastRPC compute-cbs' reg values that way Fixes: af2ce7296643 ("arm64: dts: qcom: sdm630: Add FastRPC nodes to ADSP") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Ekansh Gupta Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-3-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index bef3213165d6..4b47efdb57b2 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2459,27 +2459,27 @@ fastrpc { #address-cells = <1>; #size-cells = <0>; - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&lpass_smmu 3>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&lpass_smmu 7>; - }; - compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; + iommus = <&lpass_smmu 3>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&lpass_smmu 7>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; iommus = <&lpass_smmu 8>; }; - compute-cb@4 { + compute-cb@9 { compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; + reg = <9>; iommus = <&lpass_smmu 9>; }; }; From ce414263e9ebe5080381a50cbdf9065c29816202 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:11 +0300 Subject: [PATCH 059/131] arm64: dts: qcom: sdm630: describe adsp_mem region properly Downstream [1] this region is marked as shared, reusable and dynamic so describe it that way. [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L448 Fixes: b190fb010664 ("arm64: dts: qcom: sdm630: Add sdm630 dts file") Cc: stable@vger.kernel.org Reviewed-by: Ekansh Gupta Reviewed-by: Dmitry Baryshkov Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-4-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 4b47efdb57b2..252c301f0156 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -494,9 +494,12 @@ venus_region: venus@9f800000 { no-map; }; - adsp_mem: adsp-region@f6000000 { - reg = <0x0 0xf6000000 0x0 0x800000>; - no-map; + adsp_mem: adsp-region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + reusable; }; qseecom_mem: qseecom-region@f6800000 { From dc11a2824f059de67f499d2b9be82b602433b848 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Wed, 29 Apr 2026 12:30:12 +0300 Subject: [PATCH 060/131] arm64: dts: qcom: sdm630: assign adsp_mem region to ADSP FastRPC node Downstream [1] ADSP FastRPC node has the adsp_mem region assigned, so assign it to the ADSP FastRPC node. [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L1693 Reviewed-by: Dmitry Baryshkov Reviewed-by: Ekansh Gupta Reviewed-by: Konrad Dybcio Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-5-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 252c301f0156..a41ba0da380b 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2458,6 +2458,9 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + memory-region = <&adsp_mem>; + qcom,vmids = ; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; From 113343d57607937102d843775560fea0ce5cbe6f Mon Sep 17 00:00:00 2001 From: Amit Pundir Date: Tue, 7 Apr 2026 08:43:56 +0200 Subject: [PATCH 061/131] arm64: dts: qcom: sdm845-xiaomi-beryllium: Enable ath10k host-cap skip quirk The Wi-Fi firmware used on Xiaomi Poco F1 (beryllium) phone doesn't support the host-capability QMI request, so add a quirk to skip it on this device. Signed-off-by: Amit Pundir Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260407-skip-host-cam-qmi-req-v5-3-dfa8a05c6538@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index a6ee3dd171de..9b7fdbca9e1c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -677,5 +677,6 @@ &wifi { vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,calibration-variant = "xiaomi_beryllium"; + qcom,snoc-host-cap-skip-quirk; }; From 08569936a11b8ed20f95783d80d1ba2f4e93fa93 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Apr 2026 22:18:40 +0200 Subject: [PATCH 062/131] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map Make the complicated interrupt-map property (with multiple '0' entries) a bit more readable by using known define for GIC_SPI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260407201839.25759-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 32 ++++++++++++------------- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 8 +++---- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 +++---- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 +++---- 4 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index c8f7eab29606..2378b7a4a30d 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2776,10 +2776,10 @@ pcie4: pci@1bf0000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, @@ -2986,10 +2986,10 @@ pcie5: pci@1b40000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_5_AUX_CLK>, <&gcc GCC_PCIE_5_CFG_AHB_CLK>, @@ -3252,10 +3252,10 @@ pcie6: pci@1c00000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_6_AUX_CLK>, <&gcc GCC_PCIE_6_CFG_AHB_CLK>, @@ -3462,10 +3462,10 @@ pcie3b: pci@1b80000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index bab654bbd6d0..bcd1cee31356 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2313,10 +2313,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommu-map = <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d41b5c470c48..347706011637 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -955,10 +955,10 @@ pcie0: pcie@1c00000 { "msi7", "global"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 417f28d8c919..5921f83aafac 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5210,10 +5210,10 @@ pcie0: pcie@1c00000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, From d962cd7c49fa210e53dfeed04028ac9ef112ae70 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Thu, 9 Apr 2026 11:01:55 +0800 Subject: [PATCH 063/131] arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM pins This patch adds the Generic Pack Router (GPR) node together with Audio Process Manager (APM) and Proxy Resource Manager (PRM) audio service nodes to the Talos device tree description. It also introduces MI2S1 pinctrl states for data0, data1, sck, and ws lines, grouped into a single entry at the SoC-level DTSI for better reuse and clarity. Reviewed-by: Konrad Dybcio Signed-off-by: Le Qi Link: https://lore.kernel.org/r/20260409030156.155455-2-le.qi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 54 +++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 8c7ea369a332..fb1bbc51bb8a 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -1657,6 +1658,20 @@ qspi_cs1: qspi-cs1-state { drive-strength = <6>; }; + mi2s1_pins: mi2s1-state { + pins = "gpio108", "gpio109", "gpio110", "gpio111"; + function = "mi2s_1"; + drive-strength = <8>; + bias-disable; + }; + + mi2s_mclk: mi2s-mclk-state { + pins = "gpio122"; + function = "mclk2"; + drive-strength = <8>; + bias-disable; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -5212,6 +5227,45 @@ compute-cb@6 { dma-coherent; }; }; + + gpr: gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1721 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; From 141d7ea5036e70f670aba1e6704be74552a3c964 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Thu, 9 Apr 2026 11:01:56 +0800 Subject: [PATCH 064/131] arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codec Add the sound card node for QCS615 Talos EVK with DA7212 codec connected over the Primary MI2S interface. The configuration enables headphone playback and headset microphone capture, both of which have been tested to work. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Le Qi Link: https://lore.kernel.org/r/20260409030156.155455-3-le.qi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos-evk.dts | 56 ++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/qcom/talos-evk.dts index af100e22beee..b7f514fbc7b2 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "talos-evk-som.dtsi" +#include / { model = "Qualcomm QCS615 IQ 615 EVK"; @@ -40,6 +41,46 @@ hdmi_con_out: endpoint { }; }; + sound { + compatible = "qcom,qcs615-sndcard"; + model = "TALOS-EVK"; + + pinctrl-0 = <&mi2s1_pins>, <&mi2s_mclk>; + pinctrl-names = "default"; + + pri-mi2s-capture-dai-link { + link-name = "Primary MI2S Capture"; + + codec { + sound-dai = <&codec_da7212>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + pri-mi2s-playback-dai-link { + link-name = "Primary MI2S Playback"; + + codec { + sound-dai = <&codec_da7212>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vreg_v1p8_out: regulator-v1p8-out { compatible = "regulator-fixed"; regulator-name = "vreg-v1p8-out"; @@ -109,6 +150,21 @@ adv7535_out: endpoint { }; }; +&i2c5 { + status = "okay"; + + codec_da7212: codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_2 LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + VDDA-supply = <&vreg_v1p8_out>; + VDDIO-supply = <&vreg_v1p8_out>; + VDDMIC-supply = <&vreg_v3p3_out>; + }; +}; + &mdss_dsi0_out { remote-endpoint = <&adv7535_in>; data-lanes = <0 1 2 3>; From 8222873cd4698627c08bffb2e40ba6f5a008fe32 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 31 Mar 2026 17:01:47 +0800 Subject: [PATCH 065/131] arm64: dts: qcom: lemans: Move PCIe devices into soc node These PCIe devices with MMIO address should be inside soc node rather than outside. Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Signed-off-by: Shawn Guo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260331090147.18522-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 692 +++++++++++++-------------- 1 file changed, 346 insertions(+), 346 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 84a1e5ebbf5e..bc7b4f65ad5e 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2694,6 +2694,352 @@ mmss_noc: interconnect@17a0000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pcie@1c00000 { + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + status = "disabled"; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x1fe00000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + num-lanes = <2>; + linux,pci-domain = <0>; + + status = "disabled"; + }; + + pcie0_phy: phy@1c04000 { + compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x1c04000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pcie@1c10000 { + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <4>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie1_ep: pcie-ep@1c10000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x1fe00000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x80 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + num-lanes = <4>; + linux,pci-domain = <1>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x1c14000 0x0 0x4000>; + + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; @@ -8836,350 +9182,4 @@ turing_llm_tpdm_out: endpoint { }; }; }; - - pcie0: pcie@1c00000 { - compatible = "qcom,pcie-sa8775p"; - reg = <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf20>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x4000>, - <0x0 0x40100000 0x0 0x100000>, - <0x0 0x01c03000 0x0 0x1000>; - reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - bus-range = <0x00 0xff>; - - dma-coherent; - - linux,pci-domain = <0>; - num-lanes = <2>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>, - <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; - reset-names = "pci", - "link_down"; - - power-domains = <&gcc PCIE_0_GDSC>; - - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; - eq-presets-16gts = /bits/ 8 <0x55 0x55>; - - status = "disabled"; - - pcieport0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - }; - - pcie0_ep: pcie-ep@1c00000 { - compatible = "qcom,sa8775p-pcie-ep"; - reg = <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf20>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x4000>, - <0x0 0x40200000 0x0 0x1fe00000>, - <0x0 0x01c03000 0x0 0x1000>, - <0x0 0x40005000 0x0 0x2000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio", "dma"; - - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - interrupts = , - , - ; - - interrupt-names = "global", "doorbell", "dma"; - - interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - dma-coherent; - iommus = <&pcie_smmu 0x0000 0x7f>; - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - num-lanes = <2>; - linux,pci-domain = <0>; - - status = "disabled"; - }; - - pcie0_phy: phy@1c04000 { - compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; - reg = <0x0 0x1c04000 0x0 0x2000>; - - clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - #clock-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - - pcie1: pcie@1c10000 { - compatible = "qcom,pcie-sa8775p"; - reg = <0x0 0x01c10000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf20>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x4000>, - <0x0 0x60100000 0x0 0x100000>, - <0x0 0x01c13000 0x0 0x1000>; - reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; - bus-range = <0x00 0xff>; - - dma-coherent; - - linux,pci-domain = <1>; - num-lanes = <4>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>, - <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; - reset-names = "pci", - "link_down"; - - power-domains = <&gcc PCIE_1_GDSC>; - - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; - eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; - - status = "disabled"; - - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - }; - - pcie1_ep: pcie-ep@1c10000 { - compatible = "qcom,sa8775p-pcie-ep"; - reg = <0x0 0x01c10000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf20>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x4000>, - <0x0 0x60200000 0x0 0x1fe00000>, - <0x0 0x01c13000 0x0 0x1000>, - <0x0 0x60005000 0x0 0x2000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio", "dma"; - - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - interrupts = , - , - ; - - interrupt-names = "global", "doorbell", "dma"; - - interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - dma-coherent; - iommus = <&pcie_smmu 0x80 0x7f>; - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - num-lanes = <4>; - linux,pci-domain = <1>; - - status = "disabled"; - }; - - pcie1_phy: phy@1c14000 { - compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; - reg = <0x0 0x1c14000 0x0 0x4000>; - - clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; }; From 4eacad2d8e3bd1115a65fd62ce5e08825706fa52 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 8 Apr 2026 19:41:12 -0700 Subject: [PATCH 066/131] arm64: dts: qcom: sdm845-lg-common: Add camera flash Camera doesn't work yet (imx351), but we can use the flash as a flashlight. Reviewed-by: Konrad Dybcio Signed-off-by: Paul Sajna Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-1-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 71d070619ad7..9d82961d527e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -496,6 +496,19 @@ &pm8998_resin { status = "okay"; }; +&pmi8998_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <2>; + led-max-microamp = <100000>; + flash-max-microamp = <500000>; + flash-max-timeout-us = <500000>; + }; +}; + &pmi8998_lpg { status = "okay"; From d2735f569053092ca2a47367dce1594b985409e5 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 8 Apr 2026 19:41:13 -0700 Subject: [PATCH 067/131] arm64: dts: qcom: sdm845-lg-common: Change ipa gsi-loader to 'self', add memory-region The modem firmware for this device doesn't preload the IPA firmware and requires the OS handles that instead. Set qcom,gsi-loader = "self" to reflect that. Ensure the ipa uses the correct memory. ipa 1e40000.ipa: channel 4 limited to 256 TREs ipa 1e40000.ipa: IPA driver initialized ipa 1e40000.ipa: received modem starting event ipa 1e40000.ipa: received modem running event Reviewed-by: Konrad Dybcio Signed-off-by: Paul Sajna Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-2-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 9d82961d527e..85dc4468b6c4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -473,7 +473,9 @@ &gpu { }; &ipa { - qcom,gsi-loader = "modem"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + status = "okay"; }; From 3f779220c64796df483c4cd47154d4ff1104a2e2 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 8 Apr 2026 19:41:14 -0700 Subject: [PATCH 068/131] arm64: dts: qcom: sdm845-lg-{judyln, judyp}: Reference memory region in fb To prevent duplicating the framebuffer address and size point out the existing framebuffer memory region instead of specifying the address manually. Reviewed-by: Konrad Dybcio Signed-off-by: Paul Sajna Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-3-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 3 +-- arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 85dc4468b6c4..86cf4eb44084 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -98,8 +98,7 @@ spss_mem: memory@99000000 { no-map; }; - /* Framebuffer region */ - memory@9d400000 { + framebuffer_mem: memory@9d400000 { reg = <0x0 0x9d400000 0x0 0x2400000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts index adf41aa0146a..349faa123ff1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -14,9 +14,9 @@ / { compatible = "lg,judyln", "qcom,sdm845"; chosen { - framebuffer@9d400000 { + framebuffer { compatible = "simple-framebuffer"; - reg = <0x0 0x9d400000 0x0 (1440 * 3120 * 4)>; + memory-region = <&framebuffer_mem>; width = <1440>; height = <3120>; stride = <(1440 * 4)>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts index d244ebdd17be..44e762f78e95 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts @@ -14,9 +14,9 @@ / { compatible = "lg,judyp", "qcom,sdm845"; chosen { - framebuffer@9d400000 { + framebuffer { compatible = "simple-framebuffer"; - reg = <0x0 0x9d400000 0x0 (1440 * 2880 * 4)>; + memory-region = <&framebuffer_mem>; width = <1440>; height = <2880>; stride = <(1440 * 4)>; From 0f7c65c11f59332ec6d02bf0482a283510efd03a Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 8 Apr 2026 19:41:15 -0700 Subject: [PATCH 069/131] arm64: dts: qcom: sdm845-lg: Enable qcom,snoc-host-cap-skip-quirk The WCN3990 firmware for judyln does not respond to the request for host capabilities. Add the devicetree quirk to skip this request. Signed-off-by: Paul Sajna Reviewed-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-4-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 86cf4eb44084..e0c3566761bf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -694,5 +694,7 @@ &wifi { vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + qcom,snoc-host-cap-skip-quirk; + status = "okay"; }; From bde860892c92a43624a7bcf932a1d375b1ad43eb Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Thu, 16 Apr 2026 22:42:00 -0700 Subject: [PATCH 070/131] arm64: dts: qcom: purwa: Add EL2 overlay for purwa-iot-evk Add support for building an EL2 combined DTB for the purwa-iot-evk in the Qualcomm DTS Makefile. The new purwa-iot-evk-el2.dtb is generated by combining the base purwa-iot-evk.dtb with the x1-el2.dtbo overlay, enabling EL2-specific configurations required by the platform. Signed-off-by: Xin Liu Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260417054200.2402281-1-xin.liu@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cc42829f92eb..35252ea586a5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -158,6 +158,10 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk.dtb + +purwa-iot-evk-el2-dtbs := purwa-iot-evk.dtb x1-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb From 630398127110753474576cbc0cd4ad102b18005e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 30 Apr 2026 09:10:44 +0200 Subject: [PATCH 071/131] arm64: dts: qcom: sm6350: add LPASS LPI pin controller Add LPASS LPI pinctrl node required for audio functionality on SM6350. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 034545d2af2d..d6adf68563cb 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1450,6 +1450,72 @@ compute-cb@5 { }; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; + reg = <0x0 0x033c0000 0x0 0x20000>, + <0x0 0x03550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + i2s1_active: i2s1-active-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + + i2s1_sleep: i2s1-sleep-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-619.0", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, From b1b08554e3be97712febad9d4d9ad617a1a32af1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 30 Apr 2026 09:10:45 +0200 Subject: [PATCH 072/131] arm64: defconfig: Enable LPASS LPI pin controller for SM6350 Build the LPASS LPI pin controller driver for SM6350 as module, which is required for audio functionality on boards such as the Fairphone 4. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-5-81d068025b97@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d905a0777f93..1f0cd5c22537 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -703,6 +703,7 @@ CONFIG_PINCTRL_LPASS_LPI=m CONFIG_PINCTRL_MILOS_LPASS_LPI=m CONFIG_PINCTRL_SC7280_LPASS_LPI=m CONFIG_PINCTRL_SM6115_LPASS_LPI=m +CONFIG_PINCTRL_SM6350_LPASS_LPI=m CONFIG_PINCTRL_SM8250_LPASS_LPI=m CONFIG_PINCTRL_SM8450_LPASS_LPI=m CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m From 627aab9bfe03613c9f0142d5a70faa7ff9634569 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 28 Apr 2026 15:32:29 +0300 Subject: [PATCH 073/131] arm64: dts: qcom: glymur-crd: Enable LID sensor The Glymur CRD has a Hall-effect sensor used for detecting when the lid is opened or closed. Describe it as an SW_LID gpio-key switch. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260428-glymur-dts-add-lid-sensor-v1-1-470cc168e70a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 2852d257ac8c..357d4ad8380a 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -10,6 +10,8 @@ #include "pmk8850.dtsi" /* SPMI0: SID-0 */ #include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ +#include + / { model = "Qualcomm Technologies, Inc. Glymur CRD"; compatible = "qcom,glymur-crd", "qcom,glymur"; @@ -44,7 +46,7 @@ sleep_clk: sleep-clk { gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&key_vol_up_default>; + pinctrl-0 = <&key_vol_up_default>, <&hall_int_n_default>; pinctrl-names = "default"; key-volume-up { @@ -55,6 +57,15 @@ key-volume-up { linux,can-disable; wakeup-source; }; + + switch-lid { + label = "lid"; + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; }; vreg_nvme: regulator-nvme { @@ -565,6 +576,12 @@ &tlmm { <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; From f5fb358c7d9161a6abfd2c619b2999c7e51cd2fe Mon Sep 17 00:00:00 2001 From: Haritha S K Date: Thu, 7 May 2026 11:59:50 +0530 Subject: [PATCH 074/131] arm64: dts: qcom: glymur: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Haritha S K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-glymur_cpu_freq-v1-1-d566cc1d32c3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 2378b7a4a30d..65c8e9233354 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -39,6 +39,7 @@ cpu0: cpu@0 { power-domains = <&cpu_pd0>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -55,6 +56,7 @@ cpu1: cpu@100 { power-domains = <&cpu_pd1>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -65,6 +67,7 @@ cpu2: cpu@200 { power-domains = <&cpu_pd2>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -75,6 +78,7 @@ cpu3: cpu@300 { power-domains = <&cpu_pd3>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -85,6 +89,7 @@ cpu4: cpu@400 { power-domains = <&cpu_pd4>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -95,6 +100,7 @@ cpu5: cpu@500 { power-domains = <&cpu_pd5>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu6: cpu@10000 { @@ -105,6 +111,7 @@ cpu6: cpu@10000 { power-domains = <&cpu_pd6>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -121,6 +128,7 @@ cpu7: cpu@10100 { power-domains = <&cpu_pd7>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu8: cpu@10200 { @@ -131,6 +139,7 @@ cpu8: cpu@10200 { power-domains = <&cpu_pd8>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu9: cpu@10300 { @@ -141,6 +150,7 @@ cpu9: cpu@10300 { power-domains = <&cpu_pd9>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu10: cpu@10400 { @@ -151,6 +161,7 @@ cpu10: cpu@10400 { power-domains = <&cpu_pd10>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu11: cpu@10500 { @@ -161,6 +172,7 @@ cpu11: cpu@10500 { power-domains = <&cpu_pd11>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; + #cooling-cells = <2>; }; cpu12: cpu@20000 { @@ -171,6 +183,7 @@ cpu12: cpu@20000 { power-domains = <&cpu_pd12>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; l2_2: l2-cache { compatible = "cache"; @@ -187,6 +200,7 @@ cpu13: cpu@20100 { power-domains = <&cpu_pd13>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu14: cpu@20200 { @@ -197,6 +211,7 @@ cpu14: cpu@20200 { power-domains = <&cpu_pd14>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu15: cpu@20300 { @@ -207,6 +222,7 @@ cpu15: cpu@20300 { power-domains = <&cpu_pd15>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu16: cpu@20400 { @@ -217,6 +233,7 @@ cpu16: cpu@20400 { power-domains = <&cpu_pd16>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu17: cpu@20500 { @@ -227,6 +244,7 @@ cpu17: cpu@20500 { power-domains = <&cpu_pd17>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; + #cooling-cells = <2>; }; cpu-map { From f92b778251ada37dc433a7f9547c5d2e5ebcdf7d Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 7 May 2026 22:38:27 +0530 Subject: [PATCH 075/131] dt-bindings: clock: add Qualcomm IPQ9650 GCC Add binding for the Qualcomm IPQ9650 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-1-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 ++++++ include/dt-bindings/clock/qcom,ipq9650-gcc.h | 172 ++++++++++++++ include/dt-bindings/reset/qcom,ipq9650-gcc.h | 215 ++++++++++++++++++ 3 files changed, 455 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq9650-gcc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9650-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml new file mode 100644 index 000000000000..f33105217a06 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9650 + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ9650 + + See also: + include/dt-bindings/clock/qcom,ipq9650-gcc.h + include/dt-bindings/reset/qcom,ipq9650-gcc.h + +properties: + compatible: + const: qcom,ipq9650-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: PCIE30 PHY4 pipe clock source + - description: USB PCIE wrapper pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq9650-gcc"; + reg = <0x01800000 0x40000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&pcie30_phy4_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq9650-gcc.h b/include/dt-bindings/clock/qcom,ipq9650-gcc.h new file mode 100644 index 000000000000..afd17c00d96e --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9650-gcc.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H + +#define GCC_ADSS_PWM_CLK 0 +#define GCC_ADSS_PWM_CLK_SRC 1 +#define GCC_ANOC_PCIE0_1LANE_M_CLK 2 +#define GCC_ANOC_PCIE0_1LANE_S_CLK 3 +#define GCC_ANOC_PCIE1_2LANE_M_CLK 4 +#define GCC_ANOC_PCIE1_2LANE_S_CLK 5 +#define GCC_ANOC_PCIE2_2LANE_M_CLK 6 +#define GCC_ANOC_PCIE2_2LANE_S_CLK 7 +#define GCC_ANOC_PCIE3_2LANE_M_CLK 8 +#define GCC_ANOC_PCIE3_2LANE_S_CLK 9 +#define GCC_ANOC_PCIE4_1LANE_M_CLK 10 +#define GCC_ANOC_PCIE4_1LANE_S_CLK 11 +#define GCC_CMN_12GPLL_AHB_CLK 12 +#define GCC_CMN_12GPLL_APU_CLK 13 +#define GCC_CMN_12GPLL_SYS_CLK 14 +#define GCC_CMN_LDO_CLK 15 +#define GCC_MDIO_AHB_CLK 16 +#define GCC_NSSCC_CLK 17 +#define GCC_NSSCFG_CLK 18 +#define GCC_NSSNOC_ATB_CLK 19 +#define GCC_NSSNOC_MEMNOC_1_CLK 20 +#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 +#define GCC_NSSNOC_MEMNOC_CLK 22 +#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 +#define GCC_NSSNOC_NSSCC_CLK 24 +#define GCC_NSSNOC_PCNOC_1_CLK 25 +#define GCC_NSSNOC_QOSGEN_REF_CLK 26 +#define GCC_NSSNOC_SNOC_1_CLK 27 +#define GCC_NSSNOC_SNOC_CLK 28 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 29 +#define GCC_NSSNOC_XO_DCD_CLK 30 +#define GCC_NSS_TS_CLK 31 +#define GCC_NSS_TS_CLK_SRC 32 +#define GCC_PCIE0_AHB_CLK 33 +#define GCC_PCIE0_AUX_CLK 34 +#define GCC_PCIE0_AXI_M_CLK 35 +#define GCC_PCIE0_AXI_M_CLK_SRC 36 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 37 +#define GCC_PCIE0_AXI_S_CLK 38 +#define GCC_PCIE0_AXI_S_CLK_SRC 39 +#define GCC_PCIE0_PIPE_CLK 40 +#define GCC_PCIE0_PIPE_CLK_SRC 41 +#define GCC_PCIE0_RCHNG_CLK 42 +#define GCC_PCIE0_RCHNG_CLK_SRC 43 +#define GCC_PCIE1_AHB_CLK 44 +#define GCC_PCIE1_AUX_CLK 45 +#define GCC_PCIE1_AXI_M_CLK 46 +#define GCC_PCIE1_AXI_M_CLK_SRC 47 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 48 +#define GCC_PCIE1_AXI_S_CLK 49 +#define GCC_PCIE1_AXI_S_CLK_SRC 50 +#define GCC_PCIE1_PIPE_CLK 51 +#define GCC_PCIE1_PIPE_CLK_SRC 52 +#define GCC_PCIE1_RCHNG_CLK 53 +#define GCC_PCIE1_RCHNG_CLK_SRC 54 +#define GCC_PCIE2_AHB_CLK 55 +#define GCC_PCIE2_AUX_CLK 56 +#define GCC_PCIE2_AXI_M_CLK 57 +#define GCC_PCIE2_AXI_M_CLK_SRC 58 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK 59 +#define GCC_PCIE2_AXI_S_CLK 60 +#define GCC_PCIE2_AXI_S_CLK_SRC 61 +#define GCC_PCIE2_PIPE_CLK 62 +#define GCC_PCIE2_PIPE_CLK_SRC 63 +#define GCC_PCIE2_RCHNG_CLK 64 +#define GCC_PCIE2_RCHNG_CLK_SRC 65 +#define GCC_PCIE3_AHB_CLK 66 +#define GCC_PCIE3_AUX_CLK 67 +#define GCC_PCIE3_AXI_M_CLK 68 +#define GCC_PCIE3_AXI_M_CLK_SRC 69 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK 70 +#define GCC_PCIE3_AXI_S_CLK 71 +#define GCC_PCIE3_AXI_S_CLK_SRC 72 +#define GCC_PCIE3_PIPE_CLK 73 +#define GCC_PCIE3_PIPE_CLK_SRC 74 +#define GCC_PCIE3_RCHNG_CLK 75 +#define GCC_PCIE3_RCHNG_CLK_SRC 76 +#define GCC_PCIE4_AHB_CLK 77 +#define GCC_PCIE4_AUX_CLK 78 +#define GCC_PCIE4_AXI_M_CLK 79 +#define GCC_PCIE4_AXI_M_CLK_SRC 80 +#define GCC_PCIE4_AXI_S_BRIDGE_CLK 81 +#define GCC_PCIE4_AXI_S_CLK 82 +#define GCC_PCIE4_AXI_S_CLK_SRC 83 +#define GCC_PCIE4_PIPE_CLK 84 +#define GCC_PCIE4_PIPE_CLK_SRC 85 +#define GCC_PCIE4_RCHNG_CLK 86 +#define GCC_PCIE4_RCHNG_CLK_SRC 87 +#define GCC_PCIE_AUX_CLK_SRC 88 +#define GCC_PCNOC_BFDCD_CLK_SRC 89 +#define GCC_QDSS_AT_CLK 90 +#define GCC_QDSS_AT_CLK_SRC 91 +#define GCC_QDSS_DAP_CLK 92 +#define GCC_QDSS_TSCTR_CLK_SRC 93 +#define GCC_QPIC_AHB_CLK 94 +#define GCC_QPIC_CLK 95 +#define GCC_QPIC_CLK_SRC 96 +#define GCC_QPIC_IO_MACRO_CLK 97 +#define GCC_QPIC_IO_MACRO_CLK_SRC 98 +#define GCC_QPIC_SLEEP_CLK 99 +#define GCC_QUPV3_2X_CORE_CLK 100 +#define GCC_QUPV3_2X_CORE_CLK_SRC 101 +#define GCC_QUPV3_AHB_MST_CLK 102 +#define GCC_QUPV3_AHB_SLV_CLK 103 +#define GCC_QUPV3_CORE_CLK 104 +#define GCC_QUPV3_SLEEP_CLK 105 +#define GCC_QUPV3_WRAP_SE0_CLK 106 +#define GCC_QUPV3_WRAP_SE0_CLK_SRC 107 +#define GCC_QUPV3_WRAP_SE1_CLK 108 +#define GCC_QUPV3_WRAP_SE1_CLK_SRC 109 +#define GCC_QUPV3_WRAP_SE2_CLK 110 +#define GCC_QUPV3_WRAP_SE2_CLK_SRC 111 +#define GCC_QUPV3_WRAP_SE3_CLK 112 +#define GCC_QUPV3_WRAP_SE3_CLK_SRC 113 +#define GCC_QUPV3_WRAP_SE4_CLK 114 +#define GCC_QUPV3_WRAP_SE4_CLK_SRC 115 +#define GCC_QUPV3_WRAP_SE5_CLK 116 +#define GCC_QUPV3_WRAP_SE5_CLK_SRC 117 +#define GCC_QUPV3_WRAP_SE6_CLK 118 +#define GCC_QUPV3_WRAP_SE6_CLK_SRC 119 +#define GCC_QUPV3_WRAP_SE7_CLK 120 +#define GCC_QUPV3_WRAP_SE7_CLK_SRC 121 +#define GCC_SDCC1_AHB_CLK 122 +#define GCC_SDCC1_APPS_CLK 123 +#define GCC_SDCC1_APPS_CLK_SRC 124 +#define GCC_SDCC1_ICE_CORE_CLK 125 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 126 +#define GCC_SLEEP_CLK_SRC 127 +#define GCC_SNOC_USB_CLK 128 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 +#define GCC_TLMM_AHB_CLK 130 +#define GCC_TLMM_CLK 131 +#define GCC_UNIPHY0_AHB_CLK 132 +#define GCC_UNIPHY0_SYS_CLK 133 +#define GCC_UNIPHY1_AHB_CLK 134 +#define GCC_UNIPHY1_SYS_CLK 135 +#define GCC_UNIPHY2_AHB_CLK 136 +#define GCC_UNIPHY2_SYS_CLK 137 +#define GCC_UNIPHY_SYS_CLK_SRC 138 +#define GCC_USB0_AUX_CLK 139 +#define GCC_USB0_AUX_CLK_SRC 140 +#define GCC_USB0_EUD_AT_CLK 141 +#define GCC_USB0_MASTER_CLK 142 +#define GCC_USB0_MASTER_CLK_SRC 143 +#define GCC_USB0_MOCK_UTMI_CLK 144 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 145 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 146 +#define GCC_USB0_PHY_CFG_AHB_CLK 147 +#define GCC_USB0_PIPE_CLK 148 +#define GCC_USB0_PIPE_CLK_SRC 149 +#define GCC_USB0_SLEEP_CLK 150 +#define GCC_USB1_MASTER_CLK 151 +#define GCC_USB1_MOCK_UTMI_CLK 152 +#define GCC_USB1_MOCK_UTMI_CLK_SRC 153 +#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 154 +#define GCC_USB1_PHY_CFG_AHB_CLK 155 +#define GCC_USB1_SLEEP_CLK 156 +#define GCC_XO_CLK_SRC 157 +#define GPLL0 158 +#define GPLL0_MAIN 159 +#define GPLL2 160 +#define GPLL2_OUT_MAIN 161 +#define GPLL4 162 +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9650-gcc.h b/include/dt-bindings/reset/qcom,ipq9650-gcc.h new file mode 100644 index 000000000000..a2cbb114addd --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9650-gcc.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_CLK_ARES 1 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 3 +#define GCC_APSS_AHB_CLK_ARES 4 +#define GCC_APSS_ATB_CLK_ARES 5 +#define GCC_APSS_AXI_CLK_ARES 6 +#define GCC_APSS_TS_CLK_ARES 7 +#define GCC_BOOT_ROM_AHB_CLK_ARES 8 +#define GCC_BOOT_ROM_BCR 9 +#define GCC_CMN_12GPLL_AHB_CLK_ARES 10 +#define GCC_CMN_12GPLL_APU_CLK_ARES 11 +#define GCC_CMN_12GPLL_SYS_CLK_ARES 12 +#define GCC_CMN_BLK_BCR 13 +#define GCC_CMN_LDO_CLK_ARES 14 +#define GCC_CPUSS_TRIG_CLK_ARES 15 +#define GCC_GP1_CLK_ARES 16 +#define GCC_GP2_CLK_ARES 17 +#define GCC_GP3_CLK_ARES 18 +#define GCC_MDIO_AHB_CLK_ARES 19 +#define GCC_MDIO_BCR 20 +#define GCC_NSSCC_CLK_ARES 21 +#define GCC_NSSCFG_CLK_ARES 22 +#define GCC_NSSNOC_ATB_CLK_ARES 23 +#define GCC_NSSNOC_MEMNOC_1_CLK_ARES 24 +#define GCC_NSSNOC_MEMNOC_CLK_ARES 25 +#define GCC_NSSNOC_NSSCC_CLK_ARES 26 +#define GCC_NSSNOC_PCNOC_1_CLK_ARES 27 +#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 28 +#define GCC_NSSNOC_SNOC_1_CLK_ARES 29 +#define GCC_NSSNOC_SNOC_CLK_ARES 30 +#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 31 +#define GCC_NSSNOC_XO_DCD_CLK_ARES 32 +#define GCC_NSS_BCR 33 +#define GCC_NSS_TS_CLK_ARES 34 +#define GCC_PCIE0PHY_PHY_BCR 35 +#define GCC_PCIE0_AHB_CLK_ARES 36 +#define GCC_PCIE0_AHB_RESET 37 +#define GCC_PCIE0_AUX_CLK_ARES 38 +#define GCC_PCIE0_AUX_RESET 39 +#define GCC_PCIE0_AXI_M_CLK_ARES 40 +#define GCC_PCIE0_AXI_M_RESET 41 +#define GCC_PCIE0_AXI_M_STICKY_RESET 42 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES 43 +#define GCC_PCIE0_AXI_S_CLK_ARES 44 +#define GCC_PCIE0_AXI_S_RESET 45 +#define GCC_PCIE0_AXI_S_STICKY_RESET 46 +#define GCC_PCIE0_BCR 47 +#define GCC_PCIE0_CORE_STICKY_RESET 48 +#define GCC_PCIE0_LINK_DOWN_BCR 49 +#define GCC_PCIE0_PHY_BCR 50 +#define GCC_PCIE0_PIPE_CLK_ARES 51 +#define GCC_PCIE0_PIPE_RESET 52 +#define GCC_PCIE1PHY_PHY_BCR 53 +#define GCC_PCIE1_AHB_CLK_ARES 54 +#define GCC_PCIE1_AHB_RESET 55 +#define GCC_PCIE1_AUX_CLK_ARES 56 +#define GCC_PCIE1_AUX_RESET 57 +#define GCC_PCIE1_AXI_M_CLK_ARES 58 +#define GCC_PCIE1_AXI_M_RESET 59 +#define GCC_PCIE1_AXI_M_STICKY_RESET 60 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES 61 +#define GCC_PCIE1_AXI_S_CLK_ARES 62 +#define GCC_PCIE1_AXI_S_RESET 63 +#define GCC_PCIE1_AXI_S_STICKY_RESET 64 +#define GCC_PCIE1_BCR 65 +#define GCC_PCIE1_CORE_STICKY_RESET 66 +#define GCC_PCIE1_LINK_DOWN_BCR 67 +#define GCC_PCIE1_PHY_BCR 68 +#define GCC_PCIE1_PIPE_CLK_ARES 69 +#define GCC_PCIE1_PIPE_RESET 70 +#define GCC_PCIE2PHY_PHY_BCR 71 +#define GCC_PCIE2_AHB_CLK_ARES 72 +#define GCC_PCIE2_AHB_RESET 73 +#define GCC_PCIE2_AUX_CLK_ARES 74 +#define GCC_PCIE2_AUX_RESET 75 +#define GCC_PCIE2_AXI_M_CLK_ARES 76 +#define GCC_PCIE2_AXI_M_RESET 77 +#define GCC_PCIE2_AXI_M_STICKY_RESET 78 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES 79 +#define GCC_PCIE2_AXI_S_CLK_ARES 80 +#define GCC_PCIE2_AXI_S_RESET 81 +#define GCC_PCIE2_AXI_S_STICKY_RESET 82 +#define GCC_PCIE2_BCR 83 +#define GCC_PCIE2_CORE_STICKY_RESET 84 +#define GCC_PCIE2_LINK_DOWN_BCR 85 +#define GCC_PCIE2_PHY_BCR 86 +#define GCC_PCIE2_PIPE_CLK_ARES 87 +#define GCC_PCIE2_PIPE_RESET 88 +#define GCC_PCIE3PHY_PHY_BCR 89 +#define GCC_PCIE3_AHB_CLK_ARES 90 +#define GCC_PCIE3_AHB_RESET 91 +#define GCC_PCIE3_AUX_CLK_ARES 92 +#define GCC_PCIE3_AUX_RESET 93 +#define GCC_PCIE3_AXI_M_CLK_ARES 94 +#define GCC_PCIE3_AXI_M_RESET 95 +#define GCC_PCIE3_AXI_M_STICKY_RESET 96 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES 97 +#define GCC_PCIE3_AXI_S_CLK_ARES 98 +#define GCC_PCIE3_AXI_S_RESET 99 +#define GCC_PCIE3_AXI_S_STICKY_RESET 100 +#define GCC_PCIE3_BCR 101 +#define GCC_PCIE3_CORE_STICKY_RESET 102 +#define GCC_PCIE3_LINK_DOWN_BCR 103 +#define GCC_PCIE3_PHY_BCR 104 +#define GCC_PCIE3_PIPE_CLK_ARES 105 +#define GCC_PCIE3_PIPE_RESET 106 +#define GCC_PCIE4PHY_PHY_BCR 107 +#define GCC_PCIE4_AHB_CLK_ARES 108 +#define GCC_PCIE4_AHB_RESET 109 +#define GCC_PCIE4_AUX_CLK_ARES 110 +#define GCC_PCIE4_AUX_RESET 111 +#define GCC_PCIE4_AXI_M_CLK_ARES 112 +#define GCC_PCIE4_AXI_M_RESET 113 +#define GCC_PCIE4_AXI_M_STICKY_RESET 114 +#define GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES 115 +#define GCC_PCIE4_AXI_S_CLK_ARES 116 +#define GCC_PCIE4_AXI_S_RESET 117 +#define GCC_PCIE4_AXI_S_STICKY_RESET 118 +#define GCC_PCIE4_BCR 119 +#define GCC_PCIE4_CORE_STICKY_RESET 120 +#define GCC_PCIE4_LINK_DOWN_BCR 121 +#define GCC_PCIE4_PHY_BCR 122 +#define GCC_PCIE4_PIPE_CLK_ARES 123 +#define GCC_PCIE4_PIPE_RESET 124 +#define GCC_QDSS_APB2JTAG_CLK_ARES 125 +#define GCC_QDSS_AT_CLK_ARES 126 +#define GCC_QDSS_BCR 127 +#define GCC_QDSS_CFG_AHB_CLK_ARES 128 +#define GCC_QDSS_DAP_AHB_CLK_ARES 129 +#define GCC_QDSS_DAP_CLK_ARES 130 +#define GCC_QDSS_ETR_USB_CLK_ARES 131 +#define GCC_QDSS_EUD_AT_CLK_ARES 132 +#define GCC_QDSS_STM_CLK_ARES 133 +#define GCC_QDSS_TRACECLKIN_CLK_ARES 134 +#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 135 +#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 136 +#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 137 +#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 138 +#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 139 +#define GCC_QDSS_TS_CLK_ARES 140 +#define GCC_QPIC_AHB_CLK_ARES 141 +#define GCC_QPIC_BCR 142 +#define GCC_QPIC_CLK_ARES 143 +#define GCC_QPIC_IO_MACRO_CLK_ARES 144 +#define GCC_QPIC_SLEEP_CLK_ARES 145 +#define GCC_QUPV3_2X_CORE_CLK_ARES 146 +#define GCC_QUPV3_AHB_MST_CLK_ARES 147 +#define GCC_QUPV3_AHB_SLV_CLK_ARES 148 +#define GCC_QUPV3_BCR 149 +#define GCC_QUPV3_CORE_CLK_ARES 150 +#define GCC_QUPV3_WRAP_SE0_BCR 151 +#define GCC_QUPV3_WRAP_SE0_CLK_ARES 152 +#define GCC_QUPV3_WRAP_SE1_BCR 153 +#define GCC_QUPV3_WRAP_SE1_CLK_ARES 154 +#define GCC_QUPV3_WRAP_SE2_BCR 155 +#define GCC_QUPV3_WRAP_SE2_CLK_ARES 156 +#define GCC_QUPV3_WRAP_SE3_BCR 157 +#define GCC_QUPV3_WRAP_SE3_CLK_ARES 158 +#define GCC_QUPV3_WRAP_SE4_BCR 159 +#define GCC_QUPV3_WRAP_SE4_CLK_ARES 160 +#define GCC_QUPV3_WRAP_SE5_BCR 161 +#define GCC_QUPV3_WRAP_SE5_CLK_ARES 162 +#define GCC_QUPV3_WRAP_SE6_BCR 163 +#define GCC_QUPV3_WRAP_SE6_CLK_ARES 164 +#define GCC_QUPV3_WRAP_SE7_BCR 165 +#define GCC_QUPV3_WRAP_SE7_CLK_ARES 166 +#define GCC_QUSB2_0_PHY_BCR 167 +#define GCC_QUSB2_1_PHY_BCR 168 +#define GCC_SDCC1_APPS_CLK_ARES 169 +#define GCC_SDCC1_ICE_CORE_CLK_ARES 170 +#define GCC_SDCC_BCR 171 +#define GCC_TLMM_AHB_CLK_ARES 172 +#define GCC_TLMM_BCR 173 +#define GCC_TLMM_CLK_ARES 174 +#define GCC_UNIPHY0_AHB_CLK_ARES 175 +#define GCC_UNIPHY0_BCR 176 +#define GCC_UNIPHY0_PMA_BCR 177 +#define GCC_UNIPHY0_SYS_CLK_ARES 178 +#define GCC_UNIPHY0_XPCS_ARES 179 +#define GCC_UNIPHY1_AHB_CLK_ARES 180 +#define GCC_UNIPHY1_BCR 181 +#define GCC_UNIPHY1_PMA_BCR 182 +#define GCC_UNIPHY1_SYS_CLK_ARES 183 +#define GCC_UNIPHY1_XPCS_ARES 184 +#define GCC_UNIPHY2_AHB_CLK_ARES 185 +#define GCC_UNIPHY2_BCR 186 +#define GCC_UNIPHY2_PMA_BCR 187 +#define GCC_UNIPHY2_SYS_CLK_ARES 188 +#define GCC_UNIPHY2_XPCS_ARES 189 +#define GCC_USB0_AUX_CLK_ARES 190 +#define GCC_USB0_MASTER_CLK_ARES 191 +#define GCC_USB0_MOCK_UTMI_CLK_ARES 192 +#define GCC_USB0_PHY_BCR 193 +#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 194 +#define GCC_USB0_PIPE_CLK_ARES 195 +#define GCC_USB0_SLEEP_CLK_ARES 196 +#define GCC_USB1_BCR 197 +#define GCC_USB1_MASTER_CLK_ARES 198 +#define GCC_USB1_MOCK_UTMI_CLK_ARES 199 +#define GCC_USB1_PHY_CFG_AHB_CLK_ARES 200 +#define GCC_USB1_SLEEP_CLK_ARES 201 +#define GCC_USB3PHY_0_PHY_BCR 202 +#define GCC_USB_BCR 203 +#define GCC_UNIPHY1_XLGPCS_ARES 204 +#define GCC_UNIPHY2_XLGPCS_ARES 205 +#endif From 5bfa2c53c675610110c797e1f17c87ce25424407 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 7 May 2026 22:38:29 +0530 Subject: [PATCH 076/131] dt-bindings: qcom: add IPQ9650 boards Document the new IPQ9650 SoC/board device tree bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-3-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2741c07e9f41..af266d584fae 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -366,6 +366,11 @@ properties: - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 + - items: + - enum: + - qcom,ipq9650-rdp488 + - const: qcom,ipq9650 + - items: - enum: - qcom,kaanapali-mtp From 8cef25a0044d3e7caef56a43bf316336fe39b5d8 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 7 May 2026 22:38:30 +0530 Subject: [PATCH 077/131] arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support Add initial device tree support for the Qualcomm IPQ9650 SoC and rdp488 board. Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-4-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 79 ++++ arch/arm64/boot/dts/qcom/ipq9650.dtsi | 377 ++++++++++++++++++++ 3 files changed, 457 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq9650.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 35252ea586a5..795cee4757ab 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb ipq9574-rdp433-emmc.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9650-rdp488.dtb dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts b/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts new file mode 100644 index 000000000000..6871f3dc4eaf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq9650.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9650 RDP488"; + compatible = "qcom,ipq9650-rdp488", "qcom,ipq9650"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&sdhc { + max-frequency = <192000000>; + bus-width = <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 = <&sdhc_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + qup_uart1_default_state: qup-uart1-default-state { + pins = "gpio43", "gpio44"; + function = "qup_se6"; + drive-strength = <8>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&qup_uart1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qcom/ipq9650.dtsi new file mode 100644 index 000000000000..a1bea8e648cd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l2_100>; + + l2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + + l2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x400>; + enable-method = "psci"; + next-level-cache = <&l2_400>; + + l2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scm { + compatible = "qcom,scm-ipq9650", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + bootloader@8a100000 { + reg = <0x0 0x8a100000 0x0 0x400000>; + no-map; + }; + + smem@8a500000 { + compatible = "qcom,smem"; + reg = <0x0 0x8a500000 0x0 0x40000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + }; + + tfa@8a600000 { + reg = <0x0 0x8a600000 0x0 0x80000>; + no-map; + }; + + optee@8a680000 { + reg = <0x0 0x8a680000 0x0 0x280000>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x10 0>; + ranges = <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9650-tlmm"; + reg = <0x0 0x01000000 0x0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq9650-gcc"; + reg = <0x0 0x01800000 0x0 0x40000>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + tcsr_mutex: hwlock@1917000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01917000 0x0 0x57000>; + #hwlock-cells = <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x01ac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart1: serial@1a98000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x01a98000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP_SE6_CLK>; + clock-names = "se"; + interrupts = ; + + status = "disabled"; + }; + }; + + sdhc: mmc@7804000 { + compatible = "qcom,ipq9650-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", + "core", + "xo"; + non-removable; + + status = "disabled"; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f240000 0x0 0xa0000>; + #interrupt-cells = <0x4>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + mbi-ranges = <800 160>; + msi-controller; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4>; + }; + }; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0f420000 0x0 0x1000>; + ranges = <0 0 0 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@f423000 { + reg = <0x0f423000 0x1000>; + interrupts = ; + frame-number = <1>; + + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>, + <0x0f426000 0x1000>; + interrupts = ; + frame-number = <2>; + + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + interrupts = ; + frame-number = <3>; + + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + interrupts = ; + frame-number = <4>; + + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + interrupts = ; + frame-number = <5>; + + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + interrupts = ; + frame-number = <6>; + + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; +}; From c50080d313d35a54c7847536ce9e27ad62546251 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 11 May 2026 22:24:54 +0530 Subject: [PATCH 078/131] arm64: dts: qcom: ipq9650: add watchdog node Add the watchdog device node for IPQ9650 SoC. Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260511-ipq9650_wdt-v1-1-1948934c1e12@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9650.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qcom/ipq9650.dtsi index a1bea8e648cd..3d3b317c6a3c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9650.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi @@ -300,6 +300,13 @@ ppi_cluster1: interrupt-partition-1 { }; }; + watchdog@f410000 { + compatible = "qcom,apss-wdt-ipq9650", "qcom,kpss-wdt"; + reg = <0x0 0x0f410000 0x0 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + }; + timer@f420000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0f420000 0x0 0x1000>; From d9dc254945756b44fa6f61b9cbd4adf0413c6a6f Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 15 Apr 2026 10:52:57 +0300 Subject: [PATCH 079/131] arm64: dts: qcom: glymur-crd: Drop forced host mode for USB SS0 and SS1 The two USB Type-C ports on Glymur CRD are dual-role capable. Do not force their controllers into host mode. Drop the explicit 'dr_mode = "host"' properties so they can use their default OTG mode instead. Fixes: c8b63029455b ("arm64: dts: qcom: glymur-crd: Enable USB support") Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-2-409e1a257f1f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 35aaf09e4e2b..c98dfb3941fa 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -322,8 +322,6 @@ reset-n-pins { }; &usb_0 { - dr_mode = "host"; - status = "okay"; }; @@ -353,8 +351,6 @@ &usb_0_qmpphy_out { }; &usb_1 { - dr_mode = "host"; - status = "okay"; }; From 347fa2fa64e1cef0c7897522896c0c66e734c82b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 15 Apr 2026 10:52:56 +0300 Subject: [PATCH 080/131] arm64: dts: qcom: glymur: Mark USB SS1 and SS2 as role-switch capable Like USB SS0, the USB SS1 and SS2 controllers on Glymur also support USB role switching. Describe this by adding the 'usb-role-switch' property to both controllers. Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes") Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-1-409e1a257f1f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 65c8e9233354..8a239dc359b0 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3972,6 +3972,8 @@ usb_1: usb@a800000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + usb-role-switch; + status = "disabled"; ports { @@ -4045,6 +4047,8 @@ usb_2: usb@a000000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + usb-role-switch; + status = "disabled"; ports { From 675fec65df73b525c12cb7a1c1ef54fcc3296d7c Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 10 Apr 2026 09:19:04 +0530 Subject: [PATCH 081/131] arm64: dts: qcom: Add support for MM clock controllers for Glymur Add the device nodes for the multimedia clock controllers videocc, gpucc and gxclkctl. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260410-glymur_mmcc_dt_config_v2-v3-1-acce9d106e72@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 8a239dc359b0..5e7c5320dc20 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5,7 +5,10 @@ #include #include +#include #include +#include +#include #include #include #include @@ -3742,6 +3745,34 @@ hsc_noc: interconnect@2000000 { #interconnect-cells = <2>; }; + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,glymur-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,glymur-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains = <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + ipcc: mailbox@3e04000 { compatible = "qcom,glymur-ipcc", "qcom,ipcc"; reg = <0x0 0x03e04000 0x0 0x1000>; @@ -4637,6 +4668,22 @@ mdss_dp3_out: endpoint { }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,glymur-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; From cd1d174c75f70fb0d7204802551aeaeb84689b59 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 13 Mar 2026 17:38:13 +0530 Subject: [PATCH 082/131] arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes. Signed-off-by: Sibi Sankar Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260313120814.1312410-5-sibi.sankar@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 286 +++++++++++++++++++++++++++ 1 file changed, 286 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 5e7c5320dc20..376fdb3cc8ad 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3784,6 +3784,122 @@ ipcc: mailbox@3e04000 { #mbox-cells = <2>; }; + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + iommus = <&apps_smmu 0x1000 0x0>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <2>; + + label = "lpass"; + + fastrpc { + compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + iommus = <&apps_smmu 0x1008 0x80>, + <&apps_smmu 0x1068 0x20>; + dma-coherent; + }; + }; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,glymur-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -6002,6 +6118,176 @@ system-cache-controller@21800000 { interrupts = ; }; + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x10000>; + + iommus = <&apps_smmu 0x2400 0x400>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + + iommus = <&apps_smmu 0x2401 0x440>, + <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x19c1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + + iommus = <&apps_smmu 0x2402 0x440>, + <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x2403 0x440>, + <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x2404 0x440>, + <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x2405 0x440>, + <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x2406 0x440>, + <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x2407 0x440>, + <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + iommus = <&apps_smmu 0x2408 0x440>, + <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + /* note: compute-cb@9 is secure */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + + iommus = <&apps_smmu 0x240c 0x440>, + <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + + iommus = <&apps_smmu 0x240d 0x440>, + <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + + iommus = <&apps_smmu 0x240e 0x440>, + <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; + }; + }; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,glymur-nsp-noc"; reg = <0x0 0x320c0000 0x0 0x21280>; From 377665c6078d1aa18d29d56a39d70ed8185cd2d1 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 13 Mar 2026 17:38:14 +0530 Subject: [PATCH 083/131] arm64: dts: qcom: glymur-crd: Enable ADSP and CDSP Enable ADSP and CDSP on Glymur CRD board. Signed-off-by: Sibi Sankar Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260313120814.1312410-6-sibi.sankar@oss.qualcomm.com [bjorn: Moved snippet to common glymur-crd.dtsi] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 357d4ad8380a..e784b538f42e 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -571,6 +571,20 @@ &pon_resin { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/glymur/adsp.mbn", + "qcom/glymur/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/cdsp.mbn", + "qcom/glymur/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ From 4a1779f42e21962381a9696d182a2620c830ff10 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 11 May 2026 15:45:43 +0530 Subject: [PATCH 084/131] arm64: dts: qcom: sm8750: Add camera clock controller The camera clock controller is split into cambistmclk and camcc. The cambist clock controller handles the mclks and the rest of the clocks of camera are part of the camcc clock controller. Add the camcc clock controller device node for SM8750 SoC. Reviewed-by: Abel Vesa Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260511-sm8750_camcc_dt-v4-1-eab4b6c3eaea@oss.qualcomm.com [bjorn: Fixed include file order] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 5921f83aafac..49d4a9a34c04 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5,6 +5,8 @@ #include #include +#include +#include #include #include #include @@ -2082,6 +2084,23 @@ aggre2_noc: interconnect@1700000 { clocks = <&rpmhcc RPMH_IPA_CLK>; }; + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,sm8750-cambistmclkcc"; + reg = <0x0 0x1760000 0x0 0x6000>; + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mmss_noc: interconnect@1780000 { compatible = "qcom,sm8750-mmss-noc"; reg = <0x0 0x01780000 0x0 0x5b800>; @@ -3444,6 +3463,23 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8750-camcc"; + reg = <0x0 0xade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; From 9c633eec37782b2d31281a0289882bb419b5ad18 Mon Sep 17 00:00:00 2001 From: Wojciech Slenska Date: Tue, 10 Mar 2026 12:22:31 +0100 Subject: [PATCH 085/131] arm64: dts: qcom: agatti: Add IPA nodes Added IPA nodes and definitions. Signed-off-by: Wojciech Slenska Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260310112309.79261-3-wojciech.slenska@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 53 ++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index fd40aa59878a..f0b6ae9b8152 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -433,6 +433,18 @@ wlan_smp2p_in: wlan-wpss-to-ap { interrupt-controller; #interrupt-cells = <2>; }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; soc: soc@0 { @@ -1641,6 +1653,47 @@ usb_dwc3_ss: endpoint { }; }; + ipa: ipa@5840000 { + compatible = "qcom,qcm2290-ipa", "qcom,sc7180-ipa"; + + iommus = <&apps_smmu 0x140 0x0>; + reg = <0x0 0x05840000 0x0 0x7000>, + <0x0 0x05847000 0x0 0x2000>, + <0x0 0x05804000 0x0 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + clock-names = "core"; + + interconnects = <&system_noc MASTER_IPA RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&system_noc MASTER_IPA RPM_ALWAYS_TAG + &system_noc SLAVE_IMEM RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_IPA_CFG RPM_ACTIVE_TAG>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + gpu: gpu@5900000 { compatible = "qcom,adreno-07000200", "qcom,adreno"; reg = <0x0 0x05900000 0x0 0x40000>, From 3f5dcc05cd33e85e897571b4e44feb06f5399b68 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Mon, 30 Mar 2026 16:50:20 -0500 Subject: [PATCH 086/131] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7) to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with referenc to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores changes frequency. The OPP tables were built using the downstream memlat ddr, llcc & l3 tables for each cluster types with the actual EPSS cpufreq LUT tables from running a QCS8550 device. Also add the OSC L3 Cache controller node. Also add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Tested-by: Neil Armstrong # on SM8550-HDK Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Aaron Kling Link: https://lore.kernel.org/r/20260330-sm8550-ddr-bw-scaling-v4-1-5020c06983a0@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 912525e9bca6..b7a7c49db077 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,13 @@ cpu0: cpu@0 { qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <326>; dynamic-power-coefficient = <251>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -104,6 +112,13 @@ cpu1: cpu@100 { qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <326>; dynamic-power-coefficient = <251>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_100: l2-cache { compatible = "cache"; @@ -125,6 +140,13 @@ cpu2: cpu@200 { qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <326>; dynamic-power-coefficient = <251>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_200: l2-cache { compatible = "cache"; @@ -146,6 +168,13 @@ cpu3: cpu@300 { qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <693>; dynamic-power-coefficient = <447>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_300: l2-cache { compatible = "cache"; @@ -167,6 +196,13 @@ cpu4: cpu@400 { qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <693>; dynamic-power-coefficient = <447>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_400: l2-cache { compatible = "cache"; @@ -188,6 +224,13 @@ cpu5: cpu@500 { qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <693>; dynamic-power-coefficient = <447>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_500: l2-cache { compatible = "cache"; @@ -209,6 +252,13 @@ cpu6: cpu@600 { qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <693>; dynamic-power-coefficient = <447>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_600: l2-cache { compatible = "cache"; @@ -230,6 +280,13 @@ cpu7: cpu@700 { qcom,freq-domain = <&cpufreq_hw 2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <1057>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_700: l2-cache { compatible = "cache"; @@ -397,6 +454,306 @@ memory@a0000000 { reg = <0 0xa0000000 0 0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-441600000 { + opp-hz = /bits/ 64 <441600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>; + }; + + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>; + }; + + opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>; + }; + + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible = "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible = "operating-points-v2"; + opp-shared; + + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-2092800000 { + opp-hz = /bits/ 64 <2092800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2227200000 { + opp-hz = /bits/ 64 <2227200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2476800000 { + opp-hz = /bits/ 64 <2476800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2726400000 { + opp-hz = /bits/ 64 <2726400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>; + }; + + opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2956800000 { + opp-hz = /bits/ 64 <2956800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-3187200000 { + opp-hz = /bits/ 64 <3187200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + }; + pmu-a510 { compatible = "arm,cortex-a510-pmu"; interrupts = ; @@ -5482,6 +5839,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; + epss_l3: interconnect@17d90000 { + compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3"; + reg = <0 0x17d90000 0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x17d91000 0 0x1000>, From f4d7c5875a215cd3989b59d13a9c30cec9f0a33b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 Mar 2026 18:56:46 +0200 Subject: [PATCH 087/131] arm64: dts: qcom: sm8750: Fix DSI1 phy reference clock rate The DSI PHY CXO clock input is the SoC CXO divided by two. DSI0 already uses correct one, but DSI1 got copy-paste from SM8650. Wrong clock parent will cause incorrect DSI1 PHY PLL frequencies to be used making the DSI panel non-working, although there is no upstream user of DSI1. Fixes: 818ae2b389bc ("arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260331165645.233965-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 49d4a9a34c04..70830cb49e73 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3340,7 +3340,7 @@ mdss_dsi1_phy: phy@ae97000 { "dsi_pll"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; + <&bi_tcxo_div2>; clock-names = "iface", "ref"; From fa9c7403af64d3e56a6c20dedc60e0a55b527509 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 2 Apr 2026 00:05:09 +0530 Subject: [PATCH 088/131] arm64: dts: qcom: kodiak: Fix ICE reg size The ICE register region on Kodiak is currently defined as 0x8000 bytes. According to the hardware specification, the correct register size is 0x18000. Update the ICE node reg property to match the hardware. Fixes: dfd5ee7b34bb ("arm64: dts: qcom: sc7280: Add inline crypto engine") Signed-off-by: Kuldeep Singh Reviewed-by: Harshal Dev Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-1-74e4c2129238@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 2dbeb15c84b7..c51beada8c7d 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2578,7 +2578,7 @@ ufs_mem_phy: phy@1d87000 { ice: crypto@1d88000 { compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; From 7fb3d0512dacc0d09217eb45057357f00298203d Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 2 Apr 2026 00:05:10 +0530 Subject: [PATCH 089/131] arm64: dts: qcom: sm8450: Fix ICE reg size The ICE register region size was originally described incorrectly when the ICE hardware was first introduced. The same value was later carried over unchanged when the ICE node was split out from the UFS node into its own DT entry. Correct the register size to match the hardware specification. Fixes: 276ee34a40c1 ("arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock") Signed-off-by: Kuldeep Singh Reviewed-by: Harshal Dev Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-2-74e4c2129238@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 03bf30b53f28..e0c37ce3042a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5373,7 +5373,7 @@ ufs_mem_phy: phy@1d87000 { ice: crypto@1d88000 { compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; From c4b423835ee7529854ab39b50cf766bc4c6b4d66 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 16:06:58 -0400 Subject: [PATCH 090/131] arm64: dts: qcom: sdm670: add lpi pinctrl The Snapdragon 670 has a separate TLMM for audio pins. Add the device node for it. Also add reserved GPIOs for the Pixel 3a, which blocks access to the sensor GPIOs. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20260331200658.1306-5-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index e13ced9479b7..30844b150c80 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -2300,5 +2300,78 @@ cpufreq_hw: cpufreq@17d43000 { #freq-domain-cells = <1>; }; + + lpi_tlmm: pinctrl@62b40000 { + compatible = "qcom,sdm670-lpass-lpi-pinctrl"; + reg = <0 0x62b40000 0 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_pdm_default: cdc-pdm-default-state { + clk-pins { + pins = "gpio18"; + function = "slimbus_clk"; + drive-strength = <4>; + output-low; + }; + + sync-pins { + pins = "gpio19"; + function = "pdm_sync"; + drive-strength = <4>; + output-low; + }; + + tx-pins { + pins = "gpio20"; + function = "pdm_tx"; + drive-strength = <8>; + }; + + rx-pins { + pins = "gpio21", "gpio23", "gpio25"; + function = "pdm_rx"; + drive-strength = <4>; + output-low; + }; + }; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <4>; + }; + + cdc_dmic_default: cdc-dmic-default-state { + clk1-pins { + pins = "gpio26"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + clk2-pins { + pins = "gpio28"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data1-pins { + pins = "gpio27"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + + data2-pins { + pins = "gpio29"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + }; }; }; From 69442723f38a338962bee877243e7c1ff86039b8 Mon Sep 17 00:00:00 2001 From: Harrison Vanderbyl Date: Tue, 12 May 2026 00:40:50 +1000 Subject: [PATCH 091/131] dt-bindings: arm: qcom: Add Microsoft Surface Pro 12in Document the compatible string for the Microsoft Surface Pro 12-inch, 1st Edition with Snapdragon, based on the Qualcomm X1P42100 SoC. Signed-off-by: Harrison Vanderbyl Link: https://lore.kernel.org/r/627a1e2506fbed99e971250dbba64902af54232c.1778498477.git.harrison.vanderbyl@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index af266d584fae..50cc18a6ec5e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1181,6 +1181,10 @@ properties: - const: microsoft,denali - const: qcom,x1e80100 + - items: + - const: microsoft,surface-pro-12in + - const: qcom,x1p42100 + - items: - enum: - qcom,purwa-iot-evk From 32fbd42e6b56aae4587c76f53a51d187add4eec7 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Wed, 15 Apr 2026 12:10:46 +0530 Subject: [PATCH 092/131] arm64: dts: qcom: monaco: add GDSP fastrpc-compute-cb nodes Add GDSP fastrpc compute-cb nodes for monaco SoC. Signed-off-by: Ekansh Gupta Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260415-monacogdsp-v1-1-077ded36c7fc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 7b1d57460f1e..ce6ff259cb4a 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -7615,6 +7615,35 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "gpdsp"; qcom,remote-pid = <17>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "gdsp0"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x28a1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x28a2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x28a3 0x0>; + dma-coherent; + }; + }; }; }; From 487c97b671e4f224adb9d74b9f14372e283bea32 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 15 Apr 2026 13:56:08 +0200 Subject: [PATCH 093/131] arm64: dts: qcom: sdm845-shift-axolotl: describe WiFi/BT properly The onboard WiFi / BT device, WCN3990, has a simple on-chip PMU, which further spreads generated voltage. Describe the PMU in the device tree. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260415-axolotl-wifi-v1-1-07df39cfc0a4@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 65 ++++++++++++++++--- 1 file changed, 55 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 14a683ee3823..f21b914f22b5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -105,6 +105,43 @@ vreg_s4a_1p8: pm8998-smps4 { vin-supply = <&vph_pwr>; }; + + wcn3990-pmu { + compatible = "qcom,wcn3990-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; + + swctrl-gpios = <&pm8998_gpios 3 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &adsp_pas { @@ -546,6 +583,13 @@ &mss_pil { }; &pm8998_gpios { + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio3"; + function = "normal"; + input-enable; + bias-pull-down; + }; + volume_up_gpio: pm8998-gpio6-state { pinconf { pins = "gpio6"; @@ -784,10 +828,11 @@ bluetooth { */ firmware-name = "SHIFT/axolotl/crnv21.bin"; - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + max-speed = <3200000>; }; }; @@ -842,14 +887,14 @@ &venus { }; &wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + vdd-3.3-ch1-supply = <&vreg_pmu_ch1>; qcom,calibration-variant = "shift_axolotl"; qcom,snoc-host-cap-8bit-quirk; + + status = "okay"; }; From 88ddafb01ec05bb3cd1ffb51b740bfbc989ab955 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 14 May 2026 16:54:13 +0300 Subject: [PATCH 094/131] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes Describe the ADSP remoteproc node along with its dependencies, including the IPCC mailbox, AOSS QMP and SMP2P links used for communication. The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP combo PHY and an SNPS eUSB2 PHY. Describe them. Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260514-eliza-adsp-usb-v5-1-a21056ffd892@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 260 ++++++++++++++++++++++++++++ 1 file changed, 260 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 24c680795481..9fc07b6146e5 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -6,10 +6,13 @@ #include #include #include +#include #include #include #include #include +#include +#include #include #include @@ -596,6 +599,30 @@ llcc_lpi_mem: llcc-lpi@ff800000 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -624,6 +651,17 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + ipcc: mailbox@406000 { + compatible = "qcom,eliza-ipcc", "qcom,ipcc"; + reg = <0x0 0x00406000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + qupv3_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x2000>; @@ -894,6 +932,55 @@ tcsr: clock-controller@1fbf000 { #reset-cells = <1>; }; + remoteproc_adsp: remoteproc@3000000 { + compatible = "qcom,eliza-adsp-pas"; + reg = <0x0 0x03000000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,eliza-lpass-ag-noc"; reg = <0x0 0x07e40000 0x0 0xe080>; @@ -915,6 +1002,167 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + usb_hsphy: phy@88e3000 { + compatible = "qcom,eliza-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e3000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,eliza-qmp-usb3-dp-phy", + "qcom,sm8650-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb: usb@a600000 { + compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + phys = <&usb_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + + iommus = <&apps_smmu 0x40 0x0>; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,eliza-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x40000>, @@ -989,6 +1237,18 @@ tsens2: thermal-sensor@c22a000 { #thermal-sensor-cells = <1>; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,eliza-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + spmi: arbiter@c400000 { compatible = "qcom,eliza-spmi-pmic-arb", "qcom,x1e80100-spmi-pmic-arb"; From 59703108a0c00321f181d021cb83e0d7b610ed61 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 14 May 2026 16:54:14 +0300 Subject: [PATCH 095/131] arm64: dts: qcom: Add Eliza-specific PM7550BA dtsi On Eliza, the SPMI arbiter supports multiple bus masters, requiring explicit selection of the master for each PMIC. The existing PM7550BA dtsi does not provide a way to describe this, so introduce an Eliza-specific variant with the appropriate bus configuration. This duplication is required due to hardware differences in how the SPMI bus is exposed on this platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260514-eliza-adsp-usb-v5-2-a21056ffd892@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi | 70 ++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi b/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi new file mode 100644 index 000000000000..18692893ca41 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + thermal-zones { + pm7550ba-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm7550ba_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pm7550ba: pmic@7 { + compatible = "qcom,pm7550ba", "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7550ba_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7550ba_gpios: gpio@8800 { + compatible = "qcom,pm7550ba-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7550ba_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm7550ba_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm7550ba-eusb2-repeater", + "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; From 49dab7311f57e0ba81bdcd3bcf6d763cca13532b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 14 May 2026 16:54:15 +0300 Subject: [PATCH 096/131] arm64: dts: qcom: eliza-mtp: Enable USB and ADSP support The Eliza MTP features a single USB Type-C port. Its USB 2.0 lines are routed through an eUSB2 repeater provided by the PM7550BA PMIC. Describe the port and repeater, and enable the USB controller and PHYs. Also specify the ADSP firmware and enable the remoteproc. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260514-eliza-adsp-usb-v5-3-a21056ffd892@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 81 ++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 90f629800cb0..3e41c95edb28 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -6,9 +6,12 @@ /dts-v1/; #include +#include #include #include "eliza.dtsi" +#include "pm7550ba-eliza.dtsi" + / { model = "Qualcomm Technologies, Inc. Eliza MTP"; compatible = "qcom,eliza-mtp", "qcom,eliza"; @@ -54,6 +57,44 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { }; }; + pmic-glink { + compatible = "qcom,eliza-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -376,6 +417,18 @@ vreg_l7k: ldo7 { }; }; +&pm7550ba_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; +}; + +&remoteproc_adsp { + firmware-name = "qcom/eliza/adsp.mbn", + "qcom/eliza/adsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <20 4>, /* NFC SPI */ <111 2>, /* WCN UART1 */ @@ -405,3 +458,31 @@ &ufs_mem_phy { status = "okay"; }; + +&usb { + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3g>; + vdda-pll-supply = <&vreg_l7k>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l7k>; + vdda12-supply = <&vreg_l4b>; + + phys = <&pm7550ba_eusb2_repeater>; + + status = "okay"; +}; From 159d252ed80025cfdc218dd38cdcbdc7eb4beddf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 6 May 2026 14:30:26 +0200 Subject: [PATCH 097/131] arm64: dts: qcom: eliza: Add display (MDSS) with Display CC Add device nodes for almost entire display: MDSS, DPU, DSI, DSI PHYs, DisplayPort and Display Clock Controller. Missing pieces are HDMI PHY and HDMI controller. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260506-dts-qcom-eliza-display-v3-1-9e46401f467a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 443 ++++++++++++++++++++++++++++ 1 file changed, 443 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 9fc07b6146e5..dc0d605a2125 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -3,6 +3,8 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include #include #include #include @@ -1067,6 +1069,7 @@ port@2 { reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -1163,6 +1166,446 @@ usb_dwc3_ss: endpoint { }; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,eliza-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + ranges; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,eliza-dpu"; + reg = <0x0 0x0ae01000 0x0 0x93000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + /* TODO: HDMI */ + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz = /bits/ 64 <207000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-660000000 { + opp-hz = /bits/ 64 <660000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-140630000 { + opp-hz = /bits/ 64 <140630000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; + reg = <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x300>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&bi_tcxo_div2>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae96000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; + reg = <0x0 0x0ae97000 0x0 0x200>, + <0x0 0x0ae97200 0x0 0x300>, + <0x0 0x0ae97500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,eliza-dp", "qcom,sm8650-dp"; + reg = <0x0 0x0af54000 0x0 0x200>, + <0x0 0x0af54200 0x0 0x200>, + <0x0 0x0af55000 0x0 0xc00>, + <0x0 0x0af56000 0x0 0x400>, + <0x0 0x0af57000 0x0 0x400>, + <0x0 0x0af58000 0x0 0x400>, + <0x0 0x0af59000 0x0 0x400>, + <0x0 0x0af5a000 0x0 0x600>, + <0x0 0x0af5b000 0x0 0x600>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&dp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,eliza-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>, + <0>; /* HDMI phy */ + + power-domains = <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,eliza-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x40000>, From 72f758277a4400be7c459653f709ce5fc70a9dcd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 6 May 2026 14:30:27 +0200 Subject: [PATCH 098/131] arm64: dts: qcom: eliza-mtp: Enable DSI display panel Enable display on Eliza MTP board with Visionox VTDR6130 panel. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260506-dts-qcom-eliza-display-v3-2-9e46401f467a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 63 ++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 3e41c95edb28..f0a390107d5d 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -417,6 +417,48 @@ vreg_l7k: ldo7 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l4b>; + + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + + vci-supply = <&vreg_l19b>; + vdd-supply = <&vreg_l1g>; + vddio-supply = <&vreg_l8b>; + + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l2b>; + + status = "okay"; +}; + &pm7550ba_eusb2_repeater { vdd18-supply = <&vreg_l7b>; vdd3-supply = <&vreg_l17b>; @@ -433,6 +475,27 @@ &tlmm { gpio-reserved-ranges = <20 4>, /* NFC SPI */ <111 2>, /* WCN UART1 */ <118 1>; /* NFC Secure I/O */ + + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync: mdp-vsync-state { + pins = "gpio17"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart14 { From 193fd5f1aadf464c5e2a2fe2dfcbfe51d9dee645 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 6 May 2026 14:30:28 +0200 Subject: [PATCH 099/131] arm64: dts: qcom: eliza-mtp: Enable DisplayPort on USB Enable display on USB DisplayPort on MTP board with Eliza SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260506-dts-qcom-eliza-display-v3-3-9e46401f467a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/eliza.dtsi | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index f0a390107d5d..912cfbee552e 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -421,6 +421,14 @@ &mdss { status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dsi0 { vdda-supply = <&vreg_l4b>; diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index dc0d605a2125..1fe217f636e8 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -1042,6 +1042,7 @@ usb_dp_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From 179d11c1c0cfaddcfc984edc3c1863ab600f679f Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 15 May 2026 16:22:38 +0300 Subject: [PATCH 100/131] arm64: dts: qcom: eliza-mtp: Fix the debug UART index The Eliza MTP debug UART is QUPv3 WRAP2 SE5. The existing DTS labels it as uart14, but the serial-engine index for this block is actually 13. Rename the SoC UART label and pinctrl state to uart13 and update the MTP alias and node reference accordingly. Fixes: af20af39fc09 ("arm64: dts: qcom: Introduce Eliza Soc base dtsi") Fixes: 2a5d4fc6f3f7 ("arm64: dts: qcom: eliza: Enable Eliza MTP board support") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260515-eliza-dts-fix-debug-uart-and-more-support-v2-1-5ad3da81b9d3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/eliza.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 912cfbee552e..1374afd9d14e 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -18,7 +18,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &uart14; + serial0 = &uart13; }; chosen { @@ -506,7 +506,7 @@ mdp_vsync: mdp-vsync-state { }; }; -&uart14 { +&uart13 { compatible = "qcom,geni-debug-uart"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 1fe217f636e8..9c520ee5036f 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -679,7 +679,7 @@ qupv3_2: geniqup@8c0000 { #size-cells = <2>; ranges; - uart14: serial@894000 { + uart13: serial@894000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00894000 0x0 0x4000>; @@ -695,7 +695,7 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; - pinctrl-0 = <&qup_uart14_default>; + pinctrl-0 = <&qup_uart13_default>; pinctrl-names = "default"; status = "disabled"; @@ -2070,7 +2070,7 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 184>; wakeup-parent = <&pdc>; - qup_uart14_default: qup-uart14-default-state { + qup_uart13_default: qup-uart13-default-state { /* TX, RX */ pins = "gpio18", "gpio19"; function = "qup2_se5"; From 844807e1f89d8852d570b4be5297a79ea674fc47 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 15 May 2026 16:22:39 +0300 Subject: [PATCH 101/131] arm64: dts: qcom: eliza: Add QUPv3, GPI DMA, SDHCI and LLCC nodes Describe the missing Eliza SoC nodes for the QUPv3 WRAP1 and WRAP2 serial engines, add the matching GPI DMA controllers, the SDHCI controllers and the LLCC system cache controller. Also add the TLMM pinctrl states for the QUPv3 serial engines and the SD card/eMMC interfaces, plus OPP tables for the SDHCI controllers. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-eliza-dts-fix-debug-uart-and-more-support-v2-2-5ad3da81b9d3@oss.qualcomm.com [bjorn: Temporarily replaced SLAVE_SDCC_1 with the constant] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 1527 +++++++++++++++++++++++++++ 1 file changed, 1527 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 9c520ee5036f..d465b384e223 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -664,6 +665,32 @@ ipcc: mailbox@406000 { #mbox-cells = <2>; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x436 0>; + + dma-coherent; + }; + qupv3_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x2000>; @@ -679,6 +706,336 @@ qupv3_2: geniqup@8c0000 { #size-cells = <2>; ranges; + i2c8: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c9: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi9: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c11: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c12: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi12: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart13: serial@894000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00894000 0x0 0x4000>; @@ -700,6 +1057,679 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + + i2c14: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00898000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c15: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0089c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0089c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xb6 0x0>; + + dma-coherent; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0xa3 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c0: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c4: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi4_clk>, <&qup_spi4_cs>, + <&qup_spi4_data>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart5: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + uart6: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c7: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + sdhc_1: mmc@f44000 { + compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x00f44000 0x0 0x1000>, + <0x0 0x00f45000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc 30 /*TODO: SLAVE_SDCC_1*/ QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + qcom,dll-config = <0x000f44ec>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x520 0x0>; + dma-coherent; + + bus-width = <8>; + + resets = <&gcc GCC_SDCC1_BCR>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; }; config_noc: interconnect@1600000 { @@ -1004,6 +2034,59 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + sdhc_2: mmc@8804000 { + compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + dma-coherent; + + bus-width = <4>; + + resets = <&gcc GCC_SDCC2_BCR>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_hsphy: phy@88e3000 { compatible = "qcom,eliza-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; @@ -2070,6 +3153,280 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 184>; wakeup-parent = <&pdc>; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + pins = "gpio28", "gpio29"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio31"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio28", "gpio29", "gpio30"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins = "gpio32", "gpio33"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio35"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins = "gpio52", "gpio53"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio55"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio47"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins = "gpio36", "gpio37"; + function = "qup1_se4_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_clk: qup-spi4-clk-state { + pins = "gpio37"; + function = "qup1_se4_23"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio36"; + function = "qup1_se4_23"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data: qup-spi4-data-state { + pins = "gpio36", "gpio37"; + function = "qup1_se4_01"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins = "gpio134", "gpio135"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart5_cts_rts: qup-uart5-cts-rts-state { + /* CTS, RTS */ + pins = "gpio132", "gpio133"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart6_default: qup-uart6-default-state { + /* TX, RX */ + pins = "gpio42", "gpio40"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart6_cts_rts: qup-uart6-cts-rts-state { + /* CTS, RTS */ + pins = "gpio40", "gpio42"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + pins = "gpio81", "gpio80"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio78"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + pins = "gpio81", "gpio80", "gpio114"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + pins = "gpio0", "gpio1"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio3"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + pins = "gpio4", "gpio5"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio7"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + pins = "gpio4", "gpio5", "gpio6"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + pins = "gpio8", "gpio9"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio11"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + pins = "gpio8", "gpio9", "gpio10"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + pins = "gpio79", "gpio97"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio116"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio79", "gpio97", "gpio100"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + pins = "gpio12", "gpio13"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio27"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + pins = "gpio12", "gpio13", "gpio26"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + qup_uart13_default: qup-uart13-default-state { /* TX, RX */ pins = "gpio18", "gpio19"; @@ -2077,6 +3434,162 @@ qup_uart13_default: qup-uart13-default-state { drive-strength = <2>; bias-pull-up; }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + pins = "gpio20", "gpio21"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio23"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio20", "gpio21", "gpio22"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + pins = "gpio27", "gpio26"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio12"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio27", "gpio26", "gpio13"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "gpio121"; + function = "sdc1"; + drive-strength = <12>; + bias-disable; + }; + + cmd-pins { + pins = "gpio123"; + function = "sdc1"; + drive-strength = <12>; + bias-pull-up; + }; + + data-pins { + pins = "gpio124", "gpio125", + "gpio126", "gpio127", + "gpio128", "gpio129", + "gpio130", "gpio131"; + function = "sdc1"; + drive-strength = <12>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio120"; + function = "sdc1"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "gpio121"; + function = "sdc1"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "gpio123"; + function = "sdc1"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "gpio124", "gpio125", + "gpio126", "gpio127", + "gpio128", "gpio129", + "gpio130", "gpio131"; + function = "sdc1"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio120"; + function = "sdc1"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "gpio62"; + function = "sdc2"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "gpio51"; + function = "sdc2"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "gpio38", "gpio39", + "gpio48", "gpio49"; + function = "sdc2"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "gpio62"; + function = "sdc2"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "gpio51"; + function = "sdc2"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "gpio38", "gpio39", + "gpio48", "gpio49"; + function = "sdc2"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; gem_noc: interconnect@24100000 { @@ -2086,6 +3599,20 @@ gem_noc: interconnect@24100000 { #interconnect-cells = <2>; }; + system-cache-controller@24800000 { + compatible = "qcom,eliza-llcc"; + reg = <0x0 0x24800000 0x0 0x200000>, + <0x0 0x24c00000 0x0 0x200000>, + <0x0 0x26800000 0x0 0x200000>, + <0x0 0x26c00000 0x0 0x200000>; + reg-names = "llcc0_base", + "llcc2_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = ; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,eliza-nsp-noc"; reg = <0x0 0x320c0000 0x0 0xe080>; From 853a3ead458c409ffcfd7ff6a33ddc994b9a444d Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Sat, 18 Apr 2026 10:39:45 +0000 Subject: [PATCH 102/131] arm64: dts: qcom: eliza: Sort nodes by unit address Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move few nodes in Eliza DTSI to fix that. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich Link: https://lore.kernel.org/r/20260418-eliza-imem-v3-1-bfbd499b6e77@pm.me [bjorn: Rebased on top of branch] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 654 ++++++++++++++-------------- 1 file changed, 327 insertions(+), 327 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index d465b384e223..abfaea2f6b75 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -1732,16 +1732,16 @@ opp-384000000 { }; }; - config_noc: interconnect@1600000 { - compatible = "qcom,eliza-cnoc-cfg"; - reg = <0x0 0x01600000 0x0 0x5200>; + cnoc_main: interconnect@1500000 { + compatible = "qcom,eliza-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x16080>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; - cnoc_main: interconnect@1500000 { - compatible = "qcom,eliza-cnoc-main"; - reg = <0x0 0x01500000 0x0 0x16080>; + config_noc: interconnect@1600000 { + compatible = "qcom,eliza-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x5200>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; @@ -2013,13 +2013,6 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; - lpass_ag_noc: interconnect@7e40000 { - compatible = "qcom,eliza-lpass-ag-noc"; - reg = <0x0 0x07e40000 0x0 0xe080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,eliza-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -2690,6 +2683,13 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; }; + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,eliza-lpass-ag-noc"; + reg = <0x0 0x07e40000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,eliza-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x40000>, @@ -2824,320 +2824,6 @@ spmi_bus1: spmi@c432000 { }; }; - apps_smmu: iommu@15000000 { - compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0x0 0x15000000 0x0 0x100000>; - - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - #iommu-cells = <2>; - #global-interrupts = <1>; - - dma-coherent; - }; - - intc: interrupt-controller@17100000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x17100000 0x0 0x10000>, - <0x0 0x17180000 0x0 0x200000>; - - interrupts = ; - - #interrupt-cells = <3>; - interrupt-controller; - - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic_its: msi-controller@17140000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0x17140000 0x0 0x40000>; - - msi-controller; - #msi-cells = <1>; - }; - }; - - apps_rsc: rsc@17a00000 { - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x17a00000 0x0 0x10000>, - <0x0 0x17a10000 0x0 0x10000>, - <0x0 0x17a20000 0x0 0x10000>; - reg-names = "drv-0", - "drv-1", - "drv-2"; - - interrupts = , - , - ; - - power-domains = <&cluster_pd>; - label = "apps_rsc"; - - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,eliza-rpmh-clk"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmhpd: power-controller { - compatible = "qcom,eliza-rpmhpd"; - - operating-points-v2 = <&rpmhpd_opp_table>; - - #power-domain-cells = <1>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp-16 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp-48 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d3: opp-50 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d2: opp-52 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d1: opp-56 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d0: opp-60 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp-64 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_l1: opp-80 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp-128 { - opp-level = ; - }; - - rpmhpd_opp_svs_l0: opp-144 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp-192 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp-224 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp-256 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp-320 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp-336 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp-384 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp-416 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l2: opp-432 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l3: opp-448 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l4: opp-452 { - opp-level = ; - }; - - rpmhpd_opp_super_turbo_no_cpr: opp-480 { - opp-level = ; - }; - }; - }; - }; - - epss_l3: interconnect@17d90000 { - compatible = "qcom,eliza-epss-l3", "qcom,epss-l3"; - reg = <0x0 0x17d90000 0x0 0x1000>; - - clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@17d91000 { - compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0x0 0x17d91000 0x0 0x1000>, - <0x0 0x17d92000 0x0 0x1000>, - <0x0 0x17d93000 0x0 0x1000>; - reg-names = "freq-domain0", - "freq-domain1", - "freq-domain2"; - - interrupts = , - , - ; - interrupt-names = "dcvsh-irq-0", - "dcvsh-irq-1", - "dcvsh-irq-2"; - - clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - #clock-cells = <1>; - }; - tlmm: pinctrl@f100000 { compatible = "qcom,eliza-tlmm"; reg = <0x0 0x0f100000 0x0 0xf00000>; @@ -3592,6 +3278,320 @@ data-pins { }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17100000 0x0 0x10000>, + <0x0 0x17180000 0x0 0x200000>; + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17140000 0x0 0x40000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + + interrupts = , + , + ; + + power-domains = <&cluster_pd>; + label = "apps_rsc"; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,eliza-rpmh-clk"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmhpd: power-controller { + compatible = "qcom,eliza-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level = ; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level = ; + }; + }; + }; + }; + + epss_l3: interconnect@17d90000 { + compatible = "qcom,eliza-epss-l3", "qcom,epss-l3"; + reg = <0x0 0x17d90000 0x0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + gem_noc: interconnect@24100000 { compatible = "qcom,eliza-gem-noc"; reg = <0x0 0x24100000 0x0 0x163080>; From 9b31a0c535433e02acc9e9719f4eb797fd155f83 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Sat, 18 Apr 2026 10:40:00 +0000 Subject: [PATCH 103/131] arm64: dts: qcom: eliza: Add IMEM node Add a node for the IMEM found on Eliza, which contains pil-reloc-info and the modem tables for IPA, among others. Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260418-eliza-imem-v3-3-bfbd499b6e77@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index abfaea2f6b75..466d49e421bf 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -3278,6 +3278,26 @@ data-pins { }; }; + sram@14680000 { + compatible = "qcom,eliza-imem", "mmio-sram"; + reg = <0x0 0x14680000 0x0 0x2c000>; + ranges = <0x0 0x0 0x14680000 0x2c000>; + + no-memory-wc; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc-sram@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + ipa_modem_tables: modem-tables-sram@3000 { + reg = <0x3000 0x2000>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; From 2597338625b4e391d4d1aecbe2356f43cdacc057 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Sun, 12 Apr 2026 15:38:43 +0000 Subject: [PATCH 104/131] arm64: dts: qcom: eliza: Fix reserved memory addresses & sizes Update cpusys_vm_mem from 256KiB to 4MiB, cpucp_mem from 2MiB to 1MiB and fix cpucp_scandump_mem node name to match actual reg address. This matches the downstream memmap and kera-reserved-memory.dtsi. Signed-off-by: Alexander Koskovich Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260412-eliza-reserved-memory-fix-v1-1-05cb3e33a9fe@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 466d49e421bf..efac6cb6bb3b 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -411,12 +411,12 @@ gunyah_hyp_mem: gunyah-hyp@80000000 { }; cpusys_vm_mem: cpusys-vm-mem@80e00000 { - reg = <0x0 0x80e00000 0x0 0x40000>; + reg = <0x0 0x80e00000 0x0 0x400000>; no-map; }; cpucp_mem: cpucp@81200000 { - reg = <0x0 0x81200000 0x0 0x200000>; + reg = <0x0 0x81200000 0x0 0x100000>; no-map; }; @@ -450,7 +450,7 @@ smem_mem: smem@81d00000 { no-map; }; - cpucp_scandump_mem: cpucp-scandump@82000000 { + cpucp_scandump_mem: cpucp-scandump@82200000 { reg = <0x0 0x82200000 0x0 0x180000>; no-map; }; From b7c9047f851e80b580aba485b61785c7554b992c Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:29 +0530 Subject: [PATCH 105/131] arm64: dts: qcom: milos: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for milos. Fixes: 04bb37433330e ("arm64: dts: qcom: milos: Add UFS nodes") Signed-off-by: Harshal Dev Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-12-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 4a64a98a434b..a6e463f3885d 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1275,7 +1275,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From 90825ab392ac15a51f62e3f561ad77e0226a1cfc Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:30 +0530 Subject: [PATCH 106/131] arm64: dts: qcom: eliza: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for eliza. Fixes: af20af39fc09b ("arm64: dts: qcom: Introduce Eliza Soc base dtsi") Signed-off-by: Harshal Dev Reviewed-by: Konrad Dybcio Fixes: 54a4f0239f2e ("KVM: MMU: make kvm_mmu_zap_page() return the Reviewed-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-13-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 4a7a0ac40ce6..7e97361a5dc5 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -843,7 +843,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From 11b48f6d5ed505ced9cd3645d6615279198a7a54 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:20 +0530 Subject: [PATCH 107/131] arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kaanapali. Fixes: 2eeb5767d53f4 ("arm64: dts: qcom: Introduce Kaanapali SoC") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-3-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index bcd1cee31356..370c9af7c37d 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2538,7 +2538,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From 04566e287b35fde9fd129db5fdf6a96e336af55c Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:21 +0530 Subject: [PATCH 108/131] arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for lemans. Fixes: 96272ba7103d4 ("arm64: dts: qcom: sa8775p: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Reviewed-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-4-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index bc7b4f65ad5e..dffbe1f5250a 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3104,7 +3104,11 @@ ice: crypto@1d88000 { compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 68d5d9701a7ab1b1f9c76feaa3a24ca716f03f0b Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:22 +0530 Subject: [PATCH 109/131] arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for monaco. Fixes: cc9d29aad876d ("arm64: dts: qcom: qcs8300: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-5-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index ce6ff259cb4a..2660c161c3d7 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2737,7 +2737,11 @@ ice: crypto@1d88000 { compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; crypto: crypto@1dfa000 { From 7cd7271ac525e4eadd22734f418219f247638f43 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:23 +0530 Subject: [PATCH 110/131] arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sc7180. Fixes: 858536d9dc946 ("arm64: dts: qcom: sc7180: Add UFS nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-6-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8341a7c4a4c6..fa65c485172f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1605,7 +1605,11 @@ ice: crypto@1d90000 { compatible = "qcom,sc7180-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d90000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ipa: ipa@1e40000 { From cca53c338ad87edc4b46d2d82730fd8ca01a164f Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:24 +0530 Subject: [PATCH 111/131] arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kodiak. Fixes: dfd5ee7b34bb7 ("arm64: dts: qcom: sc7280: Add inline crypto engine") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Tested-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-7-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index c51beada8c7d..fa540d8c2615 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2579,7 +2579,11 @@ ice: crypto@1d88000 { compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 3a5cb1ccbfb3141862b28f24cd5050083233aae7 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:25 +0530 Subject: [PATCH 112/131] arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450. Fixes: 86b0aef435851 ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-8-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e0c37ce3042a..47b028259d91 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5374,7 +5374,11 @@ ice: crypto@1d88000 { compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 52696dbbe7bbe0c8fc8c17133ffb5133b8cf37a6 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:26 +0530 Subject: [PATCH 113/131] arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8550. Fixes: b8630c48b43fc ("arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-9-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index b7a7c49db077..1bdd740039b0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2822,7 +2822,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From c62b084d5d1564f808408a2f7d4c514e57cd4106 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:27 +0530 Subject: [PATCH 114/131] arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8650. Fixes: 10e0246712951 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-10-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 1604bc8cff37..e2d98cf6adca 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4081,7 +4081,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 081ac792f0ea6d27a4b130c70cfd7544efee8137 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 16 Apr 2026 17:29:28 +0530 Subject: [PATCH 115/131] arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8750. Fixes: b1dac789c650a ("arm64: dts: qcom: sm8750: Add ICE nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-11-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 70830cb49e73..5a5761e5ce2c 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2113,7 +2113,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 4bd073e00fd79c0aead74ad64ade48c904221245 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 28 Jan 2026 17:18:50 +0530 Subject: [PATCH 116/131] arm64: dts: qcom: lemans: Add eDP ref clock for eDP PHYs The eDP PHY nodes on lemans were missing the reference clock voting. This initially went unnoticed because the clock was implicitly enabled by the UFS PHY driver, and the eDP PHY happened to rely on that. After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off calls"), the UFS driver no longer keeps the reference clock enabled. As a result, the eDP PHY fails to power on. To fix this, add eDP reference clock for eDP PHYs on lemans chipset ensuring reference clock is enabled. Fixes: e1e3e5673f8d7 ("arm64: dts: qcom: sa8775p: add DisplayPort device nodes") Signed-off-by: Ritesh Kumar Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260128114853.2543416-3-quic_riteshk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index dffbe1f5250a..522ba43836a2 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5658,9 +5658,11 @@ mdss0_dp0_phy: phy@aec2a00 { <0x0 0x0aec2000 0x0 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; @@ -5677,9 +5679,11 @@ mdss0_dp1_phy: phy@aec5a00 { <0x0 0x0aec5000 0x0 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; From 85abff1549515c453dd113c4a4e3dd75ef3cd30d Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 9 Apr 2026 23:43:29 +0530 Subject: [PATCH 117/131] arm64: dts: qcom: Drop unused remoteproc_adsp_glink label The remoteproc_adsp_glink label on the ADSP glink-edge node has no users in the upstream tree across all affected SoCs. The only user of this label is qcs6490-audioreach.dtsi which references the label defined in its own SoC dtsi and is left untouched. Remove the label from kaanapali, lemans, monaco, sar2130p, sc8180x, sc8280xp, sm8450, sm8550, sm8650 and sm8750. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260409181329.556899-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 +- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 +- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 +- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 370c9af7c37d..7aa9653bd456 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2638,7 +2638,7 @@ remoteproc_adsp: remoteproc@6800000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 522ba43836a2..353a6e6fd3ac 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -8072,7 +8072,7 @@ remoteproc_adsp: remoteproc@30000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 2660c161c3d7..e4c8466f941b 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2799,7 +2799,7 @@ remoteproc_adsp: remoteproc@3000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index d65ad0df6865..3c9529bb2f76 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1612,7 +1612,7 @@ remoteproc_adsp: remoteproc@3000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index e87e82fa73e9..45391768e245 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3755,7 +3755,7 @@ remoteproc_adsp: remoteproc@17300000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts = ; label = "lpass"; qcom,remote-pid = <2>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ee02acd18856..afe3f8018b22 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2956,7 +2956,7 @@ remoteproc_adsp: remoteproc@3000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 47b028259d91..56cb6e959e4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2798,7 +2798,7 @@ remoteproc_adsp: remoteproc@3000000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 1bdd740039b0..396201905ef2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3158,7 +3158,7 @@ remoteproc_adsp: remoteproc@6800000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e2d98cf6adca..160ead25ecf7 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4490,7 +4490,7 @@ remoteproc_adsp: remoteproc@6800000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 5a5761e5ce2c..4e0ae737c281 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2248,7 +2248,7 @@ remoteproc_adsp: remoteproc@6800000 { status = "disabled"; - remoteproc_adsp_glink: glink-edge { + glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; From ecabfe832b817bd1c1fdb8841d7bc706bf621ef1 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Mon, 18 May 2026 02:52:53 -0700 Subject: [PATCH 118/131] arm64: dts: qcom: glymur: Fix wrong interrupt number for i2c19 The i2c19 node at 0x88c000 uses GIC SPI 584, but that interrupt belongs to the neighboring i2c18/spi18 node at 0x888000. The correct interrupt for i2c19 is GIC SPI 585, as used by its sibling nodes spi19 and uart19 which share the same register base and clock. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Gopikrishna Garmidi Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260518-glymur-fix-i2c19-irq-v1-1-7d5968bd9b2b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 376fdb3cc8ad..85040459a452 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -989,7 +989,7 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, i2c19: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x0088c000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS From 89e77275b55eac3d3b8027c9806eb32b24b05023 Mon Sep 17 00:00:00 2001 From: Anup Kulkarni Date: Tue, 19 May 2026 12:19:54 +0530 Subject: [PATCH 119/131] arm64: dts: qcom: lemans-evk: Enable CAN RX via I2C GPIO expander The LeMans EVK board routes the RX lines of CAN controllers 2, 4, and 6 (part of the RTSS subsystem) through a signal multiplexer controlled by GPIO 4 of the I2C GPIO expander at address 0x3b. The remaining CAN controllers, out of 8 total on RTSS, are wired directly to their transceivers. The multiplexer select pin defaults low on reset, disconnecting CAN 2, 4, and 6 RX lines from their respective transceivers, which results in no data being received on these interfaces. Configure GPIO 4 as output-high to assert the mux select line at boot, connecting the RX signals of CAN 2, 4, and 6 to their transceivers as required by the EVK board wiring. Signed-off-by: Anup Kulkarni Reviewed-by: Dmitry Baryshkov Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260519064954.2759960-1-anup.kulkarni@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index c665db6a4595..34dfc8d22b6a 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -616,6 +616,13 @@ expander3: gpio@3b { interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&expander3_int>; pinctrl-names = "default"; + + rtss-can-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rtss-can-sel"; + }; }; eeprom@50 { From f6dd5665d8e525484c2d0ebdb7004319024ee640 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 20 May 2026 12:54:37 +0300 Subject: [PATCH 120/131] arm64: dts: qcom: qcs6490-rb3gen2: add rmtfs node Downstream kernels for RB3 Gen2 don't specify the RMTFS address, instead the kernel is supposed to allocate rmtfs buffers dynamically. The upstream kernel doesn't support dynamic allocation of RMTFS buffers, so use the fixed allocation. The RMTFS node (and corresponding interface) is required for the modem DSP to work (which otherwise would crash). Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260520-rb3g2-rmtfs-ipa-v1-1-8b3942ded279@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index ceb68a890bf4..37a3b51323ce 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -165,6 +165,15 @@ debug_vm_mem: debug-vm@d0600000 { reg = <0x0 0xd0600000 0x0 0x100000>; no-map; }; + + rmtfs_mem: memory@f8500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8500000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = , ; + }; }; gpio-keys { From 1f7d0c42a08d157294b8dce4ac162c2853f287d0 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 20 May 2026 09:42:45 +0800 Subject: [PATCH 121/131] arm64: dts: qcom: glymur: add coresight nodes Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF. These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and some small subsystems, such as GCC, IPCC, PMU and so on. Delete cti_wpss DT node on Mahua since this device will cause NoC issue on Mahua device. Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260520-add-coresight-nodes-for-glymur-v6-1-0bfdcdfce3ec@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1097 ++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/mahua.dtsi | 1 + 2 files changed, 1098 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 85040459a452..ca0fd85e2946 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -362,6 +362,18 @@ domain_ss3: domain-sleep-0 { }; }; + dummy-sink { + compatible = "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = <&swao_rep_out1>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-glymur", "qcom,scm"; @@ -5712,6 +5724,1035 @@ rx-pins { }; }; + stm: stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + qdss_tpda_in1: endpoint { + remote-endpoint = <&spdm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = <&funnel0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + spdm_tpdm_out: endpoint { + remote-endpoint = <&qdss_tpda_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel0_in0: endpoint { + remote-endpoint = <&tn_ag_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel0_in6: endpoint { + remote-endpoint = <&qdss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&aoss_funnel_in6>; + }; + }; + }; + }; + + tpdm@1102c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1102c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + gcc_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in36>; + }; + }; + }; + }; + + tpdm@11180000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11180000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + cdsp_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in0>; + }; + }; + }; + }; + + tpdm@11185000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11185000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + cdsp_dpm1_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in5>; + }; + }; + }; + }; + + tpdm@11186000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11186000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + cdsp_dpm2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in6>; + }; + }; + }; + }; + + tpda@11188000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11188000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + cdsp_tpda_in0: endpoint { + remote-endpoint = <&cdsp_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + cdsp_tpda_in1: endpoint { + remote-endpoint = <&cdsp_llm_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + cdsp_tpda_in2: endpoint { + remote-endpoint = <&cdsp_llm2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + cdsp_tpda_in3: endpoint { + remote-endpoint = <&cdsp_cmsr_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + cdsp_tpda_in4: endpoint { + remote-endpoint = <&cdsp_cmsr2_tpdm_out>; + }; + }; + + port@5 { + reg = <5>; + + cdsp_tpda_in5: endpoint { + remote-endpoint = <&cdsp_dpm1_tpdm_out>; + }; + }; + + port@6 { + reg = <6>; + + cdsp_tpda_in6: endpoint { + remote-endpoint = <&cdsp_dpm2_tpdm_out>; + }; + }; + }; + + out-ports { + port { + cdsp_tpda_out: endpoint { + remote-endpoint = <&cdsp_funnel_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11189000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + cdsp_funnel_in0: endpoint { + remote-endpoint = <&cdsp_tpda_out>; + }; + }; + }; + + out-ports { + port { + cdsp_funnel_out: endpoint { + remote-endpoint = <&tn_ag_in53>; + }; + }; + }; + }; + + cti@11193000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x11193000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti_wpss: cti@111ab000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x111ab000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@111d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + qm_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in35>; + }; + }; + }; + }; + + itnoc@11200000 { + compatible = "qcom,coresight-itnoc"; + reg = <0x0 0x11200000 0x0 0x3c00>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + + tn_ag_in6: endpoint { + remote-endpoint = <&mm_dsb_tpdm_out>; + }; + }; + + port@10 { + reg = <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint = <&east_dsb_tpdm_out>; + }; + }; + + port@21 { + reg = <0x21>; + + tn_ag_in33: endpoint { + remote-endpoint = <&west_dsb_tpdm_out>; + }; + }; + + port@23 { + reg = <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint = <&qm_tpdm_out>; + }; + }; + + port@24 { + reg = <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint = <&gcc_tpdm_out>; + }; + }; + + port@32 { + reg = <0x32>; + + tn_ag_in50: endpoint { + remote-endpoint = <&pcie_rscc_tpda_out>; + }; + }; + + port@35 { + reg = <0x35>; + + tn_ag_in53: endpoint { + remote-endpoint = <&cdsp_funnel_out>; + }; + }; + + port@3f { + reg = <0x3f>; + + tn_ag_in63: endpoint { + remote-endpoint = <¢er_dsb_tpdm_out>; + }; + }; + + port@40 { + reg = <0x40>; + + tn_ag_in64: endpoint { + remote-endpoint = <&ipcc_cmb_tpdm_out>; + }; + }; + + port@41 { + reg = <0x41>; + + tn_ag_in65: endpoint { + remote-endpoint = <&qrng_tpdm_out>; + }; + }; + + port@42 { + reg = <0x42>; + + tn_ag_in66: endpoint { + remote-endpoint = <&pmu_tpdm_out>; + }; + }; + + port@43 { + reg = <0x43>; + + tn_ag_in67: endpoint { + remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; + }; + }; + + port@44 { + reg = <0x44>; + + tn_ag_in68: endpoint { + remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; + }; + }; + + port@45 { + reg = <0x45>; + + tn_ag_in69: endpoint { + remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; + }; + }; + + port@4b { + reg = <0x4b>; + + tn_ag_in75: endpoint { + remote-endpoint = <&south_dsb2_tpdm_out>; + }; + }; + + port@52 { + reg = <0x52>; + + tn_ag_in82: endpoint { + remote-endpoint = <&south_dsb_tpdm_out>; + }; + }; + + port@53 { + reg = <0x53>; + + tn_ag_in83: endpoint { + remote-endpoint = <¢er_dsb1_tpdm_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint = <&funnel0_in0>; + }; + }; + }; + }; + + tpdm@11207000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11207000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + mm_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in6>; + }; + }; + }; + }; + + tpdm@1120b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1120b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + east_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@11213000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11213000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + west_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in33>; + }; + }; + }; + }; + + tpdm@11219000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11219000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + center_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in63>; + }; + }; + }; + }; + + tpdm@1121a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + ipcc_cmb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in64>; + }; + }; + }; + }; + + tpdm@1121b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qrng_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in65>; + }; + }; + }; + }; + + tpdm@1121c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + pmu_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in66>; + }; + }; + }; + }; + + tpdm@1121d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb0_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in67>; + }; + }; + }; + }; + + tpdm@1121e000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb1_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in68>; + }; + }; + }; + }; + + tpdm@1121f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1121f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + rdpm_west_cmb2_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in69>; + }; + }; + }; + }; + + tpdm@11220000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11220000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + center_dsb1_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in83>; + }; + }; + }; + }; + + tpdm@11224000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11224000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + south_dsb2_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in75>; + }; + }; + }; + }; + + tpdm@11228000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11228000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + south_dsb_tpdm_out: endpoint { + remote-endpoint = <&tn_ag_in82>; + }; + }; + }; + }; + + tpdm@11470000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11470000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + pcie_rscc_tpdm_out: endpoint { + remote-endpoint = <&pcie_rscc_tpda_in0>; + }; + }; + }; + }; + + tpda@11471000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11471000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + pcie_rscc_tpda_in0: endpoint { + remote-endpoint = <&pcie_rscc_tpdm_out>; + }; + }; + }; + + out-ports { + port { + pcie_rscc_tpda_out: endpoint { + remote-endpoint = <&tn_ag_in50>; + }; + }; + }; + }; + + tpdm@11c03000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c03000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio4_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in4>; + }; + }; + }; + }; + + funnel@11c04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11c04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + + aoss_funnel_in5: endpoint { + remote-endpoint = <&aoss_tpda_out>; + }; + }; + + port@6 { + reg = <6>; + + aoss_funnel_in6: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + }; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint = <&etf0_in>; + }; + }; + }; + }; + + tmc_etf: tmc@11c05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x11c05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint = <&aoss_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint = <&swao_rep_in>; + }; + }; + }; + }; + + replicator@11c06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x11c06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = <&etf0_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + swao_rep_out1: endpoint { + remote-endpoint = <&eud_in>; + }; + }; + }; + }; + + tpda@11c08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11c08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + aoss_tpda_in0: endpoint { + remote-endpoint = <&swao_prio0_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + aoss_tpda_in1: endpoint { + remote-endpoint = <&swao_prio1_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + aoss_tpda_in2: endpoint { + remote-endpoint = <&swao_prio2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + aoss_tpda_in3: endpoint { + remote-endpoint = <&swao_prio3_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + aoss_tpda_in4: endpoint { + remote-endpoint = <&swao_prio4_tpdm_out>; + }; + }; + + port@5 { + reg = <5>; + + aoss_tpda_in5: endpoint { + remote-endpoint = <&swao_tpdm_out>; + }; + }; + }; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = <&aoss_funnel_in5>; + }; + }; + }; + }; + + tpdm@11c09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio0_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@11c0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio1_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@11c0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio2_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@11c0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio3_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@11c0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11c0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + swao_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in5>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,glymur-smmu-500", "qcom,smmu-500", @@ -7513,4 +8554,60 @@ gpuss-1-critical { }; }; }; + + tpdm-cdsp-llm { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + cdsp_llm_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + cdsp_llm2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in2>; + }; + }; + }; + }; + + tpdm-cdsp-cmsr { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + cdsp_cmsr_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in3>; + }; + }; + }; + }; + + tpdm-cdsp-cmsr2 { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + cdsp_cmsr2_tpdm_out: endpoint { + remote-endpoint = <&cdsp_tpda_in4>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi index 990a02c6afc1..22822b6b2e8b 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -21,6 +21,7 @@ /delete-node/ &cpu_pd15; /delete-node/ &cpu_pd16; /delete-node/ &cpu_pd17; +/delete-node/ &cti_wpss; /delete-node/ &thermal_aoss_6; /delete-node/ &thermal_aoss_7; /delete-node/ &thermal_cpu_2_0_0; From b39a174a535841e71c59661cc92408b710e0fe6a Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Wed, 1 Apr 2026 02:25:07 +0000 Subject: [PATCH 122/131] arm64: dts: qcom: milos: Add qfprom efuse node Add the qfprom efuse node and describe where the GPU speedbin fuse is located on Milos. Note that for SM7635-AB at least, the value is "221", the max frequency for this is 1050MHz. There's another speedbin out there for 1150MHz but we do not know the value for it so just document in this commit. Once the value is discovered we should add the speedbins to the A810 Adreno entry and update devicetree. Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260331-milos-qfprom-v1-2-36017cc642db@pm.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 886d8514ce33..8c9232988953 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1331,6 +1331,18 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + qfprom: efuse@221c8000 { + compatible = "qcom,milos-qfprom", "qcom,qfprom"; + reg = <0x0 0x221c8000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@138 { + reg = <0x138 0x2>; + bits = <0 9>; + }; + }; + remoteproc_adsp: remoteproc@3000000 { compatible = "qcom,milos-adsp-pas"; reg = <0x0 0x03000000 0x0 0x10000>; From db9900e518b2992cbbcbfb7572c2d436ec0feb6d Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Tue, 31 Mar 2026 19:24:21 +0530 Subject: [PATCH 123/131] arm64: dts: qcom: glymur: Add qfprom efuse node Add the qfprom (Qualcomm Fuse ROM) efuse node and gpu speed bin child node for Glymur SoC Signed-off-by: Pankaj Patil Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260331-glymur-qfprom-v1-2-5b4284d23c80@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index ca0fd85e2946..b129e268aab4 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -7336,6 +7336,18 @@ nsp_noc: interconnect@320c0000 { #interconnect-cells = <2>; }; + qfprom: efuse@361c8000 { + compatible = "qcom,glymur-qfprom", "qcom,qfprom"; + reg = <0x0 0x361c8000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@138 { + reg = <0x138 0x2>; + bits = <0 9>; + }; + }; + imem: sram@81e08600 { compatible = "mmio-sram"; reg = <0x0 0x81e08600 0x0 0x300>; From 0299c007e6f34a2a5b724c332b86be77409ea729 Mon Sep 17 00:00:00 2001 From: Shuai Zhang Date: Wed, 29 Apr 2026 18:35:37 +0800 Subject: [PATCH 124/131] arm64: dts: qcom: monaco-arduino-monza: Add Bluetooth UART node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QCA2066 Bluetooth chip is powered by a board-level 3.3 V supply provided by the hardware. This change connects the Bluetooth controller via UART10, and the corresponding GPIO is used to enable the Bluetooth chip. basic function test step: - bluetoothctl power on/off - bluetoothctl scan bredr/le - bluetoothctl pair - bluetoothctl connect low-state test and state: - rtcwake -d /dev/rtc0 -m no -s 30 && systemctl suspend cat /sys/kernel/debug/suspend_stats success: 1 fail: 0 failed_freeze: 0 failed_prepare: 0 failed_suspend: 0 failed_suspend_late: 0 failed_suspend_noirq: 0 failed_resume: 0 failed_resume_early: 0 failed_resume_noirq: 0 failures: last_failed_dev: last_failed_errno: 0 0 last_failed_step: Signed-off-by: Shuai Zhang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260429103537.1282497-1-shuai.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index ca14f0ea4dae..379b796f261f 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -21,6 +21,7 @@ aliases { ethernet0 = ðernet0; i2c1 = &i2c1; serial0 = &uart7; + serial1 = &uart10; }; chosen { @@ -454,6 +455,16 @@ &uart7 { status = "okay"; }; +&uart10 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,qca2066-bt"; + enable-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; + clocks = <&sleep_clk>; + }; +}; + &usb_1 { status = "okay"; }; From f3cd85f60c5eb2d817af6c62465018dd941ce4f3 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 29 Apr 2026 15:16:53 +0200 Subject: [PATCH 125/131] arm64: dts: qcom: sdm845-xiaomi-beryllium: Correct IPA FW path The path was accidentally reverted back to old while refactoring of the device-tree. Fixes: 5bde31dc7b17 ("arm64: dts: qcom: sdm845-xiaomi-beryllium: Add placeholders and sort") Signed-off-by: Joel Selvaraj Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260429-beryllium-ipa-fix-v1-1-816326ba9047@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 9b7fdbca9e1c..54e58ca04693 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -287,7 +287,7 @@ &ibb { &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/ipa_fws.mbn"; status = "okay"; }; From 7a473107f9785700a5c57cee69f60c19a9703f95 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 11 May 2026 16:26:41 +0530 Subject: [PATCH 126/131] arm64: dts: qcom: ipq5210: add watchdog node Add the watchdog device node for IPQ5210 SoC. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260511-ipq5210_wdt-v1-1-870c4b7f77b6@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 3761eb03ab24..2cdc10529c48 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -236,6 +236,13 @@ v2m2: v2m@2000 { }; }; + watchdog@b017000 { + compatible = "qcom,apss-wdt-ipq5210", "qcom,kpss-wdt"; + reg = <0x0 0x0b017000 0x0 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; From 6ba85ffe796ab4eff37e3229999b34a99954fb49 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Thu, 7 May 2026 22:34:35 +0800 Subject: [PATCH 127/131] arm64: dts: qcom: sc8280xp: drop unused polling-delay-passive properties Remove the unused polling-delay-passive properties from thermal nodes without a passive trip point. Signed-off-by: Xilin Wu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-sc8280xp-thermal-zones-v1-1-33d4395b1be9@radxa.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index afe3f8018b22..a2bd6b10e475 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6898,8 +6898,6 @@ sound: sound { thermal-zones { cpu0-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 1>; trips { @@ -6912,8 +6910,6 @@ cpu-crit { }; cpu1-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 2>; trips { @@ -6926,8 +6922,6 @@ cpu-crit { }; cpu2-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 3>; trips { @@ -6940,8 +6934,6 @@ cpu-crit { }; cpu3-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 4>; trips { @@ -6954,8 +6946,6 @@ cpu-crit { }; cpu4-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 5>; trips { @@ -6968,8 +6958,6 @@ cpu-crit { }; cpu5-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 6>; trips { @@ -6982,8 +6970,6 @@ cpu-crit { }; cpu6-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 7>; trips { @@ -6996,8 +6982,6 @@ cpu-crit { }; cpu7-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 8>; trips { @@ -7010,8 +6994,6 @@ cpu-crit { }; cluster0-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 9>; trips { @@ -7051,8 +7033,6 @@ trip-point1 { }; mem-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 15>; trips { From 1daf54d8100e0e92c826ac8a2b888008b2571cc0 Mon Sep 17 00:00:00 2001 From: Saurabh Anand Date: Fri, 15 May 2026 12:44:48 +0530 Subject: [PATCH 128/131] arm64: dts: qcom: sm8750: allow mode-switch events to reach the QMP Combo PHY Allow mode-switch events to reach the QMP Combo PHY to support setting the QMP Combo PHY in DP 4Lanes Altmode. Signed-off-by: Saurabh Anand Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260515071448.1845500-1-saurabh.anand@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 4e0ae737c281..fafed417c66f 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2794,6 +2794,7 @@ usb_dp_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From 181bef739979466b6ede95b34d6c94d0250b1c0e Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Fri, 15 May 2026 11:53:23 +0530 Subject: [PATCH 129/131] arm64: dts: qcom: hamoa-iot-evk: add MCP2518FD CAN on spi18 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the Microchip MCP2518FD CAN-FD controller on hamoa. The controller is connected via SPI18 and uses a 40 MHz oscillator. Signed-off-by: Viken Dadhaniya Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-hamoa-spi-can-devicetree-v2-1-d0e922608065@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 460f27dcd6f6..c7ba4b353ddd 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -29,6 +29,14 @@ backlight: backlight { pinctrl-names = "default"; }; + clocks { + mcp2518fd_osc: clock-40000000 { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + wcd938x: audio-codec { compatible = "qcom,wcd9385-codec"; @@ -1227,6 +1235,19 @@ tpm@0 { }; }; +&spi18 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 68 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mcp2518fd_osc>; + spi-max-frequency = <14000000>; + microchip,xstbyen; + }; +}; + &swr0 { status = "okay"; From fe9f4a46895dc3062cedcdd38772dd578de9e62f Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Wed, 13 May 2026 13:25:48 -0400 Subject: [PATCH 130/131] arm64: dts: qcom: sdm670-google: add common device tree include The Pixel 3a XL can be supported by reusing most of the device tree from the Pixel 3a. Move the common elements to a common device tree include like with other devices. Since the original devicetree should only specify non-XL properties, it needs to be completely rewritten. Also change the SPDX license identifier from GPL-2.0 (which was deprecated as it can be misinterpreted as GPLv2 or later) into GPL-2.0-only. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Assisted-by: "Claude Code Review Bot":claude-opus-4-6 Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260513172549.1345-2-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm670-google-common.dtsi | 712 +++++++++++++++++ .../boot/dts/qcom/sdm670-google-sargo.dts | 714 +----------------- 2 files changed, 725 insertions(+), 701 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi new file mode 100644 index 000000000000..0f57b915186b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for Google Pixel 3a, adapted from google-blueline device tree, + * xiaomi-lavender device tree, and oneplus-common device tree. + * + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "sdm670.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &adsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +/ { + aliases { }; + + battery: battery { + compatible = "simple-battery"; + + voltage-min-design-microvolt = <3312000>; + voltage-max-design-microvolt = <4400000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + memory-region = <&fb_mem>; + width = <1080>; + /* height is in specific device trees */ + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin>; + + key-vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + mpss_region: mpss@8b000000 { + reg = <0 0x8b000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@94800000 { + reg = <0 0x94800000 0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@94d00000 { + reg = <0 0x94d00000 0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@94e00000 { + reg = <0 0x94e00000 0 0x800000>; + no-map; + }; + + mba_region: mba@95600000 { + reg = <0 0x95600000 0 0x200000>; + no-map; + }; + + adsp_mem: adsp@95800000 { + reg = <0 0x95800000 0 0x2200000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@97a00000 { + reg = <0 0x97a00000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@97a10000 { + reg = <0 0x97a10000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97a15000 { + reg = <0 0x97a15000 0 0x2000>; + no-map; + }; + + fb_mem: framebuffer-region@9c000000 { + reg = <0 0x9c000000 0 0x2400000>; + no-map; + }; + + /* Also includes ramoops regions */ + debug_info_mem: debug-info@a1800000 { + reg = <0 0xa1800000 0 0x411000>; + no-map; + }; + }; + + /* + * The touchscreen regulator seems to be controlled somehow by a gpio. + * Model it as a fixed regulator and keep it on. Without schematics we + * don't know how this is actually wired up... + */ + ts_1p8_supply: ts-1p8-regulator { + compatible = "regulator-fixed"; + regulator-name = "ts_1p8_supply"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * Supply map from xiaomi-lavender specifies this as the supply for + * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies + * this as a power domain. Set this as a fixed regulator with the same + * voltage as lavender until display is needed to avoid unneccessarily + * using a deprecated binding (regulator-fixed-domain). + */ + vreg_s2b_1p05: vreg-s2b-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + cam_front_ldo: cam-front-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_front_ldo"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-enable-ramp-delay = <135>; + + gpios = <&pm660l_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_front_ldo_pin>; + pinctrl-names = "default"; + }; + + cam_vio_ldo: cam-vio-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_vio_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <233>; + + gpios = <&pm660_gpios 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_vio_pin>; + pinctrl-names = "default"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm660-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l1-l6-l7-supply = <&vreg_s6a_0p87>; + vdd-l2-l3-supply = <&vreg_s2b_1p05>; + vdd-l5-supply = <&vreg_s2b_1p05>; + vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_2p04>; + vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: smps4 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s6a_0p87: smps6 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1352000>; + regulator-enable-ramp-delay = <150>; + }; + + /* LDOs */ + vreg_l1a_1p225: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5a_0p848: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6a_1p3: ldo6 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7a_1p2: ldo7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8a_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-always-on; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l17a_1p8: ldo17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + }; + }; + + regulators-1 { + compatible = "qcom,pm660l-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>; + vdd-l2-supply = <&vreg_bob>; + vdd-l3-l5-l7-l8-supply = <&vreg_bob>; + vdd-l4-l6-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + /* LDOs */ + vreg_l1b_0p925: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <900000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l2b_2p95: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3b_3p0: ldo3 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3008000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l4b_2p95: ldo4 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5b_2p95: ldo5 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6b_3p3: ldo6 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7b_3p125: ldo7 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: ldo8 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + }; + + /* + * Downstream specifies a fixed voltage of 3.312 V, but the + * PMIC4 BOB ranges don't support that. Widen the range a + * little to avoid adding a new BOB regulator type. + */ + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <500>; + }; + }; +}; + +&camss { + vdda-phy-supply = <&vreg_l1a_1p225>; + vdda-pll-supply = <&vreg_s6a_0p87>; + + status = "okay"; +}; + +&camss_port1 { + camss_endpoint1: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_front_endpoint>; + }; +}; + +&cci { + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&cci_i2c1 { + camera@1a { + compatible = "sony,imx355"; + reg = <0x1a>; + + clocks = <&camcc CAM_CC_MCLK2_CLK>; + + /* + * The sensor can accept a 24 MHz clock, but 19.2 MHz has + * better driver compatibility. + */ + assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates = <19200000>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + avdd-supply = <&cam_front_ldo>; + dvdd-supply = <&cam_front_ldo>; + dovdd-supply = <&cam_vio_ldo>; + + pinctrl-0 = <&cam_mclk2_default>; + pinctrl-names = "default"; + + rotation = <270>; + orientation = <0>; + + port { + cam_front_endpoint: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <360000000>; + remote-endpoint = <&camss_endpoint1>; + }; + }; + }; +}; + +&gcc { + protected-clocks = , + , + ; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + synaptics-rmi4-i2c@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_default>; + + vio-supply = <&ts_1p8_supply>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <200>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4_f12: rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l1a_1p225>; + status = "okay"; + + panel: panel@0 { + /* compatible is provided in specific device trees */ + reg = <0>; + + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default>; + + power-supply = <&vreg_l6b_3p3>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&pm660_charger { + monitored-battery = <&battery>; + status = "okay"; +}; + +&pm660_gpios { + cam_vio_pin: cam-vio-state { + pins = "gpio13"; + function = "normal"; + power-source = <0>; + }; +}; + +&pm660_rradc { + status = "okay"; +}; + +&pm660l_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <2>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm660l_gpios { + cam_front_ldo_pin: cam-front-state { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + }; + + vol_up_pin: vol-up-state { + pins = "gpio7"; + function = "normal"; + qcom,drive-strength = ; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_1 { + supports-cqe; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + + qcom,ddr-config = <0xc3040873>; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + panel_default: panel-default-state { + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio75"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mode-pins { + pins = "gpio76"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; + + touchscreen_default: ts-default-state { + ts-reset-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + + ts-irq-pins { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts-switch-pins { + pins = "gpio135"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; + + status = "okay"; +}; + +&usb_1 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + /* Only peripheral works for now */ + dr_mode = "peripheral"; + + /* Do not assume that sdm670.dtsi will never support USB 3.0 */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index eba2f3792dd0..c67a0396436b 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -1,720 +1,32 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Device tree for Google Pixel 3a, adapted from google-blueline device tree, - * xiaomi-lavender device tree, and oneplus-common device tree. + * Device tree for Google Pixel 3a (non-XL). * - * Copyright (c) 2022, Richard Acayan. All rights reserved. + * Copyright (c) Richard Acayan. All rights reserved. */ /dts-v1/; -#include -#include -#include -#include -#include -#include "sdm670.dtsi" -#include "pm660.dtsi" -#include "pm660l.dtsi" - -/delete-node/ &mpss_region; -/delete-node/ &venus_mem; -/delete-node/ &wlan_msa_mem; -/delete-node/ &cdsp_mem; -/delete-node/ &mba_region; -/delete-node/ &adsp_mem; -/delete-node/ &ipa_fw_mem; -/delete-node/ &ipa_gsi_mem; -/delete-node/ &gpu_mem; +#include "sdm670-google-common.dtsi" / { model = "Google Pixel 3a"; compatible = "google,sargo", "qcom,sdm670"; - - aliases { }; - - battery: battery { - compatible = "simple-battery"; - - voltage-min-design-microvolt = <3312000>; - voltage-max-design-microvolt = <4400000>; - charge-full-design-microamp-hours = <3000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - framebuffer@9c000000 { - compatible = "simple-framebuffer"; - reg = <0 0x9c000000 0 (1080 * 2220 * 4)>; - width = <1080>; - height = <2220>; - stride = <(1080 * 4)>; - format = "a8r8g8b8"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&vol_up_pin>; - - key-vol-up { - label = "Volume Up"; - linux,code = ; - gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - - mpss_region: mpss@8b000000 { - reg = <0 0x8b000000 0 0x9800000>; - no-map; - }; - - venus_mem: venus@94800000 { - reg = <0 0x94800000 0 0x500000>; - no-map; - }; - - wlan_msa_mem: wlan-msa@94d00000 { - reg = <0 0x94d00000 0 0x100000>; - no-map; - }; - - cdsp_mem: cdsp@94e00000 { - reg = <0 0x94e00000 0 0x800000>; - no-map; - }; - - mba_region: mba@95600000 { - reg = <0 0x95600000 0 0x200000>; - no-map; - }; - - adsp_mem: adsp@95800000 { - reg = <0 0x95800000 0 0x2200000>; - no-map; - }; - - ipa_fw_mem: ipa-fw@97a00000 { - reg = <0 0x97a00000 0 0x10000>; - no-map; - }; - - ipa_gsi_mem: ipa-gsi@97a10000 { - reg = <0 0x97a10000 0 0x5000>; - no-map; - }; - - gpu_mem: gpu@97a15000 { - reg = <0 0x97a15000 0 0x2000>; - no-map; - }; - - framebuffer-region@9c000000 { - reg = <0 0x9c000000 0 0x2400000>; - no-map; - }; - - /* Also includes ramoops regions */ - debug_info_mem: debug-info@a1800000 { - reg = <0 0xa1800000 0 0x411000>; - no-map; - }; - }; - - /* - * The touchscreen regulator seems to be controlled somehow by a gpio. - * Model it as a fixed regulator and keep it on. Without schematics we - * don't know how this is actually wired up... - */ - ts_1p8_supply: ts-1p8-regulator { - compatible = "regulator-fixed"; - regulator-name = "ts_1p8_supply"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3312000>; - - regulator-always-on; - regulator-boot-on; - }; - - /* - * Supply map from xiaomi-lavender specifies this as the supply for - * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies - * this as a power domain. Set this as a fixed regulator with the same - * voltage as lavender until display is needed to avoid unneccessarily - * using a deprecated binding (regulator-fixed-domain). - */ - vreg_s2b_1p05: vreg-s2b-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_s2b"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - cam_front_ldo: cam-front-ldo-regulator { - compatible = "regulator-fixed"; - regulator-name = "cam_front_ldo"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - regulator-enable-ramp-delay = <135>; - - gpios = <&pm660l_gpios 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&cam_front_ldo_pin>; - pinctrl-names = "default"; - }; - - cam_vio_ldo: cam-vio-ldo-regulator { - compatible = "regulator-fixed"; - regulator-name = "cam_vio_ldo"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <233>; - - gpios = <&pm660_gpios 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&cam_vio_pin>; - pinctrl-names = "default"; - }; }; -&apps_rsc { - regulators-0 { - compatible = "qcom,pm660-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - - vdd-l1-l6-l7-supply = <&vreg_s6a_0p87>; - vdd-l2-l3-supply = <&vreg_s2b_1p05>; - vdd-l5-supply = <&vreg_s2b_1p05>; - vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_2p04>; - vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>; - - /* - * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed - * by the Core Power Reduction hardened (CPRh) and the - * Operating State Manager (OSM) HW automatically. - */ - - vreg_s4a_2p04: smps4 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2040000>; - regulator-enable-ramp-delay = <200>; - }; - - vreg_s6a_0p87: smps6 { - regulator-min-microvolt = <1224000>; - regulator-max-microvolt = <1352000>; - regulator-enable-ramp-delay = <150>; - }; - - /* LDOs */ - vreg_l1a_1p225: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1250000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l2a_1p0: ldo2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l3a_1p0: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l5a_0p848: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l6a_1p3: ldo6 { - regulator-min-microvolt = <1248000>; - regulator-max-microvolt = <1304000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l7a_1p2: ldo7 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l8a_1p8: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - regulator-always-on; - }; - - vreg_l9a_1p8: ldo9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l10a_1p8: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l11a_1p8: ldo11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l13a_1p8: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l14a_1p8: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l15a_1p8: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2696000>; - regulator-max-microvolt = <2696000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l17a_1p8: ldo17 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l19a_3p3: ldo19 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-enable-ramp-delay = <250>; - }; - }; - - regulators-1 { - compatible = "qcom,pm660l-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - - vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>; - vdd-l2-supply = <&vreg_bob>; - vdd-l3-l5-l7-l8-supply = <&vreg_bob>; - vdd-l4-l6-supply = <&vreg_bob>; - vdd-bob-supply = <&vph_pwr>; - - /* LDOs */ - vreg_l1b_0p925: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <900000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l2b_2p95: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l3b_3p0: ldo3 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3008000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l4b_2p95: ldo4 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l5b_2p95: ldo5 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l6b_3p3: ldo6 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l7b_3p125: ldo7 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3100000>; - regulator-enable-ramp-delay = <250>; - }; - - vreg_l8b_3p3: ldo8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-enable-ramp-delay = <250>; - }; - - /* - * Downstream specifies a fixed voltage of 3.312 V, but the - * PMIC4 BOB ranges don't support that. Widen the range a - * little to avoid adding a new BOB regulator type. - */ - vreg_bob: bob { - regulator-min-microvolt = <3296000>; - regulator-max-microvolt = <3328000>; - regulator-enable-ramp-delay = <500>; - }; - }; +&battery { + charge-full-design-microamp-hours = <3000000>; }; -&camss { - vdda-phy-supply = <&vreg_l1a_1p225>; - vdda-pll-supply = <&vreg_s6a_0p87>; - - status = "okay"; +&framebuffer { + height = <2220>; }; -&camss_port1 { - camss_endpoint1: endpoint { - data-lanes = <0 1 2 3>; - remote-endpoint = <&cam_front_endpoint>; - }; +&panel { + compatible = "samsung,s6e3fa7-ams559nk06"; }; -&cci { - pinctrl-0 = <&cci1_default>; - pinctrl-1 = <&cci1_sleep>; - pinctrl-names = "default", "sleep"; - - status = "okay"; -}; - -&cci_i2c1 { - camera@1a { - compatible = "sony,imx355"; - reg = <0x1a>; - - clocks = <&camcc CAM_CC_MCLK2_CLK>; - - /* - * The sensor can accept a 24 MHz clock, but 19.2 MHz has - * better driver compatibility. - */ - assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>; - assigned-clock-rates = <19200000>; - - reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; - - avdd-supply = <&cam_front_ldo>; - dvdd-supply = <&cam_front_ldo>; - dovdd-supply = <&cam_vio_ldo>; - - pinctrl-0 = <&cam_mclk2_default>; - pinctrl-names = "default"; - - rotation = <270>; - orientation = <0>; - - port { - cam_front_endpoint: endpoint { - data-lanes = <1 2 3 4>; - link-frequencies = /bits/ 64 <360000000>; - remote-endpoint = <&camss_endpoint1>; - }; - }; - }; -}; - -&gcc { - protected-clocks = , - , - ; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&gpu_zap_shader { - firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; -}; - -&i2c9 { - clock-frequency = <100000>; - status = "okay"; - - synaptics-rmi4-i2c@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_default>; - - vio-supply = <&ts_1p8_supply>; - - syna,reset-delay-ms = <200>; - syna,startup-delay-ms = <200>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x01>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - touchscreen-x-mm = <62>; - touchscreen-y-mm = <127>; - syna,sensor-type = <1>; - }; - }; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - vdda-supply = <&vreg_l1a_1p225>; - status = "okay"; - - panel@0 { - compatible = "samsung,s6e3fa7-ams559nk06"; - reg = <0>; - - reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_default>; - - power-supply = <&vreg_l6b_3p3>; - - port { - panel_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - }; -}; - -&mdss_dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&mdss_dsi0_phy { - vdds-supply = <&vreg_l1b_0p925>; - status = "okay"; -}; - -&mdss_mdp { - status = "okay"; -}; - -&pm660_charger { - monitored-battery = <&battery>; - status = "okay"; -}; - -&pm660_gpios { - cam_vio_pin: cam-vio-state { - pins = "gpio13"; - function = "normal"; - power-source = <0>; - }; -}; - -&pm660_rradc { - status = "okay"; -}; - -&pm660l_flash { - status = "okay"; - - led-0 { - function = LED_FUNCTION_FLASH; - color = ; - led-sources = <1>, <2>; - led-max-microamp = <500000>; - flash-max-microamp = <1500000>; - flash-max-timeout-us = <1280000>; - }; -}; - -&pm660l_gpios { - cam_front_ldo_pin: cam-front-state { - pins = "gpio4"; - function = "normal"; - power-source = <0>; - }; - - vol_up_pin: vol-up-state { - pins = "gpio7"; - function = "normal"; - qcom,drive-strength = ; - input-enable; - bias-pull-up; - }; -}; - -&pon_pwrkey { - status = "okay"; -}; - -&pon_resin { - linux,code = ; - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_1 { - supports-cqe; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - mmc-ddr-1_8v; - - qcom,ddr-config = <0xc3040873>; - - vmmc-supply = <&vreg_l4b_2p95>; - vqmmc-supply = <&vreg_l8a_1p8>; - - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - panel_default: panel-default-state { - te-pins { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - reset-pins { - pins = "gpio75"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - mode-pins { - pins = "gpio76"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - touchscreen_default: ts-default-state { - ts-reset-pins { - pins = "gpio99"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-high; - }; - - ts-irq-pins { - pins = "gpio125"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - ts-switch-pins { - pins = "gpio135"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - }; -}; - -&usb_1_hsphy { - vdd-supply = <&vreg_l1b_0p925>; - vdda-pll-supply = <&vreg_l10a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; - - status = "okay"; -}; - -&usb_1 { - qcom,select-utmi-as-pipe-clk; - status = "okay"; -}; - -&usb_1_dwc3 { - /* Only peripheral works for now */ - dr_mode = "peripheral"; - - /* Do not assume that sdm670.dtsi will never support USB 3.0 */ - phys = <&usb_1_hsphy>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; +&rmi4_f12 { + touchscreen-x-mm = <62>; + touchscreen-y-mm = <127>; }; From f3919fa784a3e6dd557dfe2c41072f55742e013f Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Wed, 13 May 2026 13:25:49 -0400 Subject: [PATCH 131/131] arm64: dts: qcom: add support for pixel 3a xl with the tianma panel The Pixel 3a XL has variants with either a Samsung Display Controller (SDC) panel or a Tianma panel. Add the device tree for the variant with the Tianma panel. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Assisted-by: "Claude Code Review Bot":claude-opus-4-6 Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260513172549.1345-3-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sdm670-google-bonito-tianma.dts | 32 +++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-bonito-tianma.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 795cee4757ab..6f33c4e2f09c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -308,6 +308,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-bonito-tianma.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-bonito-tianma.dts b/arch/arm64/boot/dts/qcom/sdm670-google-bonito-tianma.dts new file mode 100644 index 000000000000..42ddaf53d150 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm670-google-bonito-tianma.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device tree for Google Pixel 3a XL with the Tianma panel. + * + * Copyright (c) Richard Acayan. All rights reserved. + */ + +/dts-v1/; + +#include "sdm670-google-common.dtsi" + +/ { + model = "Google Pixel 3a XL (with Tianma panel)"; + compatible = "google,bonito-tianma", "google,bonito", "qcom,sdm670"; +}; + +&battery { + charge-full-design-microamp-hours = <3700000>; +}; + +&framebuffer { + height = <2160>; +}; + +&panel { + compatible = "novatek,nt37700f"; +}; + +&rmi4_f12 { + touchscreen-x-mm = <69>; + touchscreen-y-mm = <137>; +};