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drm/i915/dp: Move link train params to a substruct in intel_dp

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For clarity move the link training parameters updated during link
training based on the pass/fail LT result under a substruct in intel_dp.
This prepares for later patches in this patchset adding similar params
here. Rename intel_dp_reset_max_link_params() to
intel_dp_reset_link_params() to better reflect what state gets reset.

v2: Add the parameters to a more generic link substruct. (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-3-imre.deak@intel.com
This commit is contained in:
Imre Deak 2024-06-10 19:49:14 +03:00
parent 1bcbe192e0
commit 6a03100200
2 changed files with 23 additions and 20 deletions
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13
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1739,7 +1739,6 @@ struct intel_dp {
u8 lane_count;
u8 sink_count;
bool link_trained;
bool reset_link_params;
bool use_max_params;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
@ -1761,10 +1760,14 @@ struct intel_dp {
/* intersection of source and sink rates */
int num_common_rates;
int common_rates[DP_MAX_SUPPORTED_RATES];
/* Max lane count for the current link */
int max_link_lane_count;
/* Max rate for the current link */
int max_link_rate;
struct {
/* TODO: move the rest of link specific fields to here */
/* Max lane count for the current link */
int max_lane_count;
/* Max rate for the current link */
int max_rate;
} link;
bool reset_link_params;
int mso_link_count;
int mso_pixel_overlap;
/* sink or branch descriptor */

30
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -373,13 +373,13 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
int intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
switch (intel_dp->max_link_lane_count) {
switch (intel_dp->link.max_lane_count) {
case 1:
case 2:
case 4:
return intel_dp->max_link_lane_count;
return intel_dp->link.max_lane_count;
default:
MISSING_CASE(intel_dp->max_link_lane_count);
MISSING_CASE(intel_dp->link.max_lane_count);
return 1;
}
}
@ -645,7 +645,7 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
* boot-up.
*/
if (link_rate == 0 ||
link_rate > intel_dp->max_link_rate)
link_rate > intel_dp->link.max_rate)
return false;
if (lane_count == 0 ||
@ -706,8 +706,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
"Retrying Link training for eDP with same parameters\n");
return 0;
}
intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
intel_dp->max_link_lane_count = lane_count;
intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1);
intel_dp->link.max_lane_count = lane_count;
} else if (lane_count > 1) {
if (intel_dp_is_edp(intel_dp) &&
!intel_dp_can_link_train_fallback_for_edp(intel_dp,
@ -717,8 +717,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
"Retrying Link training for eDP with same parameters\n");
return 0;
}
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
intel_dp->max_link_lane_count = lane_count >> 1;
intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
intel_dp->link.max_lane_count = lane_count >> 1;
} else {
drm_err(&i915->drm, "Link Training Unsuccessful\n");
return -1;
@ -1383,7 +1383,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
int len;
len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);
return intel_dp_common_rate(intel_dp, len - 1);
}
@ -3027,10 +3027,10 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
intel_dp->lane_count = lane_count;
}
static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
static void intel_dp_reset_link_params(struct intel_dp *intel_dp)
{
intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
}
/* Enable backlight PWM and backlight PP control. */
@ -3365,7 +3365,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
if (crtc_state)
intel_dp_reset_max_link_params(intel_dp);
intel_dp_reset_link_params(intel_dp);
}
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
@ -5907,7 +5907,7 @@ intel_dp_detect(struct drm_connector *connector,
* supports link training fallback params.
*/
if (intel_dp->reset_link_params || intel_dp->is_mst) {
intel_dp_reset_max_link_params(intel_dp);
intel_dp_reset_link_params(intel_dp);
intel_dp->reset_link_params = false;
}
@ -6761,7 +6761,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp_set_source_rates(intel_dp);
intel_dp_set_common_rates(intel_dp);
intel_dp_reset_max_link_params(intel_dp);
intel_dp_reset_link_params(intel_dp);
/* init MST on ports that can support it */
intel_dp_mst_encoder_init(dig_port,