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Memory controller drivers for v6.4, part two

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1. Tegra210 EMC: correct reading of MR18 register.
 2. MediaTek SMI: add support for MT8365.
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Merge tag 'memory-controller-drv-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v6.4, part two

1. Tegra210 EMC: correct reading of MR18 register.
2. MediaTek SMI: add support for MT8365.

* tag 'memory-controller-drv-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: mtk-smi: mt8365: Add SMI Support
  dt-bindings: memory-controllers: mediatek,smi-larb: add mt8365
  dt-bindings: memory-controllers: mediatek,smi-common: add mt8365
  memory: tegra: read values from correct device

Link: https://lore.kernel.org/r/20230416143248.308942-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-04-17 17:38:04 +02:00
commit 69bda55a09
4 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
View File

@ -43,6 +43,7 @@ properties:
- mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp
- mediatek,mt8195-smi-sub-common
- mediatek,mt8365-smi-common
- description: for mt7623
items:
@ -133,6 +134,7 @@ allOf:
- mediatek,mt8192-smi-common
- mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp
- mediatek,mt8365-smi-common
then:
properties:

4
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
View File

@ -34,6 +34,10 @@ properties:
- const: mediatek,mt7623-smi-larb
- const: mediatek,mt2701-smi-larb
- items:
- const: mediatek,mt8365-smi-larb
- const: mediatek,mt8186-smi-larb
reg:
maxItems: 1

6
drivers/memory/mtk-smi.c
View File

@ -713,6 +713,11 @@ static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
.has_gals = true,
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = {
.type = MTK_SMI_GEN2,
.bus_sel = F_MMU1_LARB(2) | F_MMU1_LARB(4),
};
static const struct of_device_id mtk_smi_common_of_ids[] = {
{.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
{.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
@ -728,6 +733,7 @@ static const struct of_device_id mtk_smi_common_of_ids[] = {
{.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
{.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
{.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
{.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365},
{}
};

2
drivers/memory/tegra/tegra210-emc-cc-r21021.c
View File

@ -277,7 +277,7 @@ static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type)
/*
* Dev1 LSB.
*/
value = tegra210_emc_mrr_read(emc, 2, 18);
value = tegra210_emc_mrr_read(emc, 1, 18);
for (i = 0; i < emc->num_channels; i++) {
temp[i][0] |= (value & 0x00ff) >> 0;