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drm/nouveau/mc: use split type+inst in device reset APIs

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2021-02-06 10:44:15 +10:00
parent c653ab8383
commit 6997ea1312
9 changed files with 28 additions and 31 deletions
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8
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
View File

@ -8,10 +8,10 @@ struct nvkm_mc {
struct nvkm_subdev subdev;
};
void nvkm_mc_enable(struct nvkm_device *, enum nvkm_devidx);
void nvkm_mc_disable(struct nvkm_device *, enum nvkm_devidx);
bool nvkm_mc_enabled(struct nvkm_device *, enum nvkm_devidx);
void nvkm_mc_reset(struct nvkm_device *, enum nvkm_devidx);
void nvkm_mc_enable(struct nvkm_device *, enum nvkm_subdev_type, int);
void nvkm_mc_disable(struct nvkm_device *, enum nvkm_subdev_type, int);
bool nvkm_mc_enabled(struct nvkm_device *, enum nvkm_subdev_type, int);
void nvkm_mc_reset(struct nvkm_device *, enum nvkm_subdev_type, int);
void nvkm_mc_intr(struct nvkm_device *, bool *handled);
void nvkm_mc_intr_unarm(struct nvkm_device *);
void nvkm_mc_intr_rearm(struct nvkm_device *);

2
drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h
View File

@ -23,7 +23,7 @@ struct nvkm_top_device {
};
u32 nvkm_top_addr(struct nvkm_device *, enum nvkm_devidx);
u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_devidx);
u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_subdev_type, int);
u32 nvkm_top_intr(struct nvkm_device *, u32 intr, u64 *subdevs);
u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_devidx);
int nvkm_top_fault_id(struct nvkm_device *, enum nvkm_devidx);

2
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -111,7 +111,7 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
}
}
nvkm_mc_reset(device, subdev->index);
nvkm_mc_reset(device, subdev->type, subdev->inst);
time = ktime_to_us(ktime_get()) - time;
nvkm_trace(subdev, "%s completed in %lldus\n", action, time);

2
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
View File

@ -108,7 +108,7 @@ nvkm_falcon_fini(struct nvkm_engine *engine, bool suspend)
}
}
if (nvkm_mc_enabled(device, engine->subdev.index)) {
if (nvkm_mc_enabled(device, engine->subdev.type, engine->subdev.inst)) {
nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000);
nvkm_wr32(device, base + 0x014, 0xffffffff);
}

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
View File

@ -313,7 +313,7 @@ nvkm_fifo_oneinit(struct nvkm_engine *engine)
static void
nvkm_fifo_preinit(struct nvkm_engine *engine)
{
nvkm_mc_reset(engine->subdev.device, NVKM_ENGINE_FIFO);
nvkm_mc_reset(engine->subdev.device, NVKM_ENGINE_FIFO, 0);
}
static int

10
drivers/gpu/drm/nouveau/nvkm/falcon/base.c
View File

@ -88,13 +88,12 @@ int
nvkm_falcon_enable(struct nvkm_falcon *falcon)
{
struct nvkm_device *device = falcon->owner->device;
enum nvkm_devidx id = falcon->owner->index;
int ret;
nvkm_mc_enable(device, id);
nvkm_mc_enable(device, falcon->owner->type, falcon->owner->inst);
ret = falcon->func->enable(falcon);
if (ret) {
nvkm_mc_disable(device, id);
nvkm_mc_disable(device, falcon->owner->type, falcon->owner->inst);
return ret;
}
@ -105,15 +104,14 @@ void
nvkm_falcon_disable(struct nvkm_falcon *falcon)
{
struct nvkm_device *device = falcon->owner->device;
enum nvkm_devidx id = falcon->owner->index;
/* already disabled, return or wait_idle will timeout */
if (!nvkm_mc_enabled(device, id))
if (!nvkm_mc_enabled(device, falcon->owner->type, falcon->owner->inst))
return;
falcon->func->disable(falcon);
nvkm_mc_disable(device, id);
nvkm_mc_disable(device, falcon->owner->type, falcon->owner->inst);
}
int

23
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
View File

@ -111,17 +111,16 @@ nvkm_mc_intr(struct nvkm_device *device, bool *handled)
}
static u32
nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto,
enum nvkm_devidx devidx)
nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto, enum nvkm_subdev_type type, int inst)
{
struct nvkm_mc *mc = device->mc;
const struct nvkm_mc_map *map;
u64 pmc_enable = 0;
if (likely(mc)) {
if (!(pmc_enable = nvkm_top_reset(device, devidx))) {
if (!(pmc_enable = nvkm_top_reset(device, type, inst))) {
for (map = mc->func->reset; map && map->stat; map++) {
if (!isauto || !map->noauto) {
if (map->type + map->inst == devidx) {
if (map->type == type && map->inst == inst) {
pmc_enable = map->stat;
break;
}
@ -133,9 +132,9 @@ nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto,
}
void
nvkm_mc_reset(struct nvkm_device *device, enum nvkm_devidx devidx)
nvkm_mc_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
{
u64 pmc_enable = nvkm_mc_reset_mask(device, true, devidx);
u64 pmc_enable = nvkm_mc_reset_mask(device, true, type, inst);
if (pmc_enable) {
nvkm_mask(device, 0x000200, pmc_enable, 0x00000000);
nvkm_mask(device, 0x000200, pmc_enable, pmc_enable);
@ -144,17 +143,17 @@ nvkm_mc_reset(struct nvkm_device *device, enum nvkm_devidx devidx)
}
void
nvkm_mc_disable(struct nvkm_device *device, enum nvkm_devidx devidx)
nvkm_mc_disable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
{
u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx);
u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
if (pmc_enable)
nvkm_mask(device, 0x000200, pmc_enable, 0x00000000);
}
void
nvkm_mc_enable(struct nvkm_device *device, enum nvkm_devidx devidx)
nvkm_mc_enable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
{
u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx);
u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
if (pmc_enable) {
nvkm_mask(device, 0x000200, pmc_enable, pmc_enable);
nvkm_rd32(device, 0x000200);
@ -162,9 +161,9 @@ nvkm_mc_enable(struct nvkm_device *device, enum nvkm_devidx devidx)
}
bool
nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_devidx devidx)
nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
{
u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx);
u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
return (pmc_enable != 0) &&
((nvkm_rd32(device, 0x000200) & pmc_enable) == pmc_enable);

6
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c
View File

@ -30,14 +30,14 @@ void
gf100_pmu_reset(struct nvkm_pmu *pmu)
{
struct nvkm_device *device = pmu->subdev.device;
nvkm_mc_disable(device, NVKM_SUBDEV_PMU);
nvkm_mc_enable(device, NVKM_SUBDEV_PMU);
nvkm_mc_disable(device, NVKM_SUBDEV_PMU, 0);
nvkm_mc_enable(device, NVKM_SUBDEV_PMU, 0);
}
bool
gf100_pmu_enabled(struct nvkm_pmu *pmu)
{
return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU);
return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU, 0);
}
static const struct nvkm_pmu_func

4
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
View File

@ -59,14 +59,14 @@ nvkm_top_addr(struct nvkm_device *device, enum nvkm_devidx index)
}
u32
nvkm_top_reset(struct nvkm_device *device, enum nvkm_devidx index)
nvkm_top_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
{
struct nvkm_top *top = device->top;
struct nvkm_top_device *info;
if (top) {
list_for_each_entry(info, &top->device, head) {
if (info->index == index && info->reset >= 0)
if (info->type == type && info->inst == inst && info->reset >= 0)
return BIT(info->reset);
}
}