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perf vendor events intel: Update meteorlake events from 1.18 to 1.20

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The updated events were published in:
2eebd8e261
81c4ce2c16

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Ian Rogers 2026-02-26 09:59:33 -08:00 committed by Namhyung Kim
parent 6ac2011cd0
commit 698fd9606e
4 changed files with 116 additions and 17 deletions
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2
tools/perf/pmu-events/arch/x86/mapfile.csv
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@ -23,7 +23,7 @@ GenuineIntel-6-3E,v24,ivytown,core
GenuineIntel-6-2D,v24,jaketown,core
GenuineIntel-6-(57|85),v16,knightslanding,core
GenuineIntel-6-BD,v1.21,lunarlake,core
GenuineIntel-6-(AA|AC|B5),v1.18,meteorlake,core
GenuineIntel-6-(AA|AC|B5),v1.20,meteorlake,core
GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core
GenuineIntel-6-CC,v1.02,pantherlake,core

1 Family-model Version Filename EventType
23 GenuineIntel-6-2D v24 jaketown core
24 GenuineIntel-6-(57|85) v16 knightslanding core
25 GenuineIntel-6-BD v1.21 lunarlake core
26 GenuineIntel-6-(AA|AC|B5) v1.18 v1.20 meteorlake core
27 GenuineIntel-6-1[AEF] v4 nehalemep core
28 GenuineIntel-6-2E v4 nehalemex core
29 GenuineIntel-6-CC v1.02 pantherlake core

67
tools/perf/pmu-events/arch/x86/meteorlake/cache.json
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@ -513,6 +513,15 @@
"UMask": "0x6",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x35",
"EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT_NOSNOOP",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
"Counter": "0,1,2,3,4,5,6,7",
@ -522,6 +531,15 @@
"UMask": "0x78",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x35",
"EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS_LOCALMEM",
"SampleAfterValue": "1000003",
"UMask": "0x50",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
"Counter": "0,1,2,3,4,5,6,7",
@ -559,6 +577,24 @@
"UMask": "0x6",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but NO_FWD. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
"Counter": "0,1,2,3,4,5,6,7",
@ -568,6 +604,15 @@
"UMask": "0x78",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM",
"SampleAfterValue": "1000003",
"UMask": "0x50",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition",
"Counter": "0,1,2,3,4,5,6,7",
@ -969,7 +1014,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -981,7 +1026,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -993,7 +1038,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -1005,7 +1050,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -1017,7 +1062,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -1029,7 +1074,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -1041,7 +1086,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -1053,7 +1098,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -1065,7 +1110,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -1077,7 +1122,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@ -1159,7 +1204,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
"BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",

18
tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
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@ -430,6 +430,24 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "ICACHE_TAG.STALLS_INUSE",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_TAG.STALLS_INUSE",
"SampleAfterValue": "200003",
"UMask": "0x10",
"Unit": "cpu_core"
},
{
"BriefDescription": "ICACHE_TAG.STALLS_ISB",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_TAG.STALLS_ISB",
"SampleAfterValue": "200003",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",

46
tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
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@ -517,7 +517,7 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
@ -583,7 +583,7 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
@ -620,7 +620,7 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
@ -804,10 +804,10 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "Fixed Counter: Counts the number of instructions retired",
"BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32",
"PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
"SampleAfterValue": "2000003",
"UMask": "0x1",
"Unit": "cpu_atom"
@ -1207,6 +1207,42 @@
"UMask": "0x20",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe0",
"EventName": "MISC_RETIRED1.CL_INST",
"SampleAfterValue": "1000003",
"UMask": "0xff",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of LFENCE instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe0",
"EventName": "MISC_RETIRED1.LFENCE",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of accesses to KeyLocker cache.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe1",
"EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
"SampleAfterValue": "1000003",
"UMask": "0x10",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of misses to KeyLocker cache.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe1",
"EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
"SampleAfterValue": "1000003",
"UMask": "0x11",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"Counter": "0,1,2,3,4,5,6,7",