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ice: fall back to SBQ when LL PHY timer interface times out

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The low-latency (LL) PHY timer interface relies on a tight, atomic poll
of the PF_SB_ATQBAL register with a 2ms timeout. After an NVM update /
EMPR, FW may need significantly longer than 2ms to start responding to
ATQBAL commands. The first PHY adjust or incval write issued by
ice_ptp_rebuild_owner() fails with -ETIMEDOUT.

Fix this by falling back to the existing SBQ-based PHY register write
path when LL times out. This makes sure PTP is initialized when FW takes
longer than expected to come back online.

Steps to reproduce:
./nvmupdate64e -if devlink -f
Update E810 card with nvmupdate64e, and observe dmesg errors:
  Failed to write PHC increment value, status -110
  PTP reset failed, error: -110 (-ETIMEDOUT)

Fixes: ef9a64c072 ("ice: implement low latency PHY timer updates")
Signed-off-by: Przemyslaw Korba <przemyslaw.korba@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Przemyslaw Korba 2026-06-05 14:06:26 +02:00 committed by Tony Nguyen
parent cba9ccb47e
commit 6959fbdc94
1 changed files with 20 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View File

@ -4808,15 +4808,12 @@ static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj)
!FIELD_GET(REG_LL_PROXY_H_EXEC, val),
10, REG_LL_PROXY_H_TIMEOUT_US, false, hw,
REG_LL_PROXY_H);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n");
spin_unlock_irq(&params->atqbal_wq.lock);
return err;
}
spin_unlock_irq(&params->atqbal_wq.lock);
return 0;
if (err)
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n");
return err;
}
/**
@ -4837,8 +4834,12 @@ static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj)
u8 tmr_idx;
int err;
if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update)
return ice_ptp_prep_phy_adj_ll_e810(hw, adj);
if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) {
err = ice_ptp_prep_phy_adj_ll_e810(hw, adj);
if (err != -ETIMEDOUT)
return err;
ice_debug(hw, ICE_DBG_PTP, "LL adj timed out, falling back to SBQ\n");
}
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
@ -4901,15 +4902,12 @@ static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval)
!FIELD_GET(REG_LL_PROXY_H_EXEC, val),
10, REG_LL_PROXY_H_TIMEOUT_US, false, hw,
REG_LL_PROXY_H);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n");
spin_unlock_irq(&params->atqbal_wq.lock);
return err;
}
spin_unlock_irq(&params->atqbal_wq.lock);
return 0;
if (err)
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n");
return err;
}
/**
@ -4927,8 +4925,12 @@ static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
u8 tmr_idx;
int err;
if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update)
return ice_ptp_prep_phy_incval_ll_e810(hw, incval);
if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) {
err = ice_ptp_prep_phy_incval_ll_e810(hw, incval);
if (err != -ETIMEDOUT)
return err;
ice_debug(hw, ICE_DBG_PTP, "LL incval timed out, falling back to SBQ\n");
}
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
low = lower_32_bits(incval);