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mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver
Add SDHCI controller driver for Black Sesame Technologies C1200 SoC. This driver supports the DWCMSHC SDHCI controller with BST-specific enhancements including: - Custom clock management and tuning - Power management support - BST-specific register configurations - Support for eMMC and SD card interfaces - Hardware limitation workaround for 32-bit DMA addressing The driver addresses specific hardware constraints where: - System memory uses 64-bit bus, eMMC controller uses 32-bit bus - eMMC controller cannot access memory through SMMU due to hardware bug - All system DRAM is configured outside 4GB boundary (ZONE_DMA32) - Uses SRAM-based bounce buffer within 32-bit address space Signed-off-by: Ge Gordon <gordon.ge@bst.ai> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Albert Yang
Ulf Hansson
parent
ef7eb1a709
commit
695824f456
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@ -429,6 +429,20 @@ config MMC_SDHCI_BCM_KONA
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If you have a controller with this interface, say Y or M here.
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config MMC_SDHCI_BST
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tristate "SDHCI support for Black Sesame Technologies BST C1200 controller"
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depends on ARCH_BST || COMPILE_TEST
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depends on MMC_SDHCI_PLTFM
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depends on OF
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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for Black Sesame Technologies BST C1200 SoC. The controller is
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based on Synopsys DesignWare Cores Mobile Storage Controller but
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requires platform-specific workarounds for hardware limitations.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_F_SDH30
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tristate "SDHCI support for Fujitsu Semiconductor F_SDH30"
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depends on MMC_SDHCI_PLTFM
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@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
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obj-$(CONFIG_MMC_SDHCI) += sdhci.o
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obj-$(CONFIG_MMC_SDHCI_UHS2) += sdhci-uhs2.o
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obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
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obj-$(CONFIG_MMC_SDHCI_BST) += sdhci-of-bst.o
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sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \
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sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
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obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
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521
drivers/mmc/host/sdhci-of-bst.c
Normal file
521
drivers/mmc/host/sdhci-of-bst.c
Normal file
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@ -0,0 +1,521 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* SDHCI driver for Black Sesame Technologies C1200 controller
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*
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* Copyright (c) 2025 Black Sesame Technologies
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*/
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/platform_device.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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/* SDHCI register extensions */
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#define SDHCI_CLOCK_PLL_EN 0x0008
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#define SDHCI_VENDOR_PTR_R 0xE8
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/* BST-specific tuning parameters */
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#define BST_TUNING_COUNT 0x20
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/* Synopsys vendor specific registers */
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#define SDHC_EMMC_CTRL_R_OFFSET 0x2C
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#define MBIU_CTRL 0x510
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/* MBIU burst control bits */
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#define BURST_INCR16_EN BIT(3)
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#define BURST_INCR8_EN BIT(2)
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#define BURST_INCR4_EN BIT(1)
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#define BURST_EN (BURST_INCR16_EN | BURST_INCR8_EN | BURST_INCR4_EN)
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#define MBIU_BURST_MASK GENMASK(3, 0)
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/* CRM (Clock/Reset/Management) register offsets */
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#define SDEMMC_CRM_BCLK_DIV_CTRL 0x08
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#define SDEMMC_CRM_TIMER_DIV_CTRL 0x0C
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#define SDEMMC_CRM_RX_CLK_CTRL 0x14
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#define SDEMMC_CRM_VOL_CTRL 0x1C
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#define REG_WR_PROTECT 0x88
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#define DELAY_CHAIN_SEL 0x94
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/* CRM register values and bit definitions */
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#define REG_WR_PROTECT_KEY 0x1234abcd
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#define BST_VOL_STABLE_ON BIT(7)
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#define BST_TIMER_DIV_MASK GENMASK(7, 0)
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#define BST_TIMER_DIV_VAL 0x20
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#define BST_TIMER_LOAD_BIT BIT(8)
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#define BST_BCLK_EN_BIT BIT(10)
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#define BST_RX_UPDATE_BIT BIT(11)
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#define BST_EMMC_CTRL_RST_N BIT(2) /* eMMC card reset control */
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/* Clock frequency limits */
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#define BST_DEFAULT_MAX_FREQ 200000000UL /* 200 MHz */
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#define BST_DEFAULT_MIN_FREQ 400000UL /* 400 kHz */
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/* Clock control bit definitions */
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#define BST_CLOCK_DIV_MASK GENMASK(7, 0)
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#define BST_CLOCK_DIV_SHIFT 8
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#define BST_BCLK_DIV_MASK GENMASK(9, 0)
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/* Clock frequency thresholds */
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#define BST_CLOCK_THRESHOLD_LOW 1500
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/* Clock stability polling parameters */
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#define BST_CLK_STABLE_POLL_US 1000 /* Poll interval in microseconds */
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#define BST_CLK_STABLE_TIMEOUT_US 20000 /* Timeout for internal clock stabilization (us) */
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struct sdhci_bst_priv {
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void __iomem *crm_reg_base;
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};
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union sdhci_bst_rx_ctrl {
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struct {
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u32 rx_revert:1,
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rx_clk_sel_sec:1,
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rx_clk_div:4,
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rx_clk_phase_inner:2,
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rx_clk_sel_first:1,
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rx_clk_phase_out:2,
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rx_clk_en:1,
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res0:20;
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};
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u32 reg;
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};
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static u32 sdhci_bst_crm_read(struct sdhci_pltfm_host *pltfm_host, u32 offset)
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{
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struct sdhci_bst_priv *priv = sdhci_pltfm_priv(pltfm_host);
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return readl(priv->crm_reg_base + offset);
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}
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static void sdhci_bst_crm_write(struct sdhci_pltfm_host *pltfm_host, u32 offset, u32 value)
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{
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struct sdhci_bst_priv *priv = sdhci_pltfm_priv(pltfm_host);
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writel(value, priv->crm_reg_base + offset);
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}
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static int sdhci_bst_wait_int_clk(struct sdhci_host *host)
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{
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u16 clk;
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if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
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BST_CLK_STABLE_POLL_US, BST_CLK_STABLE_TIMEOUT_US, false,
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host, SDHCI_CLOCK_CONTROL))
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return -EBUSY;
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return 0;
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}
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static unsigned int sdhci_bst_get_max_clock(struct sdhci_host *host)
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{
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return BST_DEFAULT_MAX_FREQ;
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}
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static unsigned int sdhci_bst_get_min_clock(struct sdhci_host *host)
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{
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return BST_DEFAULT_MIN_FREQ;
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}
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static void sdhci_bst_enable_clk(struct sdhci_host *host, unsigned int clk)
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{
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struct sdhci_pltfm_host *pltfm_host;
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unsigned int div;
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u32 val;
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union sdhci_bst_rx_ctrl rx_reg;
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pltfm_host = sdhci_priv(host);
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/* Calculate clock divider based on target frequency */
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if (clk == 0) {
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div = 0;
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} else if (clk < BST_DEFAULT_MIN_FREQ) {
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/* Below minimum: use max divider to get closest to min freq */
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div = BST_DEFAULT_MAX_FREQ / BST_DEFAULT_MIN_FREQ;
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} else if (clk <= BST_DEFAULT_MAX_FREQ) {
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/* Normal range: calculate divider directly */
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div = BST_DEFAULT_MAX_FREQ / clk;
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} else {
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/* Above maximum: no division needed */
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div = 1;
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}
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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clk &= ~SDHCI_CLOCK_PLL_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
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val &= ~BST_TIMER_LOAD_BIT;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
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val &= ~BST_TIMER_DIV_MASK;
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val |= BST_TIMER_DIV_VAL;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
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val |= BST_TIMER_LOAD_BIT;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
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val &= ~BST_RX_UPDATE_BIT;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
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rx_reg.reg = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
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rx_reg.rx_revert = 0;
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rx_reg.rx_clk_sel_sec = 1;
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rx_reg.rx_clk_div = 4;
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rx_reg.rx_clk_phase_inner = 2;
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rx_reg.rx_clk_sel_first = 0;
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rx_reg.rx_clk_phase_out = 2;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, rx_reg.reg);
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
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val |= BST_RX_UPDATE_BIT;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
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/* Disable clock first */
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
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val &= ~BST_BCLK_EN_BIT;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
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/* Setup clock divider */
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
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val &= ~BST_BCLK_DIV_MASK;
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val |= div;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
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/* Enable clock */
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
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val |= BST_BCLK_EN_BIT;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
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/* RMW the clock divider bits to avoid clobbering other fields */
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= ~(BST_CLOCK_DIV_MASK << BST_CLOCK_DIV_SHIFT);
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clk |= (div & BST_CLOCK_DIV_MASK) << BST_CLOCK_DIV_SHIFT;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk |= SDHCI_CLOCK_PLL_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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clk |= SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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}
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static void sdhci_bst_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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/* Turn off card/internal/PLL clocks when clock==0 to avoid idle power */
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u32 clk_reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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if (!clock) {
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clk_reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_PLL_EN);
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sdhci_writew(host, clk_reg, SDHCI_CLOCK_CONTROL);
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return;
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}
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sdhci_bst_enable_clk(host, clock);
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}
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/*
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* sdhci_bst_reset - Reset the SDHCI host controller with special
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* handling for eMMC card reset control.
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*/
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static void sdhci_bst_reset(struct sdhci_host *host, u8 mask)
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{
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u16 vendor_ptr, emmc_ctrl_reg;
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u32 reg;
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if (host->mmc->caps2 & MMC_CAP2_NO_SD) {
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vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
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emmc_ctrl_reg = vendor_ptr + SDHC_EMMC_CTRL_R_OFFSET;
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reg = sdhci_readw(host, emmc_ctrl_reg);
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reg &= ~BST_EMMC_CTRL_RST_N;
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sdhci_writew(host, reg, emmc_ctrl_reg);
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sdhci_reset(host, mask);
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usleep_range(10, 20);
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reg = sdhci_readw(host, emmc_ctrl_reg);
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reg |= BST_EMMC_CTRL_RST_N;
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sdhci_writew(host, reg, emmc_ctrl_reg);
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} else {
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sdhci_reset(host, mask);
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}
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}
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/* Set timeout control register to maximum value (0xE) */
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static void sdhci_bst_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
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{
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sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
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}
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/*
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* sdhci_bst_set_power - Set power mode and voltage, also configures
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* MBIU burst mode control based on power state.
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*/
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static void sdhci_bst_set_power(struct sdhci_host *host, unsigned char mode,
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unsigned short vdd)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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u32 reg;
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u32 val;
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sdhci_set_power(host, mode, vdd);
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if (mode == MMC_POWER_OFF) {
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/* Disable MBIU burst mode */
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reg = sdhci_readw(host, MBIU_CTRL);
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reg &= ~BURST_EN; /* Clear all burst enable bits */
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sdhci_writew(host, reg, MBIU_CTRL);
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/* Disable CRM BCLK */
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
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val &= ~BST_BCLK_EN_BIT;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
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/* Disable RX clock */
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
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val &= ~BST_RX_UPDATE_BIT;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
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/* Turn off voltage stable power */
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val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_VOL_CTRL);
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val &= ~BST_VOL_STABLE_ON;
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sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, val);
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} else {
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/* Configure burst mode only when powered on */
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reg = sdhci_readw(host, MBIU_CTRL);
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reg &= ~MBIU_BURST_MASK; /* Clear burst related bits */
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reg |= BURST_EN; /* Enable burst mode for better bandwidth */
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sdhci_writew(host, reg, MBIU_CTRL);
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}
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}
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/*
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* sdhci_bst_execute_tuning - Execute tuning procedure by trying different
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* delay chain values and selecting the optimal one.
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*/
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static int sdhci_bst_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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struct sdhci_pltfm_host *pltfm_host;
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int ret = 0, error;
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int first_start = -1, first_end = -1, best = 0;
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int second_start = -1, second_end = -1, has_failure = 0;
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int i;
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pltfm_host = sdhci_priv(host);
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for (i = 0; i < BST_TUNING_COUNT; i++) {
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/* Protected write */
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sdhci_bst_crm_write(pltfm_host, REG_WR_PROTECT, REG_WR_PROTECT_KEY);
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/* Write tuning value */
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sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << i) - 1);
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/* Wait for internal clock stable before tuning */
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if (sdhci_bst_wait_int_clk(host)) {
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dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n");
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return -EBUSY;
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}
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ret = mmc_send_tuning(host->mmc, opcode, &error);
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if (ret != 0) {
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has_failure = 1;
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} else {
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if (has_failure == 0) {
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if (first_start == -1)
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first_start = i;
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first_end = i;
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} else {
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if (second_start == -1)
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second_start = i;
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second_end = i;
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}
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}
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}
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/* Calculate best tuning value */
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if (first_end - first_start >= second_end - second_start)
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best = ((first_end - first_start) >> 1) + first_start;
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else
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||||
best = ((second_end - second_start) >> 1) + second_start;
|
||||
|
||||
if (best < 0)
|
||||
best = 0;
|
||||
|
||||
sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << best) - 1);
|
||||
/* Confirm internal clock stable after setting best tuning value */
|
||||
if (sdhci_bst_wait_int_clk(host)) {
|
||||
dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Enable voltage stable power for voltage switch */
|
||||
static void sdhci_bst_voltage_switch(struct sdhci_host *host)
|
||||
{
|
||||
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
||||
|
||||
/* Enable voltage stable power */
|
||||
sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, BST_VOL_STABLE_ON);
|
||||
}
|
||||
|
||||
static const struct sdhci_ops sdhci_bst_ops = {
|
||||
.set_clock = sdhci_bst_set_clock,
|
||||
.set_bus_width = sdhci_set_bus_width,
|
||||
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
||||
.get_min_clock = sdhci_bst_get_min_clock,
|
||||
.get_max_clock = sdhci_bst_get_max_clock,
|
||||
.reset = sdhci_bst_reset,
|
||||
.set_power = sdhci_bst_set_power,
|
||||
.set_timeout = sdhci_bst_set_timeout,
|
||||
.platform_execute_tuning = sdhci_bst_execute_tuning,
|
||||
.voltage_switch = sdhci_bst_voltage_switch,
|
||||
};
|
||||
|
||||
static const struct sdhci_pltfm_data sdhci_bst_pdata = {
|
||||
.ops = &sdhci_bst_ops,
|
||||
.quirks = SDHCI_QUIRK_BROKEN_ADMA |
|
||||
SDHCI_QUIRK_DELAY_AFTER_POWER |
|
||||
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
|
||||
SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
|
||||
.quirks2 = SDHCI_QUIRK2_BROKEN_DDR50 |
|
||||
SDHCI_QUIRK2_TUNING_WORK_AROUND |
|
||||
SDHCI_QUIRK2_ACMD23_BROKEN,
|
||||
};
|
||||
|
||||
static void sdhci_bst_free_bounce_buffer(struct sdhci_host *host)
|
||||
{
|
||||
if (host->bounce_buffer) {
|
||||
dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size,
|
||||
host->bounce_buffer, host->bounce_addr);
|
||||
host->bounce_buffer = NULL;
|
||||
}
|
||||
of_reserved_mem_device_release(mmc_dev(host->mmc));
|
||||
}
|
||||
|
||||
static int sdhci_bst_alloc_bounce_buffer(struct sdhci_host *host)
|
||||
{
|
||||
struct mmc_host *mmc = host->mmc;
|
||||
unsigned int bounce_size;
|
||||
int ret;
|
||||
|
||||
/* Fixed SRAM bounce size to 32KB: verified config under 32-bit DMA addressing limit */
|
||||
bounce_size = SZ_32K;
|
||||
|
||||
ret = of_reserved_mem_device_init_by_idx(mmc_dev(mmc), mmc_dev(mmc)->of_node, 0);
|
||||
if (ret) {
|
||||
dev_err(mmc_dev(mmc), "Failed to initialize reserved memory\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
host->bounce_buffer = dma_alloc_coherent(mmc_dev(mmc), bounce_size,
|
||||
&host->bounce_addr, GFP_KERNEL);
|
||||
if (!host->bounce_buffer)
|
||||
return -ENOMEM;
|
||||
|
||||
host->bounce_buffer_size = bounce_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sdhci_bst_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sdhci_pltfm_host *pltfm_host;
|
||||
struct sdhci_host *host;
|
||||
struct sdhci_bst_priv *priv;
|
||||
int err;
|
||||
|
||||
host = sdhci_pltfm_init(pdev, &sdhci_bst_pdata, sizeof(struct sdhci_bst_priv));
|
||||
if (IS_ERR(host))
|
||||
return PTR_ERR(host);
|
||||
|
||||
pltfm_host = sdhci_priv(host);
|
||||
priv = sdhci_pltfm_priv(pltfm_host); /* Get platform private data */
|
||||
|
||||
err = mmc_of_parse(host->mmc);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
sdhci_get_of_property(pdev);
|
||||
|
||||
/* Get CRM registers from the second reg entry */
|
||||
priv->crm_reg_base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(priv->crm_reg_base)) {
|
||||
err = PTR_ERR(priv->crm_reg_base);
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Silicon constraints for BST C1200:
|
||||
* - System RAM base is 0x800000000 (above 32-bit addressable range)
|
||||
* - The eMMC controller DMA engine is limited to 32-bit addressing
|
||||
* - SMMU cannot be used on this path due to hardware design flaws
|
||||
* - These are fixed in silicon and cannot be changed in software
|
||||
*
|
||||
* Bus/controller mapping:
|
||||
* - No registers are available to reprogram the address mapping
|
||||
* - The 32-bit DMA limit is a hard constraint of the controller IP
|
||||
*
|
||||
* Given these constraints, an SRAM-based bounce buffer in the 32-bit
|
||||
* address space is required to enable eMMC DMA on this platform.
|
||||
*/
|
||||
err = sdhci_bst_alloc_bounce_buffer(host);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to allocate bounce buffer: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = sdhci_add_host(host);
|
||||
if (err)
|
||||
goto err_free_bounce_buffer;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_bounce_buffer:
|
||||
sdhci_bst_free_bounce_buffer(host);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void sdhci_bst_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sdhci_host *host = platform_get_drvdata(pdev);
|
||||
|
||||
sdhci_bst_free_bounce_buffer(host);
|
||||
sdhci_pltfm_remove(pdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id sdhci_bst_ids[] = {
|
||||
{ .compatible = "bst,c1200-sdhci" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sdhci_bst_ids);
|
||||
|
||||
static struct platform_driver sdhci_bst_driver = {
|
||||
.driver = {
|
||||
.name = "sdhci-bst",
|
||||
.of_match_table = sdhci_bst_ids,
|
||||
},
|
||||
.probe = sdhci_bst_probe,
|
||||
.remove = sdhci_bst_remove,
|
||||
};
|
||||
module_platform_driver(sdhci_bst_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Black Sesame Technologies SDHCI driver (BST)");
|
||||
MODULE_AUTHOR("Black Sesame Technologies Co., Ltd.");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user