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drm/amd/display: FEC check in timing validation

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[ Upstream commit 7d56a154e2 ]

[Why]
disable/enable leads FEC mismatch between hw/sw FEC state.

[How]
check FEC status to fastboot on/off.

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Chiawen Huang 2022-03-10 00:07:59 +08:00 committed by Greg Kroah-Hartman
parent 756c61c168
commit 6906e05cf3
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/amd/display/dc/core/dc.c
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@ -1173,6 +1173,10 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
return false; return false;
/* Check for FEC status*/
if (link->link_enc->funcs->fec_is_active(link->link_enc))
return false;
enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
if (enc_inst == ENGINE_ID_UNKNOWN) if (enc_inst == ENGINE_ID_UNKNOWN)