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MHI Host
-------- - Add support for Qualcomm SDX35 and Telit FE912C04 modems reusing the existing channel and event configurations. - Enable IP_SW and IP_ETH MHI channels for Qualcomm 5G DU X100 Accelerator device (QDU100). These channels are used to carry O-RAN specific M-Plane, S-Plane and Netconf packets. The drivers making use of these channels is being reviewed. - Add NMEA channels to Telit FN920C04 and FN990A modems for GPS/GNSS support - Switch to mhi_async_power_up() API in pci_generic driver to avoid boot delays as some Qcom modems take a while start. This API ensures that the pci_generic driver powers up the modem asynchronously and doesn't block the system boot. - Add pm_runtime_forbid() in remove callback to balance the pm_runtime_allow() call made during the Mission Mode transition. - Used kzalloc_flex() to simplify kzalloc() + kzalloc() calls MHI Endpoint ------------ - Test for non-zero return value 'if (ret)' in the endpoint stack where applicable to maintain code uniformity. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEZ6VDKoFIy9ikWCeXVZ8R5v6RzvUFAmnPkoUACgkQVZ8R5v6R zvVi3wf/aKbEkpA3Gn1mRIl662M40rPhwacxY3lxUvJPlegHs1fBr1UB4jbV7Me8 a5JeHwBHDt/OaMPmWt/hSV8vaOgc1Nk7lkXMpu7TJf597frcNShngpV6tnXlPiPk 4psYzCeUYdhv3TIjhgZPoWqG5+1MaEkgXEb9M5O+EnE+lSgh8DNxJvwlrBTFMCkv sFRREx0hdjqGT6UGbWJo5CmHyaCQ3gnbJgay5/TUWpUl1YIiLEwnxHR90AkkuuqC 8OJYjBfPgow0bmdtc5wounffNYc5XTnx74zTNDAUOoGghBxijuMTnccIkMO6XX6X pCjd7c52I+uB5YxTKZQEzbKNPieRPw== =GQMc -----END PGP SIGNATURE----- Merge tag 'mhi-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mani/mhi into char-misc-next Manivannan writes: MHI Host -------- - Add support for Qualcomm SDX35 and Telit FE912C04 modems reusing the existing channel and event configurations. - Enable IP_SW and IP_ETH MHI channels for Qualcomm 5G DU X100 Accelerator device (QDU100). These channels are used to carry O-RAN specific M-Plane, S-Plane and Netconf packets. The drivers making use of these channels is being reviewed. - Add NMEA channels to Telit FN920C04 and FN990A modems for GPS/GNSS support - Switch to mhi_async_power_up() API in pci_generic driver to avoid boot delays as some Qcom modems take a while start. This API ensures that the pci_generic driver powers up the modem asynchronously and doesn't block the system boot. - Add pm_runtime_forbid() in remove callback to balance the pm_runtime_allow() call made during the Mission Mode transition. - Used kzalloc_flex() to simplify kzalloc() + kzalloc() calls MHI Endpoint ------------ - Test for non-zero return value 'if (ret)' in the endpoint stack where applicable to maintain code uniformity. * tag 'mhi-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mani/mhi: bus: mhi: host: pci_generic: Add Telit FE912C04 modem support bus: mhi: ep: Test for non-zero return value where applicable bus: mhi: host: Use kzalloc_flex bus: mhi: host: pci_generic: Add pm_runtime_forbid() in remove callback bus: mhi: host: pci_generic: Switch to async power up to avoid boot delays bus: mhi: host: pci_generic: Add NMEA channels to FN920C04 and FN990A bus: mhi: host: pci_generic: Enable IP_SW and IP_ETH channels for Qcom QDU100 device bus: mhi: host: pci_generic: Add Qualcomm SDX35 modem
This commit is contained in:
commit
68c6d134ed
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@ -367,7 +367,7 @@ static void mhi_ep_read_completion(struct mhi_ep_buf_info *buf_info)
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ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el,
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MHI_TRE_DATA_GET_LEN(el),
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MHI_EV_CC_EOB);
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if (ret < 0) {
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if (ret) {
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dev_err(&mhi_chan->mhi_dev->dev,
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"Error sending transfer compl. event\n");
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goto err_free_tre_buf;
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@ -383,7 +383,7 @@ static void mhi_ep_read_completion(struct mhi_ep_buf_info *buf_info)
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ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el,
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MHI_TRE_DATA_GET_LEN(el),
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MHI_EV_CC_EOT);
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if (ret < 0) {
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if (ret) {
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dev_err(&mhi_chan->mhi_dev->dev,
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"Error sending transfer compl. event\n");
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goto err_free_tre_buf;
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@ -449,7 +449,7 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi_cntrl,
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dev_dbg(dev, "Reading %zd bytes from channel (%u)\n", tr_len, ring->ch_id);
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ret = mhi_cntrl->read_async(mhi_cntrl, &buf_info);
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if (ret < 0) {
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if (ret) {
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dev_err(&mhi_chan->mhi_dev->dev, "Error reading from channel\n");
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goto err_free_buf_addr;
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}
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@ -494,7 +494,7 @@ static int mhi_ep_process_ch_ring(struct mhi_ep_ring *ring)
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} else {
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/* UL channel */
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ret = mhi_ep_read_channel(mhi_cntrl, ring);
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if (ret < 0) {
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if (ret) {
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dev_err(&mhi_chan->mhi_dev->dev, "Failed to read channel\n");
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return ret;
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}
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@ -591,7 +591,7 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, struct sk_buff *skb)
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dev_dbg(dev, "Writing %zd bytes to channel (%u)\n", tr_len, ring->ch_id);
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ret = mhi_cntrl->write_async(mhi_cntrl, &buf_info);
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if (ret < 0) {
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if (ret) {
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dev_err(dev, "Error writing to the channel\n");
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goto err_exit;
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}
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@ -49,7 +49,7 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, size_t end)
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buf_info.dev_addr = &ring->ring_cache[start];
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ret = mhi_cntrl->read_sync(mhi_cntrl, &buf_info);
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if (ret < 0)
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if (ret)
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return ret;
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} else {
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buf_info.size = (ring->ring_size - start) * sizeof(struct mhi_ring_element);
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@ -57,7 +57,7 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, size_t end)
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buf_info.dev_addr = &ring->ring_cache[start];
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ret = mhi_cntrl->read_sync(mhi_cntrl, &buf_info);
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if (ret < 0)
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if (ret)
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return ret;
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if (end) {
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@ -66,7 +66,7 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, size_t end)
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buf_info.size = end * sizeof(struct mhi_ring_element);
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ret = mhi_cntrl->read_sync(mhi_cntrl, &buf_info);
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if (ret < 0)
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if (ret)
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return ret;
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}
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}
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@ -308,7 +308,6 @@ static void mhi_free_bhi_buffer(struct mhi_controller *mhi_cntrl,
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struct mhi_buf *mhi_buf = image_info->mhi_buf;
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dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len, mhi_buf->buf, mhi_buf->dma_addr);
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kfree(image_info->mhi_buf);
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kfree(image_info);
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}
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@ -322,7 +321,6 @@ void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl,
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dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len,
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mhi_buf->buf, mhi_buf->dma_addr);
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kfree(image_info->mhi_buf);
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kfree(image_info);
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}
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@ -333,15 +331,10 @@ static int mhi_alloc_bhi_buffer(struct mhi_controller *mhi_cntrl,
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struct image_info *img_info;
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struct mhi_buf *mhi_buf;
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img_info = kzalloc_obj(*img_info);
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img_info = kzalloc_flex(*img_info, mhi_buf, 1);
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if (!img_info)
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return -ENOMEM;
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/* Allocate memory for entry */
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img_info->mhi_buf = kzalloc_obj(*img_info->mhi_buf);
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if (!img_info->mhi_buf)
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goto error_alloc_mhi_buf;
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/* Allocate and populate vector table */
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mhi_buf = img_info->mhi_buf;
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@ -358,8 +351,6 @@ static int mhi_alloc_bhi_buffer(struct mhi_controller *mhi_cntrl,
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return 0;
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error_alloc_segment:
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kfree(mhi_buf);
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error_alloc_mhi_buf:
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kfree(img_info);
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return -ENOMEM;
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@ -375,14 +366,11 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl,
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struct image_info *img_info;
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struct mhi_buf *mhi_buf;
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img_info = kzalloc_obj(*img_info);
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img_info = kzalloc_flex(*img_info, mhi_buf, segments);
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if (!img_info)
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return -ENOMEM;
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/* Allocate memory for entries */
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img_info->mhi_buf = kzalloc_objs(*img_info->mhi_buf, segments);
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if (!img_info->mhi_buf)
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goto error_alloc_mhi_buf;
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img_info->entries = segments;
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/* Allocate and populate vector table */
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mhi_buf = img_info->mhi_buf;
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@ -402,7 +390,6 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl,
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}
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img_info->bhi_vec = img_info->mhi_buf[segments - 1].buf;
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img_info->entries = segments;
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*image_info = img_info;
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return 0;
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@ -411,9 +398,6 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl,
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for (--i, --mhi_buf; i >= 0; i--, mhi_buf--)
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dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len,
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mhi_buf->buf, mhi_buf->dma_addr);
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kfree(img_info->mhi_buf);
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error_alloc_mhi_buf:
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kfree(img_info);
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return -ENOMEM;
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@ -253,6 +253,13 @@ static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = {
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MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4),
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MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5),
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MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5),
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MHI_CHANNEL_CONFIG_UL(48, "IP_SW1", 256, 6),
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MHI_CHANNEL_CONFIG_DL(49, "IP_SW1", 256, 6),
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MHI_CHANNEL_CONFIG_UL(50, "IP_ETH0", 256, 7),
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MHI_CHANNEL_CONFIG_DL(51, "IP_ETH0", 256, 7),
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MHI_CHANNEL_CONFIG_UL(52, "IP_ETH1", 256, 8),
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MHI_CHANNEL_CONFIG_DL(53, "IP_ETH1", 256, 8),
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};
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static struct mhi_event_config mhi_qcom_qdu100_events[] = {
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@ -268,6 +275,7 @@ static struct mhi_event_config mhi_qcom_qdu100_events[] = {
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MHI_EVENT_CONFIG_SW_DATA(5, 512),
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MHI_EVENT_CONFIG_SW_DATA(6, 512),
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MHI_EVENT_CONFIG_SW_DATA(7, 512),
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MHI_EVENT_CONFIG_SW_DATA(8, 512),
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};
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static const struct mhi_controller_config mhi_qcom_qdu100_config = {
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@ -407,6 +415,16 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
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.sideband_wake = false,
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};
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static const struct mhi_pci_dev_info mhi_qcom_sdx35_info = {
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.name = "qcom-sdx35m",
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.config = &modem_qcom_v2_mhiv_config,
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.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
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.dma_data_width = 32,
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.mru_default = 32768,
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.sideband_wake = false,
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.edl_trigger = true,
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};
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static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
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.name = "qcom-sdx24",
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.edl = "qcom/prog_firehose_sdx24.mbn",
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@ -788,6 +806,8 @@ static const struct mhi_channel_config mhi_telit_fn990_channels[] = {
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MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
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MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1),
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MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1),
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MHI_CHANNEL_CONFIG_UL(94, "NMEA", 32, 1),
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MHI_CHANNEL_CONFIG_DL(95, "NMEA", 32, 1),
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MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
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MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
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};
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@ -839,6 +859,8 @@ static const struct mhi_channel_config mhi_telit_fn920c04_channels[] = {
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MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
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MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1),
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MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1),
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MHI_CHANNEL_CONFIG_UL(94, "NMEA", 32, 1),
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MHI_CHANNEL_CONFIG_DL(95, "NMEA", 32, 1),
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MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
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MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3),
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};
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@ -882,6 +904,16 @@ static const struct mhi_pci_dev_info mhi_telit_fe990b40_info = {
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.edl_trigger = true,
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};
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static const struct mhi_pci_dev_info mhi_telit_fe912c04_info = {
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.name = "telit-fe912c04",
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.config = &modem_telit_fn920c04_config,
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.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
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.dma_data_width = 32,
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.sideband_wake = false,
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.mru_default = 32768,
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.edl_trigger = true,
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};
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static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = {
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.name = "netprisma-lcur57",
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.edl = "qcom/prog_firehose_sdx24.mbn",
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@ -909,6 +941,11 @@ static const struct pci_device_id mhi_pci_id_table[] = {
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/* Telit FN920C04 (sdx35) */
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{PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2020),
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.driver_data = (kernel_ulong_t) &mhi_telit_fn920c04_info },
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/* Telit FE912C04 (sdx35) */
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2045),
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.driver_data = (kernel_ulong_t) &mhi_telit_fe912c04_info },
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{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x011a),
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.driver_data = (kernel_ulong_t) &mhi_qcom_sdx35_info },
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{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
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.driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c),
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@ -1393,7 +1430,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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goto err_unregister;
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}
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err = mhi_sync_power_up(mhi_cntrl);
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err = mhi_async_power_up(mhi_cntrl);
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if (err) {
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dev_err(&pdev->dev, "failed to power up MHI controller\n");
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goto err_unprepare;
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@ -1428,6 +1465,7 @@ static void mhi_pci_remove(struct pci_dev *pdev)
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struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
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struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
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pm_runtime_forbid(&pdev->dev);
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pci_disable_sriov(pdev);
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if (pdev->is_physfn)
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@ -85,17 +85,33 @@ enum mhi_ch_type {
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MHI_CH_TYPE_INBOUND_COALESCED = 3,
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};
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/**
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* struct mhi_buf - MHI Buffer description
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* @buf: Virtual address of the buffer
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* @name: Buffer label. For offload channel, configurations name must be:
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* ECA - Event context array data
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* CCA - Channel context array data
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* @dma_addr: IOMMU address of the buffer
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* @len: # of bytes
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*/
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struct mhi_buf {
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void *buf;
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const char *name;
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dma_addr_t dma_addr;
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size_t len;
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};
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/**
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* struct image_info - Firmware and RDDM table
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* @mhi_buf: Buffer for firmware and RDDM table
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* @entries: # of entries in table
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*/
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struct image_info {
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struct mhi_buf *mhi_buf;
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/* private: from internal.h */
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struct bhi_vec_entry *bhi_vec;
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/* public: */
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u32 entries;
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struct mhi_buf mhi_buf[] __counted_by(entries);
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};
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/**
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@ -488,22 +504,6 @@ struct mhi_result {
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int transaction_status;
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};
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/**
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* struct mhi_buf - MHI Buffer description
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* @buf: Virtual address of the buffer
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* @name: Buffer label. For offload channel, configurations name must be:
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* ECA - Event context array data
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* CCA - Channel context array data
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* @dma_addr: IOMMU address of the buffer
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* @len: # of bytes
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*/
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struct mhi_buf {
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void *buf;
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const char *name;
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dma_addr_t dma_addr;
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size_t len;
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};
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/**
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* struct mhi_driver - Structure representing a MHI client driver
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* @probe: CB function for client driver probe function
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