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drm/msm/dpu: dpu_hw_ctl.h: fix all kernel-doc warnings
Correct and add kernel-doc comments to eliminate all warnings: Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:18 cannot understand function prototype: 'enum dpu_ctl_mode_sel' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:58 struct member 'wb' not described in 'dpu_hw_intf_cfg' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:66 Incorrect use of kernel-doc format: * kickoff hw operation for Sw controlled interfaces Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:73 Incorrect use of kernel-doc format: * check if the ctl is started Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:80 Incorrect use of kernel-doc format: * kickoff prepare is in progress hw operation for sw Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:88 Incorrect use of kernel-doc format: * Clear the value of the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:96 Incorrect use of kernel-doc format: * Query the value of the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:103 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:112 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(wb_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:121 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(cwb_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:130 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(intf_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:139 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(periph_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:148 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:157 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:166 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:175 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:185 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(dsc_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:194 Incorrect use of kernel-doc format: * OR in the given flushbits to the cached pending_(cdm_)flush_mask Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:202 Incorrect use of kernel-doc format: * Write the value of the pending_flush_mask to hardware Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:208 Incorrect use of kernel-doc format: * Read the value of the flush register Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:215 Incorrect use of kernel-doc format: * Setup ctl_path interface config Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:223 Incorrect use of kernel-doc format: * reset ctl_path interface config Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:244 Incorrect use of kernel-doc format: * Set all blend stages to disabled Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:250 Incorrect use of kernel-doc format: * Configure layer mixer to pipe configuration Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:262 Incorrect use of kernel-doc format: * Set active pipes attached to this CTL Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:270 Incorrect use of kernel-doc format: * Set active layer mixers attached to this CTL Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member 'trigger_start' not described in 'dpu_hw_ctl_ops' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member 'is_started' not described in 'dpu_hw_ctl_ops' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member 'trigger_pending' not described in 'dpu_hw_ctl_ops' [many here] Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member 'pending_periph_flush_mask' not described in 'dpu_hw_ctl' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member 'pending_merge_3d_flush_mask' not described in 'dpu_hw_ctl' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member 'pending_dspp_flush_mask' not described in 'dpu_hw_ctl' Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:327 expecting prototype for dpu_hw_ctl(). Prototype was for to_dpu_hw_ctl() instead Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/695649/ Link: https://lore.kernel.org/r/20251219184638.1813181-5-rdunlap@infradead.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Randy Dunlap
Dmitry Baryshkov
parent
ce26953807
commit
686f6aafd3
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@ -12,9 +12,9 @@
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#include "dpu_hw_sspp.h"
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/**
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* dpu_ctl_mode_sel: Interface mode selection
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* DPU_CTL_MODE_SEL_VID: Video mode interface
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* DPU_CTL_MODE_SEL_CMD: Command mode interface
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* enum dpu_ctl_mode_sel: Interface mode selection
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* @DPU_CTL_MODE_SEL_VID: Video mode interface
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* @DPU_CTL_MODE_SEL_CMD: Command mode interface
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*/
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enum dpu_ctl_mode_sel {
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DPU_CTL_MODE_SEL_VID = 0,
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@ -37,6 +37,7 @@ struct dpu_hw_stage_cfg {
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* struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
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* @intf : Interface id
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* @intf_master: Master interface id in the dual pipe topology
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* @wb: Writeback mode
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* @mode_3d: 3d mux configuration
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* @merge_3d: 3d merge block used
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* @intf_mode_sel: Interface mode, cmd / vid
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@ -64,21 +65,21 @@ struct dpu_hw_intf_cfg {
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*/
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struct dpu_hw_ctl_ops {
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/**
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* kickoff hw operation for Sw controlled interfaces
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* @trigger_start: kickoff hw operation for Sw controlled interfaces
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* DSI cmd mode and WB interface are SW controlled
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* @ctx : ctl path ctx pointer
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*/
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void (*trigger_start)(struct dpu_hw_ctl *ctx);
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/**
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* check if the ctl is started
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* @is_started: check if the ctl is started
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* @ctx : ctl path ctx pointer
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* @Return: true if started, false if stopped
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*/
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bool (*is_started)(struct dpu_hw_ctl *ctx);
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/**
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* kickoff prepare is in progress hw operation for sw
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* @trigger_pending: kickoff prepare is in progress hw operation for sw
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* controlled interfaces: DSI cmd mode and WB interface
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* are SW controlled
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* @ctx : ctl path ctx pointer
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@ -86,7 +87,7 @@ struct dpu_hw_ctl_ops {
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void (*trigger_pending)(struct dpu_hw_ctl *ctx);
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/**
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* Clear the value of the cached pending_flush_mask
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* @clear_pending_flush: Clear the value of the cached pending_flush_mask
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* No effect on hardware.
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* Required to be implemented.
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* @ctx : ctl path ctx pointer
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@ -94,14 +95,15 @@ struct dpu_hw_ctl_ops {
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void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
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/**
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* Query the value of the cached pending_flush_mask
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* @get_pending_flush: Query the value of the cached pending_flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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*/
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u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
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/**
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* OR in the given flushbits to the cached pending_flush_mask
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* @update_pending_flush: OR in the given flushbits to the cached
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* pending_flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @flushbits : module flushmask
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@ -110,7 +112,8 @@ struct dpu_hw_ctl_ops {
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u32 flushbits);
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/**
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* OR in the given flushbits to the cached pending_(wb_)flush_mask
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* @update_pending_flush_wb: OR in the given flushbits to the
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* cached pending_(wb_)flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : writeback block index
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@ -119,7 +122,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_wb blk);
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/**
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* OR in the given flushbits to the cached pending_(cwb_)flush_mask
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* @update_pending_flush_cwb: OR in the given flushbits to the
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* cached pending_(cwb_)flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : concurrent writeback block index
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@ -128,7 +132,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_cwb blk);
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/**
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* OR in the given flushbits to the cached pending_(intf_)flush_mask
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* @update_pending_flush_intf: OR in the given flushbits to the
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* cached pending_(intf_)flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : interface block index
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@ -137,7 +142,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_intf blk);
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/**
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* OR in the given flushbits to the cached pending_(periph_)flush_mask
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* @update_pending_flush_periph: OR in the given flushbits to the
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* cached pending_(periph_)flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : interface block index
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@ -146,7 +152,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_intf blk);
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/**
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* OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
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* @update_pending_flush_merge_3d: OR in the given flushbits to the
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* cached pending_(merge_3d_)flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : interface block index
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@ -155,7 +162,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_merge_3d blk);
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/**
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* OR in the given flushbits to the cached pending_flush_mask
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* @update_pending_flush_sspp: OR in the given flushbits to the
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* cached pending_flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : SSPP block index
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@ -164,7 +172,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_sspp blk);
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/**
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* OR in the given flushbits to the cached pending_flush_mask
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* @update_pending_flush_mixer: OR in the given flushbits to the
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* cached pending_flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : LM block index
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@ -173,7 +182,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_lm blk);
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/**
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* OR in the given flushbits to the cached pending_flush_mask
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* @update_pending_flush_dspp: OR in the given flushbits to the
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* cached pending_flush_mask.
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : DSPP block index
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@ -183,7 +193,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_dspp blk, u32 dspp_sub_blk);
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/**
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* OR in the given flushbits to the cached pending_(dsc_)flush_mask
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* @update_pending_flush_dsc: OR in the given flushbits to the
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* cached pending_(dsc_)flush_mask.
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* No effect on hardware
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* @ctx: ctl path ctx pointer
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* @blk: interface block index
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@ -192,7 +203,8 @@ struct dpu_hw_ctl_ops {
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enum dpu_dsc blk);
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/**
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* OR in the given flushbits to the cached pending_(cdm_)flush_mask
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* @update_pending_flush_cdm: OR in the given flushbits to the
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* cached pending_(cdm_)flush_mask.
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* No effect on hardware
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* @ctx: ctl path ctx pointer
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* @cdm_num: idx of cdm to be flushed
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@ -200,20 +212,20 @@ struct dpu_hw_ctl_ops {
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void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num);
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/**
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* Write the value of the pending_flush_mask to hardware
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* @trigger_flush: Write the value of the pending_flush_mask to hardware
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* @ctx : ctl path ctx pointer
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*/
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void (*trigger_flush)(struct dpu_hw_ctl *ctx);
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/**
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* Read the value of the flush register
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* @get_flush_register: Read the value of the flush register
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* @ctx : ctl path ctx pointer
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* @Return: value of the ctl flush register.
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*/
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u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
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/**
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* Setup ctl_path interface config
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* @setup_intf_cfg: Setup ctl_path interface config
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* @ctx
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* @cfg : interface config structure pointer
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*/
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@ -221,17 +233,20 @@ struct dpu_hw_ctl_ops {
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struct dpu_hw_intf_cfg *cfg);
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/**
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* reset ctl_path interface config
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* @reset_intf_cfg: reset ctl_path interface config
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* @ctx : ctl path ctx pointer
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* @cfg : interface config structure pointer
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*/
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void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,
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struct dpu_hw_intf_cfg *cfg);
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/**
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* @reset: reset function for this ctl type
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*/
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int (*reset)(struct dpu_hw_ctl *c);
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/*
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* wait_reset_status - checks ctl reset status
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/**
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* @wait_reset_status: checks ctl reset status
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* @ctx : ctl path ctx pointer
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*
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* This function checks the ctl reset status bit.
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@ -242,13 +257,13 @@ struct dpu_hw_ctl_ops {
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int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
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/**
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* Set all blend stages to disabled
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* @clear_all_blendstages: Set all blend stages to disabled
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* @ctx : ctl path ctx pointer
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*/
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void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
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/**
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* Configure layer mixer to pipe configuration
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* @setup_blendstage: Configure layer mixer to pipe configuration
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* @ctx : ctl path ctx pointer
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* @lm : layer mixer enumeration
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* @cfg : blend stage configuration
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@ -256,11 +271,16 @@ struct dpu_hw_ctl_ops {
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void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
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enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
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/**
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* @set_active_fetch_pipes: Set active pipes attached to this CTL
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* @ctx: ctl path ctx pointer
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* @active_pipes: bitmap of enum dpu_sspp
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*/
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void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx,
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unsigned long *fetch_active);
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/**
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* Set active pipes attached to this CTL
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* @set_active_pipes: Set active pipes attached to this CTL
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* @ctx: ctl path ctx pointer
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* @active_pipes: bitmap of enum dpu_sspp
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*/
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@ -268,13 +288,12 @@ struct dpu_hw_ctl_ops {
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unsigned long *active_pipes);
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/**
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* Set active layer mixers attached to this CTL
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* @set_active_lms: Set active layer mixers attached to this CTL
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* @ctx: ctl path ctx pointer
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* @active_lms: bitmap of enum dpu_lm
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*/
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void (*set_active_lms)(struct dpu_hw_ctl *ctx,
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unsigned long *active_lms);
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};
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/**
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@ -289,6 +308,9 @@ struct dpu_hw_ctl_ops {
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* @pending_intf_flush_mask: pending INTF flush
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* @pending_wb_flush_mask: pending WB flush
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* @pending_cwb_flush_mask: pending CWB flush
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* @pending_periph_flush_mask: pending PERIPH flush
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* @pending_merge_3d_flush_mask: pending MERGE 3D flush
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* @pending_dspp_flush_mask: pending DSPP flush
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* @pending_dsc_flush_mask: pending DSC flush
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* @pending_cdm_flush_mask: pending CDM flush
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* @mdss_ver: MDSS revision information
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@ -320,7 +342,7 @@ struct dpu_hw_ctl {
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};
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/**
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* dpu_hw_ctl - convert base object dpu_hw_base to container
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* to_dpu_hw_ctl - convert base object dpu_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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