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drm/amdgpu: move dpcs_3_0_0 headers from dcn to dpcs

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To align with other headers.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2022-02-03 12:52:21 -05:00
parent 120cc6e67a
commit 68550cbc61
9 changed files with 14 additions and 14 deletions
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4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
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@ -42,8 +42,8 @@
#include "nbio/nbio_7_4_offset.h"
#include "dcn/dpcs_3_0_0_offset.h"
#include "dcn/dpcs_3_0_0_sh_mask.h"
#include "dpcs/dpcs_3_0_0_offset.h"
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"

4
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
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@ -72,8 +72,8 @@
#include "nbio/nbio_7_4_offset.h"
#include "dcn/dpcs_3_0_0_offset.h"
#include "dcn/dpcs_3_0_0_sh_mask.h"
#include "dpcs/dpcs_3_0_0_offset.h"
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"

4
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
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@ -73,8 +73,8 @@
#include "nbio/nbio_7_2_0_offset.h"
#include "dcn/dpcs_3_0_0_offset.h"
#include "dcn/dpcs_3_0_0_sh_mask.h"
#include "dpcs/dpcs_3_0_0_offset.h"
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "reg_helper.h"
#include "dce/dmub_abm.h"

4
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
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@ -66,8 +66,8 @@
#include "dimgrey_cavefish_ip_offset.h"
#include "dcn/dcn_3_0_2_offset.h"
#include "dcn/dcn_3_0_2_sh_mask.h"
#include "dcn/dpcs_3_0_0_offset.h"
#include "dcn/dpcs_3_0_0_sh_mask.h"
#include "dpcs/dpcs_3_0_0_offset.h"
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "nbio/nbio_7_4_offset.h"
#include "amdgpu_socbb.h"

4
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
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@ -42,8 +42,8 @@
#include "nbio/nbio_7_4_offset.h"
#include "dcn/dpcs_3_0_0_offset.h"
#include "dcn/dpcs_3_0_0_sh_mask.h"
#include "dpcs/dpcs_3_0_0_offset.h"
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"

4
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
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@ -40,8 +40,8 @@
#include "nbio/nbio_7_4_offset.h"
#include "dcn/dpcs_3_0_0_offset.h"
#include "dcn/dpcs_3_0_0_sh_mask.h"
#include "dpcs/dpcs_3_0_0_offset.h"
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"

4
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
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@ -37,8 +37,8 @@
#include "nbio/nbio_7_4_offset.h"
#include "dcn/dpcs_3_0_0_offset.h"
#include "dcn/dpcs_3_0_0_sh_mask.h"
#include "dpcs/dpcs_3_0_0_offset.h"
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"

0
drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h → drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_offset.h
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0
drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h → drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_sh_mask.h
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