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drm/amdgpu/mes: remove some unused functions

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Nothing uses them so remove them.  Leftover from
MES bring up.

Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2025-05-19 15:51:47 -04:00
parent 40f970ba7a
commit 684530526f
2 changed files with 0 additions and 67 deletions
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63
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
View File

@ -458,33 +458,6 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
return r;
}
int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
uint32_t val, uint32_t mask)
{
struct mes_misc_op_input op_input;
int r;
op_input.op = MES_MISC_OP_WRM_REG_WAIT;
op_input.wrm_reg.reg0 = reg;
op_input.wrm_reg.ref = val;
op_input.wrm_reg.mask = mask;
if (!adev->mes.funcs->misc_op) {
dev_err(adev->dev, "mes reg wait is not supported!\n");
r = -EINVAL;
goto error;
}
amdgpu_mes_lock(&adev->mes);
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
amdgpu_mes_unlock(&adev->mes);
if (r)
dev_err(adev->dev, "failed to reg_write_reg_wait\n");
error:
return r;
}
int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
@ -553,42 +526,6 @@ int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
return r;
}
#define DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(_eng) \
do { \
if (id_offs < AMDGPU_MES_CTX_MAX_OFFS) \
return offsetof(struct amdgpu_mes_ctx_meta_data, \
_eng[ring->idx].slots[id_offs]); \
else if (id_offs == AMDGPU_MES_CTX_RING_OFFS) \
return offsetof(struct amdgpu_mes_ctx_meta_data, \
_eng[ring->idx].ring); \
else if (id_offs == AMDGPU_MES_CTX_IB_OFFS) \
return offsetof(struct amdgpu_mes_ctx_meta_data, \
_eng[ring->idx].ib); \
else if (id_offs == AMDGPU_MES_CTX_PADDING_OFFS) \
return offsetof(struct amdgpu_mes_ctx_meta_data, \
_eng[ring->idx].padding); \
} while(0)
int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs)
{
switch (ring->funcs->type) {
case AMDGPU_RING_TYPE_GFX:
DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(gfx);
break;
case AMDGPU_RING_TYPE_COMPUTE:
DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(compute);
break;
case AMDGPU_RING_TYPE_SDMA:
DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(sdma);
break;
default:
break;
}
WARN_ON(1);
return -EINVAL;
}
uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
enum amdgpu_mes_priority_level prio)
{

4
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
View File

@ -372,8 +372,6 @@ struct amdgpu_mes_funcs {
#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
#define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
int amdgpu_mes_init(struct amdgpu_device *adev);
void amdgpu_mes_fini(struct amdgpu_device *adev);
@ -395,8 +393,6 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
int amdgpu_mes_wreg(struct amdgpu_device *adev,
uint32_t reg, uint32_t val);
int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
uint32_t val, uint32_t mask);
int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
uint32_t reg0, uint32_t reg1,
uint32_t ref, uint32_t mask);