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Merge branch 'icc-eliza' into icc-next
Add the missing Eliza SDCC1 interconnect slave ID and provider node. The Eliza interconnect binding and provider already describe SDCC2, but the matching SDCC1 CNOC CFG slave was left out. Add the binding constant and the provider node so consumers can describe SDCC1 bandwidth paths. The provider change also adds qhs_sdc1 to qsm_cfg and bcm_cn0, and updates the qsm_cfg link count and bcm_cn0 node count. * icc-eliza dt-bindings: interconnect: qcom,eliza-rpmh: Add SDCC1 slave interconnect: qcom: eliza: Add SDCC1 slave node Link: https://patch.msgid.link/20260514-eliza-interconnect-add-missing-sdcc1-slave-node-v2-0-13c03bc890cb@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
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commit
67a4412db0
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@ -127,6 +127,12 @@ static struct qcom_icc_node qhs_qup2 = {
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.buswidth = 4,
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};
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static struct qcom_icc_node qhs_sdc1 = {
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.name = "qhs_sdc1",
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.channels = 1,
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.buswidth = 4,
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};
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static struct qcom_icc_node qhs_sdc2 = {
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.name = "qhs_sdc2",
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.channels = 1,
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@ -383,7 +389,7 @@ static struct qcom_icc_node qsm_cfg = {
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.name = "qsm_cfg",
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.channels = 1,
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.buswidth = 4,
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.num_links = 29,
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.num_links = 30,
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.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
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&qhs_camera_cfg, &qhs_clk_ctl,
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&qhs_crypto0_cfg, &qhs_display_cfg,
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@ -392,7 +398,7 @@ static struct qcom_icc_node qsm_cfg = {
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&qhs_mss_cfg, &qhs_pcie_0_cfg,
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&qhs_prng, &qhs_qdss_cfg,
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&qhs_qspi, &qhs_qup1,
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&qhs_qup2, &qhs_sdc2,
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&qhs_qup2, &qhs_sdc1, &qhs_sdc2,
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&qhs_tcsr, &qhs_tlmm,
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&qhs_ufs_mem_cfg, &qhs_usb3_0,
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&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
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@ -1111,7 +1117,7 @@ static struct qcom_icc_bcm bcm_cn0 = {
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.name = "CN0",
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.enable_mask = BIT(0),
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.keepalive = true,
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.num_nodes = 43,
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.num_nodes = 44,
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.nodes = { &qsm_cfg, &qhs_ahb2phy0,
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&qhs_ahb2phy1, &qhs_camera_cfg,
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&qhs_clk_ctl, &qhs_crypto0_cfg,
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@ -1119,7 +1125,7 @@ static struct qcom_icc_bcm bcm_cn0 = {
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&qhs_i3c_ibi1_cfg, &qhs_imem_cfg,
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&qhs_mss_cfg, &qhs_pcie_0_cfg,
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&qhs_prng, &qhs_qdss_cfg,
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&qhs_qspi, &qhs_sdc2,
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&qhs_qspi, &qhs_sdc1, &qhs_sdc2,
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&qhs_tcsr, &qhs_tlmm,
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&qhs_ufs_mem_cfg, &qhs_usb3_0,
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&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
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@ -1321,6 +1327,7 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
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[SLAVE_QSPI_0] = &qhs_qspi,
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[SLAVE_QUP_1] = &qhs_qup1,
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[SLAVE_QUP_2] = &qhs_qup2,
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[SLAVE_SDCC_1] = &qhs_sdc1,
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[SLAVE_SDCC_2] = &qhs_sdc2,
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[SLAVE_TCSR] = &qhs_tcsr,
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[SLAVE_TLMM] = &qhs_tlmm,
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@ -57,6 +57,7 @@
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#define SLAVE_PCIE_ANOC_CFG 27
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#define SLAVE_QDSS_STM 28
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#define SLAVE_TCU 29
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#define SLAVE_SDCC_1 30
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#define MASTER_GEM_NOC_CNOC 0
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#define MASTER_GEM_NOC_PCIE_SNOC 1
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