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arm: dts: stm32: introduce the debug bus for stm32mp1x platforms
Some peripherals cannot be probed if a debug configuration is not set in the BSEC. Introduce a debug bus that will check the debug subsystem accessibility before probing these peripheral drivers. Add Coresight peripheral nodes under this bus and add the appropriate access-controllers property to the HDP node. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20260226-debug_bus-v6-7-5d794697798d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Gatien Chevallier
Alexandre Torgue
parent
bb3fa3f8a4
commit
672d0510cc
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@ -3,6 +3,7 @@
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* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/arm/coresight-cti-dt.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp13-clks.h>
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#include <dt-bindings/reset/stm32mp13-resets.h>
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@ -964,9 +965,125 @@ hdp: pinctrl@5002a000 {
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compatible = "st,stm32mp131-hdp";
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reg = <0x5002a000 0x400>;
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clocks = <&rcc HDP>;
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access-controllers = <&dbg_bus 1>;
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status = "disabled";
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};
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dbg_bus: bus@50080000 {
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compatible = "st,stm32mp131-dbg-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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#access-controller-cells = <1>;
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ranges = <0x50080000 0x50080000 0x3f80000>;
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status = "disabled";
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cs_etf: etf@50092000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x50092000 0x1000>;
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clocks = <&rcc CK_DBG>;
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clock-names = "apb_pclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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in-ports {
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port {
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etf_in_port: endpoint {
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remote-endpoint = <&etm0_out_port>;
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};
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};
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};
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out-ports {
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port {
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etf_out_port: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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};
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};
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cs_tpiu: tpiu@50093000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0x50093000 0x1000>;
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clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
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clock-names = "apb_pclk", "atclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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in-ports {
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port {
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tpiu_in_port: endpoint {
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remote-endpoint = <&etf_out_port>;
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};
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};
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};
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};
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cs_cti_trace: cti@50094000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x50094000 0x1000>;
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clocks = <&rcc CK_DBG>;
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clock-names = "apb_pclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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};
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cs_cti_cpu0: cti@500d8000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x500d8000 0x1000>;
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clocks = <&rcc CK_DBG>;
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clock-names = "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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trig-conns@0 {
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reg = <0>;
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arm,trig-in-sigs = <0 4 5>;
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arm,trig-in-types = <PE_DBGTRIGGER
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GEN_IO
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GEN_IO>;
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arm,trig-out-sigs = <0 7>;
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arm,trig-out-types = <PE_EDBGREQ
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PE_DBGRESTART>;
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cpu = <&cpu0>;
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};
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trig-conns@2 {
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reg = <2>;
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arm,trig-in-sigs = <2 3 6>;
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arm,trig-in-types = <ETM_EXTOUT
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ETM_EXTOUT
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ETM_EXTOUT>;
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arm,trig-out-sigs = <1 2 3 4>;
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arm,trig-out-types = <ETM_EXTIN
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ETM_EXTIN
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ETM_EXTIN
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ETM_EXTIN>;
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arm,cs-dev-assoc = <&cs_etm0>;
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};
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};
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cs_etm0: etm@500dc000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x500dc000 0x1000>;
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cpu = <&cpu0>;
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clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
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clock-names = "apb_pclk", "atclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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out-ports {
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port {
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etm0_out_port: endpoint {
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remote-endpoint = <&etf_in_port>;
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};
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};
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};
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};
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};
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mdma: dma-controller@58000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x58000000 0x1000>;
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@ -3,6 +3,7 @@
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/arm/coresight-cti-dt.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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@ -282,9 +283,180 @@ hdp: pinctrl@5002a000 {
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compatible = "st,stm32mp151-hdp";
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reg = <0x5002a000 0x400>;
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clocks = <&rcc HDP>;
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access-controllers = <&dbg_bus 1>;
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status = "disabled";
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};
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dbg_bus: bus@50080000 {
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compatible = "st,stm32mp151-dbg-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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#access-controller-cells = <1>;
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ranges = <0x50080000 0x50080000 0x3f80000>,
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<0x90000000 0x90000000 0x1000000>;
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status = "disabled";
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cs_funnel: funnel@50091000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x50091000 0x1000>;
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clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
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clock-names = "apb_pclk", "atclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel_in_port0: endpoint {
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remote-endpoint = <&stm_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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funnel_in_port1: endpoint {
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remote-endpoint = <&etm0_out>;
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};
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};
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};
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out-ports {
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port {
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funnel_out_port: endpoint {
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remote-endpoint = <&etf_in_port>;
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};
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};
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};
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};
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cs_etf: etf@50092000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x50092000 0x1000>;
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clocks = <&rcc CK_DBG>;
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clock-names = "apb_pclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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in-ports {
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port {
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etf_in_port: endpoint {
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remote-endpoint = <&funnel_out_port>;
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};
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};
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};
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out-ports {
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port {
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etf_out_port: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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};
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};
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cs_tpiu: tpiu@50093000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0x50093000 0x1000>;
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clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
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clock-names = "apb_pclk", "atclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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in-ports {
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port {
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tpiu_in_port: endpoint {
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remote-endpoint = <&etf_out_port>;
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};
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};
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};
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};
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cs_cti_trace: cti@50094000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x50094000 0x1000>;
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clocks = <&rcc CK_DBG>;
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clock-names = "apb_pclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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};
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cs_stm: stm@500a0000 {
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compatible = "arm,coresight-stm", "arm,primecell";
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reg = <0x500a0000 0x00001000>,
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<0x90000000 0x01000000>;
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reg-names = "stm-base", "stm-stimulus-base";
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clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
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clock-names = "apb_pclk", "atclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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out-ports {
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port {
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stm_out_port: endpoint {
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remote-endpoint = <&funnel_in_port0>;
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};
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};
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};
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};
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cs_cti_cpu0: cti@500d8000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x500d8000 0x1000>;
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clocks = <&rcc CK_DBG>;
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clock-names = "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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trig-conns@0 {
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reg = <0>;
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arm,trig-in-sigs = <0 4 5>;
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arm,trig-in-types = <PE_DBGTRIGGER
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GEN_IO
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GEN_IO>;
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arm,trig-out-sigs = <0 7>;
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arm,trig-out-types = <PE_EDBGREQ
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PE_DBGRESTART>;
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cpu = <&cpu0>;
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};
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trig-conns@2 {
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reg = <2>;
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arm,trig-in-sigs = <2 3 6>;
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arm,trig-in-types = <ETM_EXTOUT
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ETM_EXTOUT
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ETM_EXTOUT>;
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arm,trig-out-sigs = <1 2 3 4>;
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arm,trig-out-types = <ETM_EXTIN
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ETM_EXTIN
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ETM_EXTIN
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ETM_EXTIN>;
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arm,cs-dev-assoc = <&cs_etm0>;
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};
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};
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cs_etm0: etm@500dc000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x500dc000 0x1000>;
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cpu = <&cpu0>;
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clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
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clock-names = "apb_pclk", "atclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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out-ports {
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port {
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etm0_out: endpoint {
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remote-endpoint = <&funnel_in_port1>;
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};
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};
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};
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};
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};
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mdma1: dma-controller@58000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x58000000 0x1000>;
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@ -30,6 +30,74 @@ timer {
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};
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};
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&cs_funnel {
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in-ports {
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port@2 {
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reg = <2>;
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funnel_in_port2: endpoint {
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remote-endpoint = <&etm1_out>;
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};
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};
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};
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};
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&dbg_bus {
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cs_cti_cpu1: cti@500d9000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x500d9000 0x1000>;
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clocks = <&rcc CK_DBG>;
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clock-names = "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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trig-conns@0 {
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reg = <0>;
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arm,trig-in-sigs = <0 4 5>;
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arm,trig-in-types = <PE_DBGTRIGGER
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GEN_IO
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GEN_IO>;
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arm,trig-out-sigs = <0 7>;
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arm,trig-out-types = <PE_EDBGREQ
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PE_DBGRESTART>;
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cpu = <&cpu1>;
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};
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trig-conns@2 {
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reg = <2>;
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arm,trig-in-sigs = <2 3 6>;
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arm,trig-in-types = <ETM_EXTOUT
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ETM_EXTOUT
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ETM_EXTOUT>;
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arm,trig-out-sigs = <1 2 3 4>;
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arm,trig-out-types = <ETM_EXTIN
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ETM_EXTIN
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ETM_EXTIN
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ETM_EXTIN>;
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arm,cs-dev-assoc = <&cs_etm1>;
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};
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};
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cs_etm1: etm@500dd000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x500dd000 0x1000>;
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cpu = <&cpu1>;
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clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
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clock-names = "apb_pclk", "atclk";
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access-controllers = <&dbg_bus 0>;
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status = "disabled";
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out-ports {
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port {
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etm1_out: endpoint {
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remote-endpoint = <&funnel_in_port2>;
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};
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};
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};
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};
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};
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&etzpc {
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m_can1: can@4400e000 {
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compatible = "bosch,m_can";
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