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net: stmmac: descs: remove many xxx_SHIFT definitions

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Remove many xxx_SHIFT definitions for descriptors, isntead using
FIELD_PREP(), FIELD_GET(), and u32_replace_bits() as appropriate to
manipulate the bitfields. This avoids potential errors where an
incorrect shift is used with a mask.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vdtw2-00000002Gto-3ZPt@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle) 2026-01-08 17:36:34 +00:00 committed by Jakub Kicinski
parent d3b8c9b393
commit 670d10509f
8 changed files with 55 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/net/ethernet/stmicro/stmmac/descs.h
View File

@ -32,13 +32,11 @@
#define RDES0_DESCRIPTOR_ERROR BIT(14)
#define RDES0_ERROR_SUMMARY BIT(15)
#define RDES0_FRAME_LEN_MASK GENMASK(29, 16)
#define RDES0_FRAME_LEN_SHIFT 16
#define RDES0_DA_FILTER_FAIL BIT(30)
#define RDES0_OWN BIT(31)
/* RDES1 */
#define RDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
#define RDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
#define RDES1_BUFFER2_SIZE_SHIFT 11
#define RDES1_SECOND_ADDRESS_CHAINED BIT(24)
#define RDES1_END_RING BIT(25)
#define RDES1_DISABLE_IC BIT(31)
@ -53,7 +51,6 @@
#define ERDES1_SECOND_ADDRESS_CHAINED BIT(14)
#define ERDES1_END_RING BIT(15)
#define ERDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
#define ERDES1_BUFFER2_SIZE_SHIFT 16
#define ERDES1_DISABLE_IC BIT(31)
/* Normal transmit descriptor defines */
@ -77,14 +74,12 @@
/* TDES1 */
#define TDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
#define TDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
#define TDES1_BUFFER2_SIZE_SHIFT 11
#define TDES1_TIME_STAMP_ENABLE BIT(22)
#define TDES1_DISABLE_PADDING BIT(23)
#define TDES1_SECOND_ADDRESS_CHAINED BIT(24)
#define TDES1_END_RING BIT(25)
#define TDES1_CRC_DISABLE BIT(26)
#define TDES1_CHECKSUM_INSERTION_MASK GENMASK(28, 27)
#define TDES1_CHECKSUM_INSERTION_SHIFT 27
#define TDES1_FIRST_SEGMENT BIT(29)
#define TDES1_LAST_SEGMENT BIT(30)
#define TDES1_INTERRUPT BIT(31)
@ -109,7 +104,6 @@
#define ETDES0_SECOND_ADDRESS_CHAINED BIT(20)
#define ETDES0_END_RING BIT(21)
#define ETDES0_CHECKSUM_INSERTION_MASK GENMASK(23, 22)
#define ETDES0_CHECKSUM_INSERTION_SHIFT 22
#define ETDES0_TIME_STAMP_ENABLE BIT(25)
#define ETDES0_DISABLE_PADDING BIT(26)
#define ETDES0_CRC_DISABLE BIT(27)
@ -120,7 +114,6 @@
/* TDES1 */
#define ETDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)
#define ETDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
#define ETDES1_BUFFER2_SIZE_SHIFT 16
/* Extended Receive descriptor definitions */
#define ERDES4_IP_PAYLOAD_TYPE_MASK GENMASK(6, 2)

32
drivers/net/ethernet/stmicro/stmmac/descs_com.h
View File

@ -23,9 +23,8 @@ static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end,
int bfsize)
{
if (bfsize == BUF_SIZE_16KiB)
p->des1 |= cpu_to_le32((BUF_SIZE_8KiB
<< ERDES1_BUFFER2_SIZE_SHIFT)
& ERDES1_BUFFER2_SIZE_MASK);
p->des1 |= cpu_to_le32(FIELD_PREP(ERDES1_BUFFER2_SIZE_MASK,
BUF_SIZE_8KiB));
if (end)
p->des1 |= cpu_to_le32(ERDES1_END_RING);
@ -45,12 +44,13 @@ static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
unsigned int buffer1_max_length = BUF_SIZE_4KiB;
if (unlikely(len > buffer1_max_length)) {
p->des1 |= cpu_to_le32((((len - buffer1_max_length)
<< ETDES1_BUFFER2_SIZE_SHIFT)
& ETDES1_BUFFER2_SIZE_MASK) | (buffer1_max_length
& ETDES1_BUFFER1_SIZE_MASK));
p->des1 |= cpu_to_le32(FIELD_PREP(ETDES1_BUFFER2_SIZE_MASK,
len - buffer1_max_length) |
FIELD_PREP(ETDES1_BUFFER1_SIZE_MASK,
buffer1_max_length));
} else {
p->des1 |= cpu_to_le32((len & ETDES1_BUFFER1_SIZE_MASK));
p->des1 |= cpu_to_le32(FIELD_PREP(ETDES1_BUFFER1_SIZE_MASK,
len));
}
}
@ -61,8 +61,8 @@ static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end, int bfsize)
int bfsize2;
bfsize2 = min(bfsize - BUF_SIZE_2KiB + 1, BUF_SIZE_2KiB - 1);
p->des1 |= cpu_to_le32((bfsize2 << RDES1_BUFFER2_SIZE_SHIFT)
& RDES1_BUFFER2_SIZE_MASK);
p->des1 |= cpu_to_le32(FIELD_PREP(RDES1_BUFFER2_SIZE_MASK,
bfsize2));
}
if (end)
@ -83,13 +83,13 @@ static inline void norm_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
unsigned int buffer1_max_length = BUF_SIZE_2KiB - 1;
if (unlikely(len > buffer1_max_length)) {
unsigned int buffer1 = buffer1_max_length &
TDES1_BUFFER1_SIZE_MASK;
p->des1 |= cpu_to_le32((((len - buffer1_max_length)
<< TDES1_BUFFER2_SIZE_SHIFT)
& TDES1_BUFFER2_SIZE_MASK) | buffer1);
p->des1 |= cpu_to_le32(FIELD_PREP(TDES1_BUFFER2_SIZE_MASK,
len - buffer1_max_length) |
FIELD_PREP(TDES1_BUFFER1_SIZE_MASK,
buffer1_max_length));
} else {
p->des1 |= cpu_to_le32((len & TDES1_BUFFER1_SIZE_MASK));
p->des1 |= cpu_to_le32(FIELD_PREP(TDES1_BUFFER1_SIZE_MASK,
len));
}
}

48
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
View File

@ -44,8 +44,7 @@ static int dwmac4_wrback_get_tx_status(struct stmmac_extra_stats *x,
if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
(tdes3 & TDES3_EXCESSIVE_COLLISION)))
x->tx_collision +=
(tdes3 & TDES3_COLLISION_COUNT_MASK)
>> TDES3_COLLISION_COUNT_SHIFT;
FIELD_GET(TDES3_COLLISION_COUNT_MASK, tdes3);
if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
x->tx_deferred++;
@ -166,8 +165,7 @@ static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
x->l3_filter_match++;
if (rdes2 & RDES2_L4_FILTER_MATCH)
x->l4_filter_match++;
if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
>> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
if (rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
x->l3_l4_filter_no_match++;
return ret;
@ -256,12 +254,11 @@ static int dwmac4_rx_check_timestamp(void *desc)
u32 rdes0 = le32_to_cpu(p->des0);
u32 rdes1 = le32_to_cpu(p->des1);
u32 rdes3 = le32_to_cpu(p->des3);
u32 own, ctxt;
bool own, ctxt;
int ret = 1;
own = rdes3 & RDES3_OWN;
ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
ctxt = rdes3 & RDES3_CONTEXT_DESCRIPTOR;
if (likely(!own && ctxt)) {
if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
@ -335,10 +332,8 @@ static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
else
tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
if (likely(csum_flag))
tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
else
tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
tdes3 = u32_replace_bits(tdes3, csum_flag ? TX_CIC_FULL : 0,
TDES3_CHECKSUM_INSERTION_MASK);
if (ls)
tdes3 |= TDES3_LAST_DESCRIPTOR;
@ -367,18 +362,18 @@ static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
u32 tdes3 = le32_to_cpu(p->des3);
if (len1)
p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_BUFFER1_SIZE_MASK,
len1));
if (len2)
p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
& TDES2_BUFFER2_SIZE_MASK);
p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_BUFFER2_SIZE_MASK,
len2));
if (is_fs) {
tdes3 |= TDES3_FIRST_DESCRIPTOR |
TDES3_TCP_SEGMENTATION_ENABLE |
((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
TDES3_SLOT_NUMBER_MASK) |
((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
FIELD_PREP(TDES3_SLOT_NUMBER_MASK, tcphdrlen) |
FIELD_PREP(TDES3_TCP_PKT_PAYLOAD_MASK, tcppayloadlen);
} else {
tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
}
@ -489,9 +484,8 @@ static void dwmac4_clear(struct dma_desc *p)
static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
{
sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
p->des3 |= cpu_to_le32(FIELD_PREP(TDES3_SA_INSERT_CTRL_MASK,
sarc_type));
}
static int set_16kib_bfsize(int mtu)
@ -513,14 +507,9 @@ static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
/* Inner VLAN */
if (inner_type) {
u32 des = inner_tag << TDES2_IVT_SHIFT;
des &= TDES2_IVT_MASK;
p->des2 = cpu_to_le32(des);
des = inner_type << TDES3_IVTIR_SHIFT;
des &= TDES3_IVTIR_MASK;
p->des3 = cpu_to_le32(des | TDES3_IVLTV);
p->des2 = cpu_to_le32(FIELD_PREP(TDES2_IVT_MASK, inner_tag));
p->des3 = cpu_to_le32(FIELD_PREP(TDES3_IVTIR_MASK, inner_type) |
TDES3_IVLTV);
}
/* Outer VLAN */
@ -532,8 +521,7 @@ static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
{
type <<= TDES2_VLAN_TAG_SHIFT;
p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_VLAN_TAG_MASK, type));
}
static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)

8
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h
View File

@ -18,15 +18,11 @@
/* TDES2 (read format) */
#define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0)
#define TDES2_VLAN_TAG_MASK GENMASK(15, 14)
#define TDES2_VLAN_TAG_SHIFT 14
#define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16)
#define TDES2_BUFFER2_SIZE_MASK_SHIFT 16
#define TDES3_IVTIR_MASK GENMASK(19, 18)
#define TDES3_IVTIR_SHIFT 18
#define TDES3_IVLTV BIT(17)
#define TDES2_TIMESTAMP_ENABLE BIT(30)
#define TDES2_IVT_MASK GENMASK(31, 16)
#define TDES2_IVT_SHIFT 16
#define TDES2_INTERRUPT_ON_COMPLETION BIT(31)
/* TDES3 (read format) */
@ -34,13 +30,10 @@
#define TDES3_VLAN_TAG GENMASK(15, 0)
#define TDES3_VLTV BIT(16)
#define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16)
#define TDES3_CHECKSUM_INSERTION_SHIFT 16
#define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0)
#define TDES3_TCP_SEGMENTATION_ENABLE BIT(18)
#define TDES3_HDR_LEN_SHIFT 19
#define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19)
#define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23)
#define TDES3_SA_INSERT_CTRL_SHIFT 23
#define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26)
/* TDES3 (write back format) */
@ -49,7 +42,6 @@
#define TDES3_UNDERFLOW_ERROR BIT(2)
#define TDES3_EXCESSIVE_DEFERRAL BIT(3)
#define TDES3_COLLISION_COUNT_MASK GENMASK(7, 4)
#define TDES3_COLLISION_COUNT_SHIFT 4
#define TDES3_EXCESSIVE_COLLISION BIT(8)
#define TDES3_LATE_COLLISION BIT(9)
#define TDES3_NO_CARRIER BIT(10)

9
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
View File

@ -423,32 +423,24 @@
#define XGMAC_TDES0_LT GENMASK(7, 0)
#define XGMAC_TDES1_LT GENMASK(31, 8)
#define XGMAC_TDES2_IVT GENMASK(31, 16)
#define XGMAC_TDES2_IVT_SHIFT 16
#define XGMAC_TDES2_IOC BIT(31)
#define XGMAC_TDES2_TTSE BIT(30)
#define XGMAC_TDES2_B2L GENMASK(29, 16)
#define XGMAC_TDES2_B2L_SHIFT 16
#define XGMAC_TDES2_VTIR GENMASK(15, 14)
#define XGMAC_TDES2_VTIR_SHIFT 14
#define XGMAC_TDES2_B1L GENMASK(13, 0)
#define XGMAC_TDES3_OWN BIT(31)
#define XGMAC_TDES3_CTXT BIT(30)
#define XGMAC_TDES3_FD BIT(29)
#define XGMAC_TDES3_LD BIT(28)
#define XGMAC_TDES3_CPC GENMASK(27, 26)
#define XGMAC_TDES3_CPC_SHIFT 26
#define XGMAC_TDES3_TCMSSV BIT(26)
#define XGMAC_TDES3_SAIC GENMASK(25, 23)
#define XGMAC_TDES3_SAIC_SHIFT 23
#define XGMAC_TDES3_TBSV BIT(24)
#define XGMAC_TDES3_THL GENMASK(22, 19)
#define XGMAC_TDES3_THL_SHIFT 19
#define XGMAC_TDES3_IVTIR GENMASK(19, 18)
#define XGMAC_TDES3_IVTIR_SHIFT 18
#define XGMAC_TDES3_TSE BIT(18)
#define XGMAC_TDES3_IVLTV BIT(17)
#define XGMAC_TDES3_CIC GENMASK(17, 16)
#define XGMAC_TDES3_CIC_SHIFT 16
#define XGMAC_TDES3_TPL GENMASK(17, 0)
#define XGMAC_TDES3_VLTV BIT(16)
#define XGMAC_TDES3_VT GENMASK(15, 0)
@ -461,7 +453,6 @@
#define XGMAC_RDES3_CDA BIT(27)
#define XGMAC_RDES3_RSV BIT(26)
#define XGMAC_RDES3_L34T GENMASK(23, 20)
#define XGMAC_RDES3_L34T_SHIFT 20
#define XGMAC_RDES3_ET_LT GENMASK(19, 16)
#define XGMAC_L34T_IP4TCP 0x1
#define XGMAC_L34T_IP4UDP 0x2

25
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
View File

@ -173,7 +173,7 @@ static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
tdes3 &= ~XGMAC_TDES3_FD;
if (csum_flag)
tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT;
tdes3 |= FIELD_PREP(XGMAC_TDES3_CIC, 0x3);
else
tdes3 &= ~XGMAC_TDES3_CIC;
@ -206,13 +206,11 @@ static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
if (len1)
p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L);
if (len2)
p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) &
XGMAC_TDES2_B2L);
p->des2 |= cpu_to_le32(FIELD_PREP(XGMAC_TDES2_B2L, len2));
if (is_fs) {
tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE;
tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) &
XGMAC_TDES3_THL;
tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL;
tdes3 |= FIELD_PREP(XGMAC_TDES3_THL, tcphdrlen);
tdes3 |= FIELD_PREP(XGMAC_TDES3_TPL, tcppayloadlen);
} else {
tdes3 &= ~XGMAC_TDES3_FD;
}
@ -278,7 +276,7 @@ static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,
u32 ptype;
if (rdes3 & XGMAC_RDES3_RSV) {
ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT;
ptype = FIELD_GET(XGMAC_RDES3_L34T, rdes3);
switch (ptype) {
case XGMAC_L34T_IP4TCP:
@ -313,9 +311,7 @@ static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_v
static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)
{
sarc_type <<= XGMAC_TDES3_SAIC_SHIFT;
p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC);
p->des3 |= cpu_to_le32(FIELD_PREP(XGMAC_TDES3_SAIC, sarc_type));
}
static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
@ -328,13 +324,11 @@ static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
/* Inner VLAN */
if (inner_type) {
u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT;
u32 des = FIELD_PREP(XGMAC_TDES2_IVT, inner_tag);
des &= XGMAC_TDES2_IVT;
p->des2 = cpu_to_le32(des);
des = inner_type << XGMAC_TDES3_IVTIR_SHIFT;
des &= XGMAC_TDES3_IVTIR;
des = FIELD_PREP(XGMAC_TDES3_IVTIR, inner_type);
p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV);
}
@ -347,8 +341,7 @@ static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)
{
type <<= XGMAC_TDES2_VTIR_SHIFT;
p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);
p->des2 |= cpu_to_le32(FIELD_PREP(XGMAC_TDES2_VTIR, type));
}
static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)

17
drivers/net/ethernet/stmicro/stmmac/enh_desc.c
View File

@ -44,7 +44,7 @@ static int enh_desc_get_tx_status(struct stmmac_extra_stats *x,
if (unlikely((tdes0 & ETDES0_LATE_COLLISION) ||
(tdes0 & ETDES0_EXCESSIVE_COLLISIONS)))
x->tx_collision +=
(tdes0 & ETDES0_COLLISION_COUNT_MASK) >> 3;
FIELD_GET(ETDES0_COLLISION_COUNT_MASK, tdes0);
if (unlikely(tdes0 & ETDES0_EXCESSIVE_DEFERRAL))
x->tx_deferred++;
@ -121,7 +121,7 @@ static void enh_desc_get_ext_status(struct stmmac_extra_stats *x,
u32 rdes4 = le32_to_cpu(p->des4);
if (unlikely(rdes0 & ERDES0_RX_MAC_ADDR)) {
int message_type = (rdes4 & ERDES4_MSG_TYPE_MASK) >> 8;
int message_type = FIELD_GET(ERDES4_MSG_TYPE_MASK, rdes4);
if (rdes4 & ERDES4_IP_HDR_ERR)
x->ip_hdr_err++;
@ -167,13 +167,13 @@ static void enh_desc_get_ext_status(struct stmmac_extra_stats *x,
x->av_pkt_rcvd++;
if (rdes4 & ERDES4_AV_TAGGED_PKT_RCVD)
x->av_tagged_pkt_rcvd++;
if ((rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK) >> 18)
if (rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK)
x->vlan_tag_priority_val++;
if (rdes4 & ERDES4_L3_FILTER_MATCH)
x->l3_filter_match++;
if (rdes4 & ERDES4_L4_FILTER_MATCH)
x->l4_filter_match++;
if ((rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK) >> 26)
if (rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK)
x->l3_l4_filter_no_match++;
}
}
@ -324,10 +324,8 @@ static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
else
tdes0 &= ~ETDES0_FIRST_SEGMENT;
if (likely(csum_flag))
tdes0 |= (TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
else
tdes0 &= ~(TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
tdes0 = u32_replace_bits(tdes0, csum_flag ? TX_CIC_FULL : 0,
ETDES0_CHECKSUM_INSERTION_MASK);
if (ls)
tdes0 |= ETDES0_LAST_SEGMENT;
@ -363,8 +361,7 @@ static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
if (rx_coe_type == STMMAC_RX_COE_TYPE1)
csum = 2;
return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)
>> RDES0_FRAME_LEN_SHIFT) - csum);
return FIELD_GET(RDES0_FRAME_LEN_MASK, le32_to_cpu(p->des0)) - csum;
}
static void enh_desc_enable_tx_timestamp(struct dma_desc *p)

17
drivers/net/ethernet/stmicro/stmmac/norm_desc.c
View File

@ -40,10 +40,8 @@ static int ndesc_get_tx_status(struct stmmac_extra_stats *x,
if (unlikely((tdes0 & TDES0_EXCESSIVE_DEFERRAL) ||
(tdes0 & TDES0_EXCESSIVE_COLLISIONS) ||
(tdes0 & TDES0_LATE_COLLISION))) {
unsigned int collisions;
collisions = (tdes0 & TDES0_COLLISION_COUNT_MASK) >> 3;
x->tx_collision += collisions;
x->tx_collision +=
FIELD_GET(TDES0_COLLISION_COUNT_MASK, tdes0);
}
ret = tx_err;
}
@ -185,10 +183,8 @@ static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
else
tdes1 &= ~TDES1_FIRST_SEGMENT;
if (likely(csum_flag))
tdes1 |= (TX_CIC_FULL) << TDES1_CHECKSUM_INSERTION_SHIFT;
else
tdes1 &= ~(TX_CIC_FULL << TDES1_CHECKSUM_INSERTION_SHIFT);
tdes1 = u32_replace_bits(tdes1, csum_flag ? TX_CIC_FULL : 0,
TDES1_CHECKSUM_INSERTION_MASK);
if (ls)
tdes1 |= TDES1_LAST_SEGMENT;
@ -222,10 +218,7 @@ static int ndesc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
if (rx_coe_type == STMMAC_RX_COE_TYPE1)
csum = 2;
return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)
>> RDES0_FRAME_LEN_SHIFT) -
csum);
return FIELD_GET(RDES0_FRAME_LEN_MASK, le32_to_cpu(p->des0)) - csum;
}
static void ndesc_enable_tx_timestamp(struct dma_desc *p)