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riscv: dts: spacemit: k3: add clock tree

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Add clock support to SpacemiT K3 SoC, the clock tree consist of several
blocks which are APBC, APMU, DCIU, MPUM.

Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-1-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
This commit is contained in:
Yixun Lan 2026-03-04 07:36:42 +00:00
parent 606a6b8bca
commit 67072c8cd4
1 changed files with 75 additions and 0 deletions
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75
arch/riscv/boot/dts/spacemit/k3.dtsi
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@ -4,6 +4,7 @@
* Copyright (c) 2026 Guodong Xu <guodong@riscstar.com> * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
*/ */
#include <dt-bindings/clock/spacemit,k3-clocks.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
/dts-v1/; /dts-v1/;
@ -398,6 +399,36 @@ core3 {
}; };
}; };
clocks {
vctcxo_1m: clock-1m {
compatible = "fixed-clock";
clock-frequency = <1000000>;
clock-output-names = "vctcxo_1m";
#clock-cells = <0>;
};
vctcxo_24m: clock-24m {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "vctcxo_24m";
#clock-cells = <0>;
};
vctcxo_3m: clock-3m {
compatible = "fixed-clock";
clock-frequency = <3000000>;
clock-output-names = "vctcxo_3m";
#clock-cells = <0>;
};
osc_32k: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "osc_32k";
#clock-cells = <0>;
};
};
soc: soc { soc: soc {
compatible = "simple-bus"; compatible = "simple-bus";
interrupt-parent = <&saplic>; interrupt-parent = <&saplic>;
@ -406,6 +437,15 @@ soc: soc {
dma-noncoherent; dma-noncoherent;
ranges; ranges;
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k3-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
#clock-cells = <1>;
#reset-cells = <1>;
};
uart0: serial@d4017000 { uart0: serial@d4017000 {
compatible = "spacemit,k3-uart", "intel,xscale-uart"; compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017000 0x0 0x100>; reg = <0x0 0xd4017000 0x0 0x100>;
@ -506,6 +546,41 @@ uart10: serial@d401f000 {
status = "disabled"; status = "disabled";
}; };
syscon_mpmu: system-controller@d4050000 {
compatible = "spacemit,k3-syscon-mpmu";
reg = <0x0 0xd4050000 0x0 0x10000>;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
pll: clock-controller@d4090000 {
compatible = "spacemit,k3-pll";
reg = <0x0 0xd4090000 0x0 0x10000>;
clocks = <&vctcxo_24m>;
spacemit,mpmu = <&syscon_mpmu>;
#clock-cells = <1>;
};
syscon_apmu: system-controller@d4282800 {
compatible = "spacemit,k3-syscon-apmu";
reg = <0x0 0xd4282800 0x0 0x400>;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
syscon_dciu: system-controller@d8440000 {
compatible = "spacemit,k3-syscon-dciu";
reg = <0x0 0xd8440000 0x0 0xc000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
simsic: interrupt-controller@e0400000 { simsic: interrupt-controller@e0400000 {
compatible = "spacemit,k3-imsics", "riscv,imsics"; compatible = "spacemit,k3-imsics", "riscv,imsics";
reg = <0x0 0xe0400000 0x0 0x200000>; reg = <0x0 0xe0400000 0x0 0x200000>;