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arm64: dts: rockchip: rk3588s: Add leakage information

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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Icaa30bcda38461cb7fc69d83672e9ff8fe73abd3
This commit is contained in:
Finley Xiao 2022-03-26 17:10:49 +08:00 committed by Tao Huang
parent 5c428cc16e
commit 67031fb1cc
1 changed files with 39 additions and 0 deletions
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39
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@ -570,6 +570,9 @@ cluster0_opp_table: cluster0-opp-table {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpul_leakage>;
nvmem-cell-names = "leakage";
rockchip,pvtm-voltage-sel = <
0 1410 0
1411 1434 1
@ -699,6 +702,9 @@ cluster1_opp_table: cluster1-opp-table {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpub0_leakage>;
nvmem-cell-names = "leakage";
rockchip,pvtm-voltage-sel = <
0 1640 0
1641 1675 1
@ -859,6 +865,9 @@ cluster2_opp_table: cluster2-opp-table {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpub1_leakage>;
nvmem-cell-names = "leakage";
rockchip,pvtm-voltage-sel = <
0 1640 0
1641 1675 1
@ -1159,6 +1168,9 @@ SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&log_leakage>;
nvmem-cell-names = "leakage";
opp-2750000000 {
opp-hz = /bits/ 64 <2750000000>;
opp-microvolt = <850000>;
@ -1509,6 +1521,9 @@ gpu: gpu@fb000000 {
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&gpu_leakage>;
nvmem-cell-names = "leakage";
rockchip,pvtm-voltage-sel = <
0 830 0
831 855 1
@ -2496,6 +2511,9 @@ rknpu: npu@fdab0000 {
npu_opp_table: npu-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&npu_leakage>;
nvmem-cell-names = "leakage";
rockchip,pvtm-voltage-sel = <
0 840 0
841 865 1
@ -5270,6 +5288,27 @@ otp_cpu_version: cpu-version@1c {
reg = <0x1c 0x1>;
bits = <3 3>;
};
cpub0_leakage: cpub0-leakage@17 {
reg = <0x17 0x1>;
};
cpub1_leakage: cpub1-leakage@18 {
reg = <0x18 0x1>;
};
cpul_leakage: cpul-leakage@19 {
reg = <0x19 0x1>;
};
log_leakage: log-leakage@1a {
reg = <0x1a 0x1>;
};
gpu_leakage: gpu-leakage@1b {
reg = <0x1b 0x1>;
};
npu_leakage: npu-leakage@28 {
reg = <0x28 0x1>;
};
codec_leakage: codec-leakage@29 {
reg = <0x29 0x1>;
};
};
mailbox2: mailbox@fece0000 {