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RISC-V: define the elements of the VCSR vector CSR

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The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].

Define constants for those to access the elements in a readable way.

Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-6-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Heiko Stuebner 2024-11-13 18:21:12 -08:00 committed by Palmer Dabbelt
parent 377be47f90
commit 66f197785d
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4
arch/riscv/include/asm/csr.h
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@ -314,6 +314,10 @@
#define CSR_STIMECMP 0x14D
#define CSR_STIMECMPH 0x15D
#define VCSR_VXRM_MASK 3
#define VCSR_VXRM_SHIFT 1
#define VCSR_VXSAT_MASK 1
/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
#define CSR_SISELECT 0x150
#define CSR_SIREG 0x151