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irqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpers

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The __pdc_enable_intr() function contains a version branch that selects
between two distinct enable mechanisms: a bank-based IRQ_ENABLE_BANK
register for HW < 3.2, and a per-pin enable bit in IRQ_i_CFG for
HW >= 3.2. These two paths share no code and serve different hardware.

Split them into two focused static functions: pdc_enable_intr_bank()
for HW < 3.2 and pdc_enable_intr_cfg() for HW >= 3.2. No functional
change.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260527095426.2324504-2-mukesh.ojha@oss.qualcomm.com
This commit is contained in:
Mukesh Ojha 2026-05-27 15:24:23 +05:30 committed by Thomas Gleixner
parent 6fe4500746
commit 668f338284
1 changed files with 25 additions and 16 deletions
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41
drivers/irqchip/qcom-pdc.c
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@ -97,28 +97,37 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)
pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable);
}
static void __pdc_enable_intr(int pin_out, bool on)
static void pdc_enable_intr_bank(int pin_out, bool on)
{
unsigned long enable;
u32 index, mask;
if (pdc_version < PDC_VERSION_3_2) {
u32 index, mask;
index = pin_out / 32;
mask = pin_out % 32;
index = pin_out / 32;
mask = pin_out % 32;
enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
__assign_bit(mask, &enable, on);
enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
__assign_bit(mask, &enable, on);
if (pdc_x1e_quirk)
pdc_x1e_irq_enable_write(index, enable);
else
pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
}
if (pdc_x1e_quirk)
pdc_x1e_irq_enable_write(index, enable);
else
pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
} else {
enable = pdc_reg_read(IRQ_i_CFG, pin_out);
__assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on);
pdc_reg_write(IRQ_i_CFG, pin_out, enable);
}
static void pdc_enable_intr_cfg(int pin_out, bool on)
{
unsigned long enable = pdc_reg_read(IRQ_i_CFG, pin_out);
__assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on);
pdc_reg_write(IRQ_i_CFG, pin_out, enable);
}
static void __pdc_enable_intr(int pin_out, bool on)
{
if (pdc_version < PDC_VERSION_3_2)
pdc_enable_intr_bank(pin_out, on);
else
pdc_enable_intr_cfg(pin_out, on);
}
static void pdc_enable_intr(struct irq_data *d, bool on)