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PCI: Update CXL DVSEC definitions
CXL DVSEC definitions were recently moved into uapi/pci_regs.h, but the newly added macros do not follow the file's existing naming conventions. The current format uses CXL_DVSEC_XYZ, while the new CXL entries must instead use the PCI_DVSEC_CXL_XYZ prefix to match the conventions already established in pci_regs.h. The new CXL DVSEC macros also introduce _MASK and _OFFSET suffixes, which are not used anywhere else in the file. These suffixes lengthen the identifiers and reduce readability. Remove _MASK and _OFFSET from the recently added definitions. Additionally, remove PCI_DVSEC_HEADER1_LENGTH, as it duplicates the existing PCI_DVSEC_HEADER1_LEN() macro. Update all existing references to use the new macro names. Finally, update the inline documentation to reference the latest revision of the CXL specification. Signed-off-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20260114182055.46029-3-terry.bowman@amd.com Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
This commit is contained in:
Terry Bowman
Dave Jiang
parent
0f7afd80d8
commit
6612bd9ff0
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@ -86,12 +86,12 @@ static int cxl_dvsec_mem_range_valid(struct cxl_dev_state *cxlds, int id)
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i = 1;
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do {
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rc = pci_read_config_dword(pdev,
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d + CXL_DVSEC_RANGE_SIZE_LOW(id),
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d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id),
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&temp);
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if (rc)
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return rc;
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valid = FIELD_GET(CXL_DVSEC_MEM_INFO_VALID, temp);
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valid = FIELD_GET(PCI_DVSEC_CXL_MEM_INFO_VALID, temp);
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if (valid)
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break;
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msleep(1000);
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@ -121,11 +121,11 @@ static int cxl_dvsec_mem_range_active(struct cxl_dev_state *cxlds, int id)
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/* Check MEM ACTIVE bit, up to 60s timeout by default */
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for (i = media_ready_timeout; i; i--) {
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(id), &temp);
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pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp);
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if (rc)
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return rc;
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active = FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp);
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active = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE, temp);
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if (active)
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break;
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msleep(1000);
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@ -154,11 +154,11 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds)
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u16 cap;
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rc = pci_read_config_word(pdev,
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d + CXL_DVSEC_CAP_OFFSET, &cap);
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d + PCI_DVSEC_CXL_CAP, &cap);
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if (rc)
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return rc;
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hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap);
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hdm_count = FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT, cap);
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for (i = 0; i < hdm_count; i++) {
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rc = cxl_dvsec_mem_range_valid(cxlds, i);
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if (rc)
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@ -186,16 +186,16 @@ static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val)
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u16 ctrl;
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int rc;
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rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
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rc = pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, &ctrl);
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if (rc < 0)
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return rc;
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if ((ctrl & CXL_DVSEC_MEM_ENABLE) == val)
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if ((ctrl & PCI_DVSEC_CXL_MEM_ENABLE) == val)
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return 1;
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ctrl &= ~CXL_DVSEC_MEM_ENABLE;
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ctrl &= ~PCI_DVSEC_CXL_MEM_ENABLE;
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ctrl |= val;
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rc = pci_write_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, ctrl);
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rc = pci_write_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, ctrl);
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if (rc < 0)
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return rc;
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@ -211,7 +211,7 @@ static int devm_cxl_enable_mem(struct device *host, struct cxl_dev_state *cxlds)
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{
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int rc;
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rc = cxl_set_mem_enable(cxlds, CXL_DVSEC_MEM_ENABLE);
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rc = cxl_set_mem_enable(cxlds, PCI_DVSEC_CXL_MEM_ENABLE);
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if (rc < 0)
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return rc;
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if (rc > 0)
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@ -273,11 +273,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
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return -ENXIO;
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}
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rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap);
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rc = pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CAP, &cap);
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if (rc)
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return rc;
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if (!(cap & CXL_DVSEC_MEM_CAPABLE)) {
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if (!(cap & PCI_DVSEC_CXL_MEM_CAPABLE)) {
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dev_dbg(dev, "Not MEM Capable\n");
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return -ENXIO;
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}
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@ -288,7 +288,7 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
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* driver is for a spec defined class code which must be CXL.mem
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* capable, there is no point in continuing to enable CXL.mem.
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*/
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hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap);
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hdm_count = FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT, cap);
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if (!hdm_count || hdm_count > 2)
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return -EINVAL;
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@ -297,11 +297,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
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* disabled, and they will remain moot after the HDM Decoder
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* capability is enabled.
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*/
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rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
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rc = pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, &ctrl);
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if (rc)
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return rc;
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info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
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info->mem_enabled = FIELD_GET(PCI_DVSEC_CXL_MEM_ENABLE, ctrl);
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if (!info->mem_enabled)
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return 0;
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@ -314,35 +314,35 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
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return rc;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp);
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pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i), &temp);
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if (rc)
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return rc;
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size = (u64)temp << 32;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp);
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pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(i), &temp);
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if (rc)
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return rc;
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size |= temp & CXL_DVSEC_MEM_SIZE_LOW_MASK;
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size |= temp & PCI_DVSEC_CXL_MEM_SIZE_LOW;
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if (!size) {
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continue;
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}
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp);
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pdev, d + PCI_DVSEC_CXL_RANGE_BASE_HIGH(i), &temp);
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if (rc)
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return rc;
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base = (u64)temp << 32;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp);
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pdev, d + PCI_DVSEC_CXL_RANGE_BASE_LOW(i), &temp);
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if (rc)
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return rc;
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base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK;
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base |= temp & PCI_DVSEC_CXL_MEM_BASE_LOW;
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info->dvsec_range[ranges++] = (struct range) {
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.start = base,
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@ -1068,7 +1068,7 @@ u16 cxl_gpf_get_dvsec(struct device *dev)
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is_port = false;
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dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
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is_port ? CXL_DVSEC_PORT_GPF : CXL_DVSEC_DEVICE_GPF);
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is_port ? PCI_DVSEC_CXL_PORT_GPF : PCI_DVSEC_CXL_DEVICE_GPF);
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if (!dvsec)
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dev_warn(dev, "%s GPF DVSEC not present\n",
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is_port ? "Port" : "Device");
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@ -1084,14 +1084,14 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
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switch (phase) {
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case 1:
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offset = CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET;
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base = CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK;
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scale = CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK;
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offset = PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL;
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base = PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE;
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scale = PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE;
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break;
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case 2:
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offset = CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET;
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base = CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK;
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scale = CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK;
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offset = PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL;
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base = PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE;
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scale = PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE;
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break;
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default:
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return -EINVAL;
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@ -271,10 +271,10 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, "CXL");
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static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_hi,
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struct cxl_register_map *map)
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{
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u8 reg_type = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo);
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int bar = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo);
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u8 reg_type = FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID, reg_lo);
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int bar = FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BIR, reg_lo);
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u64 offset = ((u64)reg_hi << 32) |
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(reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK);
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(reg_lo & PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW);
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if (offset > pci_resource_len(pdev, bar)) {
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dev_warn(&pdev->dev,
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@ -311,15 +311,15 @@ static int __cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_ty
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};
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regloc = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
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CXL_DVSEC_REG_LOCATOR);
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PCI_DVSEC_CXL_REG_LOCATOR);
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if (!regloc)
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return -ENXIO;
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pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size);
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regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size);
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regloc_size = PCI_DVSEC_HEADER1_LEN(regloc_size);
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regloc += CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET;
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regblocks = (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8;
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regloc += PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1;
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regblocks = (regloc_size - PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1) / 8;
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for (i = 0; i < regblocks; i++, regloc += 8) {
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u32 reg_lo, reg_hi;
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@ -933,7 +933,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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cxlds->rcd = is_cxl_restricted(pdev);
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cxlds->serial = pci_get_dsn(pdev);
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cxlds->cxl_dvsec = pci_find_dvsec_capability(
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pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
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pdev, PCI_VENDOR_ID_CXL, PCI_DVSEC_CXL_DEVICE);
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if (!cxlds->cxl_dvsec)
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dev_warn(&pdev->dev,
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"Device DVSEC not present, skip CXL.mem init\n");
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@ -1333,63 +1333,57 @@
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#define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE)
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#define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc))
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/* Compute Express Link (CXL r3.1, sec 8.1.5) */
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#define PCI_DVSEC_CXL_PORT 3
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#define PCI_DVSEC_CXL_PORT_CTL 0x0c
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#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
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/*
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* Compute Express Link (CXL r3.2, sec 8.1)
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* Compute Express Link (CXL r4.0, sec 8.1)
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*
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* Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state
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* is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these
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* is "disconnected" (CXL r4.0, sec 9.12.3). Re-enumerate these
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* registers on downstream link-up events.
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*/
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#define PCI_DVSEC_HEADER1_LENGTH_MASK __GENMASK(31, 20)
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/* CXL 3.2 8.1.3: PCIe DVSEC for CXL Device */
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#define CXL_DVSEC_PCIE_DEVICE 0
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#define CXL_DVSEC_CAP_OFFSET 0xA
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#define CXL_DVSEC_MEM_CAPABLE _BITUL(2)
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#define CXL_DVSEC_HDM_COUNT_MASK __GENMASK(5, 4)
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#define CXL_DVSEC_CTRL_OFFSET 0xC
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#define CXL_DVSEC_MEM_ENABLE _BITUL(2)
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#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
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#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
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#define CXL_DVSEC_MEM_INFO_VALID _BITUL(0)
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#define CXL_DVSEC_MEM_ACTIVE _BITUL(1)
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#define CXL_DVSEC_MEM_SIZE_LOW_MASK __GENMASK(31, 28)
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#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
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#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
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#define CXL_DVSEC_MEM_BASE_LOW_MASK __GENMASK(31, 28)
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/* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */
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#define PCI_DVSEC_CXL_DEVICE 0
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#define PCI_DVSEC_CXL_CAP 0xA
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#define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2)
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#define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4)
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#define PCI_DVSEC_CXL_CTRL 0xC
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#define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2)
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#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
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#define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
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#define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0)
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#define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1)
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#define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28)
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#define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
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#define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
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#define PCI_DVSEC_CXL_MEM_BASE_LOW __GENMASK(31, 28)
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#define CXL_DVSEC_RANGE_MAX 2
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/* CXL 3.2 8.1.4: Non-CXL Function Map DVSEC */
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#define CXL_DVSEC_FUNCTION_MAP 2
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/* CXL r4.0, 8.1.4: Non-CXL Function Map DVSEC */
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#define PCI_DVSEC_CXL_FUNCTION_MAP 2
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/* CXL 3.2 8.1.5: Extensions DVSEC for Ports */
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#define CXL_DVSEC_PORT 3
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#define CXL_DVSEC_PORT_CTL 0x0c
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#define CXL_DVSEC_PORT_CTL_UNMASK_SBR 0x00000001
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/* CXL r4.0, 8.1.5: Extensions DVSEC for Ports */
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#define PCI_DVSEC_CXL_PORT 3
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#define PCI_DVSEC_CXL_PORT_CTL 0x0c
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#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
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/* CXL 3.2 8.1.6: GPF DVSEC for CXL Port */
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#define CXL_DVSEC_PORT_GPF 4
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#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C
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#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK __GENMASK(3, 0)
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#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK __GENMASK(11, 8)
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#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE
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#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK __GENMASK(3, 0)
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#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK __GENMASK(11, 8)
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/* CXL r4.0, 8.1.6: GPF DVSEC for CXL Port */
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#define PCI_DVSEC_CXL_PORT_GPF 4
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#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL 0x0C
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#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE __GENMASK(3, 0)
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#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE __GENMASK(11, 8)
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#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL 0xE
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#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE __GENMASK(3, 0)
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#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE __GENMASK(11, 8)
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/* CXL 3.2 8.1.7: GPF DVSEC for CXL Device */
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#define CXL_DVSEC_DEVICE_GPF 5
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/* CXL r4.0, 8.1.7: GPF DVSEC for CXL Device */
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#define PCI_DVSEC_CXL_DEVICE_GPF 5
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/* CXL 3.2 8.1.9: Register Locator DVSEC */
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#define CXL_DVSEC_REG_LOCATOR 8
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#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
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#define CXL_DVSEC_REG_LOCATOR_BIR_MASK __GENMASK(2, 0)
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#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK __GENMASK(15, 8)
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#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK __GENMASK(31, 16)
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/* CXL r4.0, 8.1.9: Register Locator DVSEC */
|
||||
#define PCI_DVSEC_CXL_REG_LOCATOR 8
|
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#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1 0xC
|
||||
#define PCI_DVSEC_CXL_REG_LOCATOR_BIR __GENMASK(2, 0)
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#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID __GENMASK(15, 8)
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#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW __GENMASK(31, 16)
|
||||
|
||||
#endif /* LINUX_PCI_REGS_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user