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Merge branch 'icc-kuno' into icc-next

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Add interconnect (NoC) provider driver for the Qualcomm Kuno SoC.

* icc-kuno
  dt-bindings: interconnect: Add Qualcomm Kuno NoC
  interconnect: qcom: Add Kuno interconnect provider driver

Link: https://patch.msgid.link/20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov 2026-09-16 19:36:26 +03:00
commit 65ec39aad4
5 changed files with 1210 additions and 0 deletions
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118
Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml Normal file
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@ -0,0 +1,118 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,kuno-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on Kuno SoC
maintainers:
- Hardeep Sharma <hardeep.sharma@oss.qualcomm.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also: include/dt-bindings/interconnect/qcom,kuno.h
properties:
compatible:
enum:
- qcom,kuno-aggre-noc
- qcom,kuno-clk-virt
- qcom,kuno-cnoc-main
- qcom,kuno-dc-noc
- qcom,kuno-mc-virt
- qcom,kuno-mem-noc
- qcom,kuno-pcie-anoc
- qcom,kuno-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,kuno-clk-virt
- qcom,kuno-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
const: qcom,kuno-aggre-noc
then:
properties:
clocks:
items:
- description: System NoC USB SF AXI clock
- description: IPA clock
- if:
properties:
compatible:
contains:
const: qcom,kuno-system-noc
then:
properties:
clocks:
items:
- description: IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,kuno-aggre-noc
- qcom,kuno-system-noc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,kuno-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
clk_virt: interconnect-0 {
compatible = "qcom,kuno-clk-virt";
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre_noc: interconnect@1640000 {
compatible = "qcom,kuno-aggre-noc";
reg = <0x01640000 0x33400>;
clocks = <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
...

13
drivers/interconnect/qcom/Kconfig
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@ -53,6 +53,19 @@ config INTERCONNECT_QCOM_KAANAPALI
This is a driver for the Qualcomm Network-on-Chip on kaanapali-based
platforms.
config INTERCONNECT_QCOM_KUNO
tristate "Qualcomm Kuno interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
depends on ARM || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on kuno-based
platforms. The interconnect provider collects and aggregates the
consumer bandwidth requests to satisfy constraints placed on the
Network-on-Chip performance states.
config INTERCONNECT_QCOM_MAILI
tristate "Qualcomm MAILI interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

2
drivers/interconnect/qcom/Makefile
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@ -8,6 +8,7 @@ qnoc-eliza-objs := eliza.o
qnoc-glymur-objs := glymur.o
qnoc-hawi-objs := hawi.o
qnoc-kaanapali-objs := kaanapali.o
qnoc-kuno-objs := kuno.o
qnoc-maili-objs := maili.o
qnoc-milos-objs := milos.o
qnoc-msm8909-objs := msm8909.o
@ -57,6 +58,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) += qnoc-eliza.o
obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o
obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) += qnoc-hawi.o
obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o
obj-$(CONFIG_INTERCONNECT_QCOM_KUNO) += qnoc-kuno.o
obj-$(CONFIG_INTERCONNECT_QCOM_MAILI) += qnoc-maili.o
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o

988
drivers/interconnect/qcom/kuno.c Normal file
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@ -0,0 +1,988 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/interconnect/qcom,kuno.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ahb2_phy = {
.name = "qhs_ahb2_phy",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_mxa = {
.name = "qhs_cpr_mxa",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_mxc = {
.name = "qhs_cpr_mxc",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_crypto_cfg = {
.name = "qhs_crypto_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_emac0_cfg = {
.name = "qhs_emac0_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie_rscc = {
.name = "qhs_pcie_rscc",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
.name = "qhs_pmu_wrapper_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qss_anoc_throttle_cfg = {
.name = "qss_anoc_throttle_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qhs_lagg = {
.name = "qhs_lagg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mccc_master = {
.name = "qhs_mccc_master",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node srvc_memnoc = {
.name = "srvc_memnoc",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qup0_core_slave },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
.channels = 1,
.buswidth = 4,
.num_links = 2,
.link_nodes = { &qhs_lagg, &qhs_mccc_master },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &ebi },
};
static struct qcom_icc_node qnm_memnoc_cfg = {
.name = "qnm_memnoc_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &srvc_memnoc },
};
static struct qcom_icc_node qnm_memnoc_pcie = {
.name = "qnm_memnoc_pcie",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &xs_pcie_0 },
};
static struct qcom_icc_node xm_ipa2pcie = {
.name = "xm_ipa2pcie",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &xs_pcie_0 },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qnm_cnoc },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = { &llcc_mc },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_memnoc_pcie },
};
static struct qcom_icc_node qhm_pcie_rscc = {
.name = "qhm_pcie_rscc",
.channels = 1,
.buswidth = 4,
.num_links = 34,
.link_nodes = { &qhs_ahb2_phy, &qhs_aoss,
&qhs_apss, &qhs_audio,
&qhs_clk_ctl, &qhs_cpr_cx,
&qhs_cpr_mxa, &qhs_cpr_mxc,
&qhs_crypto_cfg, &qhs_emac0_cfg,
&qhs_imem_cfg, &qhs_ipa,
&qhs_ipc_router, &qhs_mss_cfg,
&qhs_pcie0_cfg, &qhs_pdm,
&qhs_pmu_wrapper_cfg, &qhs_prng,
&qhs_qdss_cfg, &qhs_qpic,
&qhs_qup0, &qhs_sdc4,
&qhs_spmi_vgi_coex, &qhs_tcsr,
&qhs_tlmm, &qhs_tme_cfg,
&qhs_usb3, &qhs_vsense_ctrl_cfg,
&qns_ddrss_cfg, &qss_anoc_throttle_cfg,
&qxs_boot_imem, &qxs_imem,
&xs_qdss_stm, &xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_memnoc_cnoc = {
.name = "qnm_memnoc_cnoc",
.channels = 1,
.buswidth = 8,
.num_links = 35,
.link_nodes = { &qhs_ahb2_phy, &qhs_aoss,
&qhs_apss, &qhs_audio,
&qhs_clk_ctl, &qhs_cpr_cx,
&qhs_cpr_mxa, &qhs_cpr_mxc,
&qhs_crypto_cfg, &qhs_emac0_cfg,
&qhs_imem_cfg, &qhs_ipa,
&qhs_ipc_router, &qhs_mss_cfg,
&qhs_pcie0_cfg, &qhs_pcie_rscc,
&qhs_pdm, &qhs_pmu_wrapper_cfg,
&qhs_prng, &qhs_qdss_cfg,
&qhs_qpic, &qhs_qup0,
&qhs_sdc4, &qhs_spmi_vgi_coex,
&qhs_tcsr, &qhs_tlmm,
&qhs_tme_cfg, &qhs_usb3,
&qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
&qss_anoc_throttle_cfg, &qxs_boot_imem,
&qxs_imem, &xs_qdss_stm,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_node qns_memnoc_cnoc = {
.name = "qns_memnoc_cnoc",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_memnoc_cnoc },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
.channels = 1,
.buswidth = 8,
.num_links = 3,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc,
&qns_pcie },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc },
};
static struct qcom_icc_node xm_apps0 = {
.name = "xm_apps0",
.channels = 1,
.buswidth = 16,
.num_links = 3,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc,
&qns_pcie },
};
static struct qcom_icc_node qns_pcie_memnoc = {
.name = "qns_pcie_memnoc",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_pcie },
};
static struct qcom_icc_node qns_memnoc_sf = {
.name = "qns_memnoc_sf",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_snoc_sf },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_pcie_memnoc },
};
static struct qcom_icc_node qhm_cpucp = {
.name = "qhm_cpucp",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_memnoc_sf },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_memnoc_sf, &xs_pcie_0 },
};
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
.channels = 1,
.buswidth = 4,
.num_links = 2,
.link_nodes = { &qns_memnoc_sf, &xs_pcie_0 },
};
static struct qcom_icc_node qxm_mss_nav_ce = {
.name = "qxm_mss_nav_ce",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_memnoc_sf, &xs_pcie_0 },
};
static struct qcom_icc_node qxm_tme = {
.name = "qxm_tme",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_memnoc_sf, &xs_pcie_0 },
};
static struct qcom_icc_node qns_a1noc = {
.name = "qns_a1noc",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_aggre_noc },
};
static struct qcom_icc_node qns_snoc_datapath = {
.name = "qns_snoc_datapath",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qnm_cnoc_datapath },
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_qdss_etr0 = {
.name = "xm_qdss_etr0",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_qdss_etr1 = {
.name = "xm_qdss_etr1",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
.channels = 1,
.buswidth = 8,
.num_links = 36,
.link_nodes = { &qhs_ahb2_phy, &qhs_aoss,
&qhs_apss, &qhs_audio,
&qhs_clk_ctl, &qhs_cpr_cx,
&qhs_cpr_mxa, &qhs_cpr_mxc,
&qhs_crypto_cfg, &qhs_emac0_cfg,
&qhs_imem_cfg, &qhs_ipa,
&qhs_ipc_router, &qhs_mss_cfg,
&qhs_pcie0_cfg, &qhs_pcie_rscc,
&qhs_pdm, &qhs_pmu_wrapper_cfg,
&qhs_prng, &qhs_qdss_cfg,
&qhs_qpic, &qhs_qup0,
&qhs_sdc4, &qhs_spmi_vgi_coex,
&qhs_tcsr, &qhs_tlmm,
&qhs_tme_cfg, &qhs_usb3,
&qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
&qns_snoc_datapath, &qss_anoc_throttle_cfg,
&qxs_boot_imem, &qxs_imem,
&xs_qdss_stm, &xs_sys_tcu_cfg },
};
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = 0x8,
.num_nodes = 1,
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.num_nodes = 1,
.nodes = { &qxm_crypto },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
.enable_mask = 0x1,
.num_nodes = 39,
.nodes = { &qhm_pcie_rscc, &qnm_memnoc_cnoc,
&xm_qdss_dap, &qhs_ahb2_phy,
&qhs_aoss, &qhs_apss,
&qhs_audio, &qhs_clk_ctl,
&qhs_cpr_cx, &qhs_cpr_mxa,
&qhs_cpr_mxc, &qhs_crypto_cfg,
&qhs_emac0_cfg, &qhs_imem_cfg,
&qhs_ipa, &qhs_ipc_router,
&qhs_mss_cfg, &qhs_pcie0_cfg,
&qhs_pcie_rscc, &qhs_pdm,
&qhs_pmu_wrapper_cfg, &qhs_prng,
&qhs_qdss_cfg, &qhs_qpic,
&qhs_qup0, &qhs_sdc4,
&qhs_spmi_vgi_coex, &qhs_tcsr,
&qhs_tlmm, &qhs_tme_cfg,
&qhs_usb3, &qhs_vsense_ctrl_cfg,
&qns_ddrss_cfg, &qns_snoc_datapath,
&qss_anoc_throttle_cfg, &qxs_boot_imem,
&qxs_imem, &xs_qdss_stm,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.vote_scale = 1,
.num_nodes = 1,
.nodes = { &qup0_core_slave },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_llcc },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qns_memnoc_cnoc, &qns_pcie },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_memnoc_sf },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &xm_pcie3_0 },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.num_nodes = 2,
.nodes = { &qns_a1noc, &qnm_aggre_noc },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.num_nodes = 1,
.nodes = { &qxm_mss_nav_ce },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.num_nodes = 1,
.nodes = { &xs_pcie_0 },
};
static struct qcom_icc_bcm * const aggre_noc_bcms[] = {
&bcm_ce0,
};
static struct qcom_icc_node * const aggre_noc_nodes[] = {
[MASTER_AUDIO] = &qhm_audio,
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
[MASTER_QPIC] = &qhm_qpic,
[MASTER_QUP_0] = &qhm_qup0,
[MASTER_CRYPTO] = &qxm_crypto,
[MASTER_IPA] = &qxm_ipa,
[MASTER_EMAC] = &xm_emac_0,
[MASTER_QDSS_ETR] = &xm_qdss_etr0,
[MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
[MASTER_SDCC_4] = &xm_sdc4,
[MASTER_USB3_0] = &xm_usb3,
[SLAVE_A1NOC_CFG] = &qns_a1noc,
};
static const struct qcom_icc_desc kuno_aggre_noc = {
.nodes = aggre_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre_noc_nodes),
.bcms = aggre_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre_noc_bcms),
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
&bcm_qup0,
};
static struct qcom_icc_node * const clk_virt_nodes[] = {
[MASTER_QUP_CORE_0] = &qup0_core_master,
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
};
static const struct qcom_icc_desc kuno_clk_virt = {
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
};
static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
&bcm_cn0,
};
static struct qcom_icc_node * const cnoc_main_nodes[] = {
[MASTER_PCIE_RSCC] = &qhm_pcie_rscc,
[MASTER_GEM_NOC_CNOC] = &qnm_memnoc_cnoc,
[MASTER_QDSS_DAP] = &xm_qdss_dap,
[SLAVE_AHB2PHY] = &qhs_ahb2_phy,
[SLAVE_AOSS] = &qhs_aoss,
[SLAVE_APPSS] = &qhs_apss,
[SLAVE_AUDIO] = &qhs_audio,
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
[SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
[SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
[SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
[SLAVE_IPA_CFG] = &qhs_ipa,
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
[SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc,
[SLAVE_PDM] = &qhs_pdm,
[SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
[SLAVE_PRNG] = &qhs_prng,
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
[SLAVE_QPIC] = &qhs_qpic,
[SLAVE_QUP_0] = &qhs_qup0,
[SLAVE_SDCC_4] = &qhs_sdc4,
[SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
[SLAVE_TCSR] = &qhs_tcsr,
[SLAVE_TLMM] = &qhs_tlmm,
[SLAVE_TME_CFG] = &qhs_tme_cfg,
[SLAVE_USB3] = &qhs_usb3,
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
[SLAVE_SNOC_CNOC] = &qns_snoc_datapath,
[SLAVE_ANOC_THROTTLE_CFG] = &qss_anoc_throttle_cfg,
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
[SLAVE_IMEM] = &qxs_imem,
[SLAVE_QDSS_STM] = &xs_qdss_stm,
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
static const struct qcom_icc_desc kuno_cnoc_main = {
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
};
static struct qcom_icc_node * const dc_noc_nodes[] = {
[MASTER_CNOC_DC_NOC] = &qnm_cnoc,
[SLAVE_LAGG_CFG] = &qhs_lagg,
[SLAVE_MCCC_MASTER] = &qhs_mccc_master,
};
static const struct qcom_icc_desc kuno_dc_noc = {
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
};
static struct qcom_icc_node * const mc_virt_nodes[] = {
[MASTER_LLCC] = &llcc_mc,
[SLAVE_EBI1] = &ebi,
};
static const struct qcom_icc_desc kuno_mc_virt = {
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
};
static struct qcom_icc_bcm * const mem_noc_bcms[] = {
&bcm_sh0,
&bcm_sh1,
};
static struct qcom_icc_node * const mem_noc_nodes[] = {
[MASTER_SYS_TCU] = &alm_sys_tcu,
[MASTER_MSS_PROC] = &qnm_mdsp,
[MASTER_GEM_NOC_CFG] = &qnm_memnoc_cfg,
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
[MASTER_APPSS_PROC] = &xm_apps0,
[SLAVE_LLCC] = &qns_llcc,
[SLAVE_GEM_NOC_CNOC] = &qns_memnoc_cnoc,
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
[SLAVE_SERVICE_GEM_NOC] = &srvc_memnoc,
};
static const struct qcom_icc_desc kuno_mem_noc = {
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
.num_bcms = ARRAY_SIZE(mem_noc_bcms),
};
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
&bcm_sn1,
};
static struct qcom_icc_node * const pcie_anoc_nodes[] = {
[MASTER_PCIE_0] = &xm_pcie3_0,
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_memnoc,
};
static const struct qcom_icc_desc kuno_pcie_anoc = {
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
&bcm_sn0,
&bcm_sn2,
&bcm_sn4,
&bcm_sn7,
};
static struct qcom_icc_node * const system_noc_nodes[] = {
[MASTER_CPUCP] = &qhm_cpucp,
[MASTER_ANOC_SNOC] = &qnm_aggre_noc,
[MASTER_CNOC_SNOC] = &qnm_cnoc_datapath,
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
[MASTER_MSS_NAV] = &qxm_mss_nav_ce,
[MASTER_TME] = &qxm_tme,
[MASTER_IPA_PCIE] = &xm_ipa2pcie,
[SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
[SLAVE_PCIE_0] = &xs_pcie_0,
};
static const struct qcom_icc_desc kuno_system_noc = {
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,kuno-aggre-noc", .data = &kuno_aggre_noc },
{ .compatible = "qcom,kuno-clk-virt", .data = &kuno_clk_virt },
{ .compatible = "qcom,kuno-cnoc-main", .data = &kuno_cnoc_main },
{ .compatible = "qcom,kuno-dc-noc", .data = &kuno_dc_noc },
{ .compatible = "qcom,kuno-mc-virt", .data = &kuno_mc_virt },
{ .compatible = "qcom,kuno-mem-noc", .data = &kuno_mem_noc },
{ .compatible = "qcom,kuno-pcie-anoc", .data = &kuno_pcie_anoc },
{ .compatible = "qcom,kuno-system-noc", .data = &kuno_system_noc },
{ }
};
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
.probe = qcom_icc_rpmh_probe,
.remove = qcom_icc_rpmh_remove,
.driver = {
.name = "qnoc-kuno",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
static int __init qnoc_driver_init(void)
{
return platform_driver_register(&qnoc_driver);
}
core_initcall(qnoc_driver_init);
static void __exit qnoc_driver_exit(void)
{
platform_driver_unregister(&qnoc_driver);
}
module_exit(qnoc_driver_exit);
MODULE_DESCRIPTION("Kuno NoC driver");
MODULE_LICENSE("GPL");

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include/dt-bindings/interconnect/qcom,kuno.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H
#define MASTER_SYS_TCU 0
#define MASTER_LLCC 1
#define MASTER_AUDIO 2
#define MASTER_CPUCP 3
#define MASTER_PCIE_RSCC 4
#define MASTER_QDSS_BAM 5
#define MASTER_QPIC 6
#define MASTER_QUP_0 7
#define MASTER_ANOC_SNOC 8
#define MASTER_CNOC_DC_NOC 9
#define MASTER_CNOC_SNOC 10
#define MASTER_MSS_PROC 11
#define MASTER_GEM_NOC_CFG 12
#define MASTER_GEM_NOC_CNOC 13
#define MASTER_GEM_NOC_PCIE_SNOC 14
#define MASTER_ANOC_PCIE_GEM_NOC 15
#define MASTER_SNOC_SF_MEM_NOC 16
#define MASTER_QUP_CORE_0 17
#define MASTER_CRYPTO 18
#define MASTER_IPA 19
#define MASTER_MSS_NAV 20
#define MASTER_TME 21
#define MASTER_APPSS_PROC 22
#define MASTER_EMAC 23
#define MASTER_IPA_PCIE 24
#define MASTER_PCIE_0 25
#define MASTER_QDSS_DAP 26
#define MASTER_QDSS_ETR 27
#define MASTER_QDSS_ETR_1 28
#define MASTER_SDCC_4 29
#define MASTER_USB3_0 30
#define SLAVE_EBI1 31
#define SLAVE_AHB2PHY 32
#define SLAVE_AOSS 33
#define SLAVE_APPSS 34
#define SLAVE_AUDIO 35
#define SLAVE_CLK_CTL 36
#define SLAVE_RBCPR_CX_CFG 37
#define SLAVE_RBCPR_MXA_CFG 38
#define SLAVE_RBCPR_MXC_CFG 39
#define SLAVE_CRYPTO_0_CFG 40
#define SLAVE_EMAC_CFG 41
#define SLAVE_IMEM_CFG 42
#define SLAVE_IPA_CFG 43
#define SLAVE_IPC_ROUTER_CFG 44
#define SLAVE_LAGG_CFG 45
#define SLAVE_MCCC_MASTER 46
#define SLAVE_CNOC_MSS 47
#define SLAVE_PCIE_0_CFG 48
#define SLAVE_PCIE_RSC_CFG 49
#define SLAVE_PDM 50
#define SLAVE_PMU_WRAPPER_CFG 51
#define SLAVE_PRNG 52
#define SLAVE_QDSS_CFG 53
#define SLAVE_QPIC 54
#define SLAVE_QUP_0 55
#define SLAVE_SDCC_4 56
#define SLAVE_SPMI_VGI_COEX 57
#define SLAVE_TCSR 58
#define SLAVE_TLMM 59
#define SLAVE_TME_CFG 60
#define SLAVE_USB3 61
#define SLAVE_VSENSE_CTRL_CFG 62
#define SLAVE_A1NOC_CFG 63
#define SLAVE_DDRSS_CFG 64
#define SLAVE_LLCC 65
#define SLAVE_GEM_NOC_CNOC 66
#define SLAVE_SNOC_MEM_NOC_SF 67
#define SLAVE_MEM_NOC_PCIE_SNOC 68
#define SLAVE_ANOC_PCIE_GEM_NOC 69
#define SLAVE_SNOC_CNOC 70
#define SLAVE_ANOC_THROTTLE_CFG 71
#define SLAVE_QUP_CORE_0 72
#define SLAVE_BOOT_IMEM 73
#define SLAVE_IMEM 74
#define SLAVE_SERVICE_GEM_NOC 75
#define SLAVE_PCIE_0 76
#define SLAVE_QDSS_STM 77
#define SLAVE_TCU 78
#endif