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riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones

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Add temperature sensor and thermal-zones support for
the StarFive JH7100 SoC.

Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Hal Feng 2023-07-18 11:49:35 +08:00 committed by Conor Dooley
parent 0104340a67
commit 65e4a0f33a
1 changed files with 37 additions and 0 deletions
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37
arch/riscv/boot/dts/starfive/jh7100.dtsi
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@ -80,6 +80,31 @@ core1 {
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <15000>;
thermal-sensors = <&sfctemp>;
trips {
cpu_alert0 {
/* milliCelsius */
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit {
/* milliCelsius */
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
osc_sys: osc_sys {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -248,5 +273,17 @@ watchdog@12480000 {
resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
<&rstgen JH7100_RSTN_WDT>;
};
sfctemp: temperature-sensor@124a0000 {
compatible = "starfive,jh7100-temp";
reg = <0x0 0x124a0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
<&clkgen JH7100_CLK_TEMP_APB>;
clock-names = "sense", "bus";
resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
<&rstgen JH7100_RSTN_TEMP_APB>;
reset-names = "sense", "bus";
#thermal-sensor-cells = <0>;
};
};
};