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arm64: dts: qcom: sm8450: add display clock controller

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Add device node for display clock controller on Qualcomm SM8450 platform

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908222850.3552050-5-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2022-09-09 01:28:50 +03:00 committed by Bjorn Andersson
parent c95243eeae
commit 65b35e04d2
1 changed files with 28 additions and 0 deletions
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28
arch/arm64/boot/dts/qcom/sm8450.dtsi
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@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-camcc.h>
#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@ -2400,6 +2401,33 @@ camcc: clock-controller@ade0000 {
status = "disabled";
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sm8450-dispcc";
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<0>, /* dsi0 */
<0>,
<0>, /* dsi1 */
<0>,
<0>, /* dp0 */
<0>,
<0>, /* dp1 */
<0>,
<0>, /* dp2 */
<0>,
<0>, /* dp3 */
<0>;
power-domains = <&rpmhpd SM8450_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
status = "disabled";
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8450-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;