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drm/amdgpu/gfx12.1: replace BUG_ON() with WARN_ON()
There's no need to crash the kernel for these cases. Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit e4d99e04b2e9b13b97d3b17804c735f62689db23) Cc: stable@vger.kernel.org
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@ -248,7 +248,7 @@ static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
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PACKET3_WAIT_REG_MEM__FUNCTION(3))); /* equal */
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if (mem_space)
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BUG_ON(addr0 & 0x3); /* Dword align */
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WARN_ON(addr0 & 0x3); /* Dword align */
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amdgpu_ring_write(ring, addr0);
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amdgpu_ring_write(ring, addr1);
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amdgpu_ring_write(ring, ref);
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@ -3433,7 +3433,7 @@ static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring,
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}
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amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
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WARN_ON(ib->gpu_addr & 0x3); /* Dword align */
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amdgpu_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 0) |
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@ -3466,9 +3466,9 @@ static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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* aligned if only send 32bit data low (discard data high)
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*/
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if (write64bit)
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BUG_ON(addr & 0x7);
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WARN_ON(addr & 0x7);
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else
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BUG_ON(addr & 0x3);
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WARN_ON(addr & 0x3);
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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amdgpu_ring_write(ring, lower_32_bits(seq));
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@ -3515,9 +3515,6 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
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{
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struct amdgpu_device *adev = ring->adev;
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/* we only allocate 32bit for each seq wb address */
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BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
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/* write fence seq to the "addr" */
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1)));
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