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drm/i915/vrr: Readout framestart_delay earlier
In order to pretend that ICL/TGL VRR hardware has a similar guardband as on ADL+ we'll need access to framestart_delay already during intel_vrr_get_config(). Hoist the framestart_delay to an earlier point to make that possible. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250917203446.14374-3-ville.syrjala@linux.intel.com Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
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@ -3891,6 +3891,15 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
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intel_joiner_get_config(pipe_config);
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intel_dsc_get_config(pipe_config);
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if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
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tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
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pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
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} else {
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/* no idea if this is correct */
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pipe_config->framestart_delay = 1;
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}
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if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
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DISPLAY_VER(display) >= 11)
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intel_get_transcoder_timings(crtc, pipe_config);
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@ -3942,15 +3951,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
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pipe_config->pixel_multiplier = 1;
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}
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if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
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tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
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pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
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} else {
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/* no idea if this is correct */
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pipe_config->framestart_delay = 1;
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}
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out:
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intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);
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