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drm/i915/xe2lpd: Add fake PCH
Xe2_LPD doesn't have south display engine on a PCH, it's actually on the SoC die (while north display engine is on compute die). As such it makes no sense to go through the PCI devices looking for an ISA bridge. The approach used by BXT/GLK can't be used here since leaving it with PCH_NONE would mean taking the wrong code paths. For the places we currently use a PCH check, it's enough for now to just check the north display version. Use that to define a fake PCH to be used across the driver. Eventually these PCH checks may need to be re-designed as this is already the third platform using/needing a fake PCH. v2: Match on display IP version rather than on platform (Matt Roper) v3: Extend and clarify commit message (Matt Roper / Ville) Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-6-lucas.demarchi@intel.com
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@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
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* South display engine on the same PCI device: just assign the fake
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* PCH.
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*/
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if (IS_DG2(dev_priv)) {
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if (DISPLAY_VER(dev_priv) >= 20) {
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dev_priv->pch_type = PCH_LNL;
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return;
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} else if (IS_DG2(dev_priv)) {
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dev_priv->pch_type = PCH_DG2;
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return;
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} else if (IS_DG1(dev_priv)) {
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@ -30,6 +30,7 @@ enum intel_pch {
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/* Fake PCHs, functionality handled on the same PCI dev */
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PCH_DG1 = 1024,
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PCH_DG2,
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PCH_LNL,
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};
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#define INTEL_PCH_DEVICE_ID_MASK 0xff80
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@ -66,6 +67,7 @@ enum intel_pch {
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#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
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#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
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#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
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#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
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#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
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#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
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