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Delete some obsolete networking code

Browse Source 
Old code like amateur radio and NFC have long been a burden
 to core networking developers. syzbot loves to find bugs
 in BKL-era code, and noobs try to fix them.
 
 If we want to have a fighting chance of surviving the LLM-pocalypse
 this code needs to find a dedicated owner or get deleted.
 We've talked about these deletions multiple times in the past
 and every time someone wanted the code to stay. It is never
 very clear to me how many of those people actually use the code
 vs are just nostalgic to see it go. Amateur radio did have
 occasional users (or so I think) but most users switched
 to user space implementations since its all super slow stuff.
 Nobody stepped up to maintain the kernel code.
 
 We were lucky enough to find someone who wants to help with NFC
 so we're giving that a chance. Let's try to put the rest of
 this code behind us.
 
 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Merge tag 'net-deletions' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next

Pull networking deletions from Jakub Kicinski:
 "Delete some obsolete networking code

  Old code like amateur radio and NFC have long been a burden to core
  networking developers. syzbot loves to find bugs in BKL-era code, and
  noobs try to fix them.

  If we want to have a fighting chance of surviving the LLM-pocalypse
  this code needs to find a dedicated owner or get deleted. We've talked
  about these deletions multiple times in the past and every time
  someone wanted the code to stay. It is never very clear to me how many
  of those people actually use the code vs are just nostalgic to see it
  go. Amateur radio did have occasional users (or so I think) but most
  users switched to user space implementations since its all super slow
  stuff. Nobody stepped up to maintain the kernel code.

  We were lucky enough to find someone who wants to help with NFC so
  we're giving that a chance. Let's try to put the rest of this code
  behind us"

* tag 'net-deletions' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next:
  drivers: net: 8390: wd80x3: Remove this driver
  drivers: net: 8390: ultra: Remove this driver
  drivers: net: 8390: AX88190: Remove this driver
  drivers: net: fujitsu: fmvj18x: Remove this driver
  drivers: net: smsc: smc91c92: Remove this driver
  drivers: net: smsc: smc9194: Remove this driver
  drivers: net: amd: nmclan: Remove this driver
  drivers: net: amd: lance: Remove this driver
  drivers: net: 3com: 3c589: Remove this driver
  drivers: net: 3com: 3c574: Remove this driver
  drivers: net: 3com: 3c515: Remove this driver
  drivers: net: 3com: 3c509: Remove this driver
  net: packetengines: remove obsolete yellowfin driver and vendor dir
  net: packetengines: remove obsolete hamachi driver
  net: remove unused ATM protocols and legacy ATM device drivers
  net: remove ax25 and amateur radio (hamradio) subsystem
  net: remove ISDN subsystem and Bluetooth CMTP
  caif: remove CAIF NETWORK LAYER
This commit is contained in:
Linus Torvalds 2026-04-24 09:41:58 -07:00
commit 64edfa6506
311 changed files with 14 additions and 138161 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
CREDITS
View File

@ -3652,6 +3652,11 @@ S: Dag Hammerskjolds v. 3E
S: S-226 64 LUND
S: Sweden
N: Tilman Schmidt
E: tilman@imap.cc
D: Siemens Gigaset ISDN driver author and maintainer
D: ISDN CAPI subsystem contributions
N: Henning P. Schmiedehausen
E: hps@tanstaafl.de
D: added PCI support to the serial driver

6
Documentation/.renames.txt
View File

@ -783,11 +783,9 @@ namespaces/compatibility-list admin-guide/namespaces/compatibility-list
namespaces/index admin-guide/namespaces/index
namespaces/resource-control admin-guide/namespaces/resource-control
networking/altera_tse networking/device_drivers/ethernet/altera/altera_tse
networking/baycom networking/device_drivers/hamradio/baycom
networking/bpf_flow_dissector bpf/prog_flow_dissector
networking/cxacru networking/device_drivers/atm/cxacru
networking/defza networking/device_drivers/fddi/defza
networking/device_drivers/3com/3c509 networking/device_drivers/ethernet/3com/3c509
networking/device_drivers/3com/vortex networking/device_drivers/ethernet/3com/vortex
networking/device_drivers/amazon/ena networking/device_drivers/ethernet/amazon/ena
networking/device_drivers/aquantia/atlantic networking/device_drivers/ethernet/aquantia/atlantic
@ -822,7 +820,6 @@ networking/device_drivers/microsoft/netvsc networking/device_drivers/ethernet/mi
networking/device_drivers/netronome/nfp networking/device_drivers/ethernet/netronome/nfp
networking/device_drivers/pensando/ionic networking/device_drivers/ethernet/pensando/ionic
networking/device_drivers/qualcomm/rmnet networking/device_drivers/cellular/qualcomm/rmnet
networking/device_drivers/smsc/smc9 networking/device_drivers/ethernet/smsc/smc9
networking/device_drivers/stmicro/stmmac networking/device_drivers/ethernet/stmicro/stmmac
networking/device_drivers/ti/cpsw networking/device_drivers/ethernet/ti/cpsw
networking/device_drivers/ti/cpsw_switchdev networking/device_drivers/ethernet/ti/cpsw_switchdev
@ -836,19 +833,16 @@ networking/e100 networking/device_drivers/ethernet/intel/e100
networking/e1000 networking/device_drivers/ethernet/intel/e1000
networking/e1000e networking/device_drivers/ethernet/intel/e1000e
networking/fm10k networking/device_drivers/ethernet/intel/fm10k
networking/fore200e networking/device_drivers/atm/fore200e
networking/hinic networking/device_drivers/ethernet/huawei/hinic
networking/i40e networking/device_drivers/ethernet/intel/i40e
networking/iavf networking/device_drivers/ethernet/intel/iavf
networking/ice networking/device_drivers/ethernet/intel/ice
networking/igb networking/device_drivers/ethernet/intel/igb
networking/igbvf networking/device_drivers/ethernet/intel/igbvf
networking/iphase networking/device_drivers/atm/iphase
networking/ixgbe networking/device_drivers/ethernet/intel/ixgbe
networking/ixgbevf networking/device_drivers/ethernet/intel/ixgbevf
networking/netdev-FAQ process/maintainer-netdev
networking/skfp networking/device_drivers/fddi/skfp
networking/z8530drv networking/device_drivers/hamradio/z8530drv
nfc/index driver-api/nfc/index
nfc/nfc-hci driver-api/nfc/nfc-hci
nfc/nfc-pn544 driver-api/nfc/nfc-pn544

18
Documentation/admin-guide/kernel-parameters.txt
View File

@ -6,7 +6,6 @@
APPARMOR AppArmor support is enabled.
ARM ARM architecture is enabled.
ARM64 ARM64 architecture is enabled.
AX25 Appropriate AX.25 support is enabled.
CLK Common clock infrastructure is enabled.
CMA Contiguous Memory Area support is enabled.
DRM Direct Rendering Management support is enabled.
@ -633,23 +632,6 @@ Kernel parameters
1 - Enable the BAU.
unset - Disable the BAU.
baycom_epp= [HW,AX25]
Format: <io>,<mode>
baycom_par= [HW,AX25] BayCom Parallel Port AX.25 Modem
Format: <io>,<mode>
See header of drivers/net/hamradio/baycom_par.c.
baycom_ser_fdx= [HW,AX25]
BayCom Serial Port AX.25 Modem (Full Duplex Mode)
Format: <io>,<irq>,<mode>[,<baud>]
See header of drivers/net/hamradio/baycom_ser_fdx.c.
baycom_ser_hdx= [HW,AX25]
BayCom Serial Port AX.25 Modem (Half Duplex Mode)
Format: <io>,<irq>,<mode>
See header of drivers/net/hamradio/baycom_ser_hdx.c.
bdev_allow_write_mounted=
Format: <bool>
Control the ability to open a mounted block device

73
Documentation/isdn/credits.rst
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@ -1,73 +0,0 @@
=======
Credits
=======
I want to thank all who contributed to this project and especially to:
(in alphabetical order)
Thomas Bogendörfer (tsbogend@bigbug.franken.de)
Tester, lots of bugfixes and hints.
Alan Cox (alan@lxorguk.ukuu.org.uk)
For help getting into standard-kernel.
Henner Eisen (eis@baty.hanse.de)
For X.25 implementation.
Volker Götz (volker@oops.franken.de)
For contribution of man-pages, the imontty-tool and a perfect
maintaining of the mailing-list at hub-wue.
Matthias Hessler (hessler@isdn4linux.de)
For creating and maintaining the FAQ.
Bernhard Hailer (Bernhard.Hailer@lrz.uni-muenchen.de)
For creating the FAQ, and the leafsite HOWTO.
Michael 'Ghandi' Herold (michael@abadonna.franken.de)
For contribution of the vbox answering machine.
Michael Hipp (Michael.Hipp@student.uni-tuebingen.de)
For his Sync-PPP-code.
Karsten Keil (keil@isdn4linux.de)
For adding 1TR6-support to the Teles-driver.
For the HiSax-driver.
Michael Knigge (knick@cove.han.de)
For contributing the imon-tool
Andreas Kool (akool@Kool.f.EUnet.de)
For contribution of the isdnlog/isdnrep-tool
Pedro Roque Marques (roque@di.fc.ul.pt)
For lot of new ideas and the pcbit driver.
Eberhard Mönkeberg (emoenke@gwdg.de)
For testing and help to get into kernel.
Thomas Neumann (tn@ruhr.de)
For help with Cisco-SLARP and keepalive
Jan den Ouden (denouden@groovin.xs4all.nl)
For contribution of the original teles-driver
Carsten Paeth (calle@calle.in-berlin.de)
For the AVM-B1-CAPI2.0 driver
Thomas Pfeiffer (pfeiffer@pds.de)
For V.110, extended T.70 and Hylafax extensions in isdn_tty.c
Max Riegel (riegel@max.franken.de)
For making the ICN hardware-documentation and test-equipment available.
Armin Schindler (mac@melware.de)
For the eicon active card driver.
Gerhard 'Fido' Schneider (fido@wuff.mayn.de)
For heavy-duty-beta-testing with his BBS ;)
Thomas Uhl (uhl@think.de)
For distributing the cards.
For pushing me to work ;-)

14
Documentation/isdn/index.rst
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@ -1,14 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0
====
ISDN
====
.. toctree::
:maxdepth: 2
interface_capi
m_isdn
credits

336
Documentation/isdn/interface_capi.rst
View File

@ -1,336 +0,0 @@
=========================================
Kernel CAPI Interface to Hardware Drivers
=========================================
1. Overview
===========
From the CAPI 2.0 specification:
COMMON-ISDN-API (CAPI) is an application programming interface standard used
to access ISDN equipment connected to basic rate interfaces (BRI) and primary
rate interfaces (PRI).
Kernel CAPI operates as a dispatching layer between CAPI applications and CAPI
hardware drivers. Hardware drivers register ISDN devices (controllers, in CAPI
lingo) with Kernel CAPI to indicate their readiness to provide their service
to CAPI applications. CAPI applications also register with Kernel CAPI,
requesting association with a CAPI device. Kernel CAPI then dispatches the
application registration to an available device, forwarding it to the
corresponding hardware driver. Kernel CAPI then forwards CAPI messages in both
directions between the application and the hardware driver.
Format and semantics of CAPI messages are specified in the CAPI 2.0 standard.
This standard is freely available from https://www.capi.org.
2. Driver and Device Registration
=================================
CAPI drivers must register each of the ISDN devices they control with Kernel
CAPI by calling the Kernel CAPI function attach_capi_ctr() with a pointer to a
struct capi_ctr before they can be used. This structure must be filled with
the names of the driver and controller, and a number of callback function
pointers which are subsequently used by Kernel CAPI for communicating with the
driver. The registration can be revoked by calling the function
detach_capi_ctr() with a pointer to the same struct capi_ctr.
Before the device can be actually used, the driver must fill in the device
information fields 'manu', 'version', 'profile' and 'serial' in the capi_ctr
structure of the device, and signal its readiness by calling capi_ctr_ready().
From then on, Kernel CAPI may call the registered callback functions for the
device.
If the device becomes unusable for any reason (shutdown, disconnect ...), the
driver has to call capi_ctr_down(). This will prevent further calls to the
callback functions by Kernel CAPI.
3. Application Registration and Communication
=============================================
Kernel CAPI forwards registration requests from applications (calls to CAPI
operation CAPI_REGISTER) to an appropriate hardware driver by calling its
register_appl() callback function. A unique Application ID (ApplID, u16) is
allocated by Kernel CAPI and passed to register_appl() along with the
parameter structure provided by the application. This is analogous to the
open() operation on regular files or character devices.
After a successful return from register_appl(), CAPI messages from the
application may be passed to the driver for the device via calls to the
send_message() callback function. Conversely, the driver may call Kernel
CAPI's capi_ctr_handle_message() function to pass a received CAPI message to
Kernel CAPI for forwarding to an application, specifying its ApplID.
Deregistration requests (CAPI operation CAPI_RELEASE) from applications are
forwarded as calls to the release_appl() callback function, passing the same
ApplID as with register_appl(). After return from release_appl(), no CAPI
messages for that application may be passed to or from the device anymore.
4. Data Structures
==================
4.1 struct capi_driver
----------------------
This structure describes a Kernel CAPI driver itself. It is used in the
register_capi_driver() and unregister_capi_driver() functions, and contains
the following non-private fields, all to be set by the driver before calling
register_capi_driver():
``char name[32]``
the name of the driver, as a zero-terminated ASCII string
``char revision[32]``
the revision number of the driver, as a zero-terminated ASCII string
4.2 struct capi_ctr
-------------------
This structure describes an ISDN device (controller) handled by a Kernel CAPI
driver. After registration via the attach_capi_ctr() function it is passed to
all controller specific lower layer interface and callback functions to
identify the controller to operate on.
It contains the following non-private fields:
to be set by the driver before calling attach_capi_ctr():
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
``struct module *owner``
pointer to the driver module owning the device
``void *driverdata``
an opaque pointer to driver specific data, not touched by Kernel CAPI
``char name[32]``
the name of the controller, as a zero-terminated ASCII string
``char *driver_name``
the name of the driver, as a zero-terminated ASCII string
``int (*load_firmware)(struct capi_ctr *ctrlr, capiloaddata *ldata)``
(optional) pointer to a callback function for sending firmware and
configuration data to the device
The function may return before the operation has completed.
Completion must be signalled by a call to capi_ctr_ready().
Return value: 0 on success, error code on error
Called in process context.
``void (*reset_ctr)(struct capi_ctr *ctrlr)``
(optional) pointer to a callback function for stopping the device,
releasing all registered applications
The function may return before the operation has completed.
Completion must be signalled by a call to capi_ctr_down().
Called in process context.
``void (*register_appl)(struct capi_ctr *ctrlr, u16 applid, capi_register_params *rparam)``
pointers to callback function for registration of
applications with the device
Calls to these functions are serialized by Kernel CAPI so that only
one call to any of them is active at any time.
``void (*release_appl)(struct capi_ctr *ctrlr, u16 applid)``
pointers to callback functions deregistration of
applications with the device
Calls to these functions are serialized by Kernel CAPI so that only
one call to any of them is active at any time.
``u16 (*send_message)(struct capi_ctr *ctrlr, struct sk_buff *skb)``
pointer to a callback function for sending a CAPI message to the
device
Return value: CAPI error code
If the method returns 0 (CAPI_NOERROR) the driver has taken ownership
of the skb and the caller may no longer access it. If it returns a
non-zero (error) value then ownership of the skb returns to the caller
who may reuse or free it.
The return value should only be used to signal problems with respect
to accepting or queueing the message. Errors occurring during the
actual processing of the message should be signaled with an
appropriate reply message.
May be called in process or interrupt context.
Calls to this function are not serialized by Kernel CAPI, ie. it must
be prepared to be re-entered.
``char *(*procinfo)(struct capi_ctr *ctrlr)``
pointer to a callback function returning the entry for the device in
the CAPI controller info table, /proc/capi/controller
Note:
Callback functions except send_message() are never called in interrupt
context.
to be filled in before calling capi_ctr_ready():
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
``u8 manu[CAPI_MANUFACTURER_LEN]``
value to return for CAPI_GET_MANUFACTURER
``capi_version version``
value to return for CAPI_GET_VERSION
``capi_profile profile``
value to return for CAPI_GET_PROFILE
``u8 serial[CAPI_SERIAL_LEN]``
value to return for CAPI_GET_SERIAL
4.3 SKBs
--------
CAPI messages are passed between Kernel CAPI and the driver via send_message()
and capi_ctr_handle_message(), stored in the data portion of a socket buffer
(skb). Each skb contains a single CAPI message coded according to the CAPI 2.0
standard.
For the data transfer messages, DATA_B3_REQ and DATA_B3_IND, the actual
payload data immediately follows the CAPI message itself within the same skb.
The Data and Data64 parameters are not used for processing. The Data64
parameter may be omitted by setting the length field of the CAPI message to 22
instead of 30.
4.4 The _cmsg Structure
-----------------------
(declared in <linux/isdn/capiutil.h>)
The _cmsg structure stores the contents of a CAPI 2.0 message in an easily
accessible form. It contains members for all possible CAPI 2.0 parameters,
including subparameters of the Additional Info and B Protocol structured
parameters, with the following exceptions:
* second Calling party number (CONNECT_IND)
* Data64 (DATA_B3_REQ and DATA_B3_IND)
* Sending complete (subparameter of Additional Info, CONNECT_REQ and INFO_REQ)
* Global Configuration (subparameter of B Protocol, CONNECT_REQ, CONNECT_RESP
and SELECT_B_PROTOCOL_REQ)
Only those parameters appearing in the message type currently being processed
are actually used. Unused members should be set to zero.
Members are named after the CAPI 2.0 standard names of the parameters they
represent. See <linux/isdn/capiutil.h> for the exact spelling. Member data
types are:
=========== =================================================================
u8 for CAPI parameters of type 'byte'
u16 for CAPI parameters of type 'word'
u32 for CAPI parameters of type 'dword'
_cstruct for CAPI parameters of type 'struct'
The member is a pointer to a buffer containing the parameter in
CAPI encoding (length + content). It may also be NULL, which will
be taken to represent an empty (zero length) parameter.
Subparameters are stored in encoded form within the content part.
_cmstruct alternative representation for CAPI parameters of type 'struct'
(used only for the 'Additional Info' and 'B Protocol' parameters)
The representation is a single byte containing one of the values:
CAPI_DEFAULT: The parameter is empty/absent.
CAPI_COMPOSE: The parameter is present.
Subparameter values are stored individually in the corresponding
_cmsg structure members.
=========== =================================================================
5. Lower Layer Interface Functions
==================================
::
int attach_capi_ctr(struct capi_ctr *ctrlr)
int detach_capi_ctr(struct capi_ctr *ctrlr)
register/unregister a device (controller) with Kernel CAPI
::
void capi_ctr_ready(struct capi_ctr *ctrlr)
void capi_ctr_down(struct capi_ctr *ctrlr)
signal controller ready/not ready
::
void capi_ctr_handle_message(struct capi_ctr * ctrlr, u16 applid,
struct sk_buff *skb)
pass a received CAPI message to Kernel CAPI
for forwarding to the specified application
6. Helper Functions and Macros
==============================
Macros to extract/set element values from/in a CAPI message header
(from <linux/isdn/capiutil.h>):
====================== ============================= ====================
Get Macro Set Macro Element (Type)
====================== ============================= ====================
CAPIMSG_LEN(m) CAPIMSG_SETLEN(m, len) Total Length (u16)
CAPIMSG_APPID(m) CAPIMSG_SETAPPID(m, applid) ApplID (u16)
CAPIMSG_COMMAND(m) CAPIMSG_SETCOMMAND(m,cmd) Command (u8)
CAPIMSG_SUBCOMMAND(m) CAPIMSG_SETSUBCOMMAND(m, cmd) Subcommand (u8)
CAPIMSG_CMD(m) - Command*256
+ Subcommand (u16)
CAPIMSG_MSGID(m) CAPIMSG_SETMSGID(m, msgid) Message Number (u16)
CAPIMSG_CONTROL(m) CAPIMSG_SETCONTROL(m, contr) Controller/PLCI/NCCI
(u32)
CAPIMSG_DATALEN(m) CAPIMSG_SETDATALEN(m, len) Data Length (u16)
====================== ============================= ====================
Library functions for working with _cmsg structures
(from <linux/isdn/capiutil.h>):
``char *capi_cmd2str(u8 Command, u8 Subcommand)``
Returns the CAPI 2.0 message name corresponding to the given command
and subcommand values, as a static ASCII string. The return value may
be NULL if the command/subcommand is not one of those defined in the
CAPI 2.0 standard.
7. Debugging
============
The module kernelcapi has a module parameter showcapimsgs controlling some
debugging output produced by the module. It can only be set when the module is
loaded, via a parameter "showcapimsgs=<n>" to the modprobe command, either on
the command line or in the configuration file.
If the lowest bit of showcapimsgs is set, kernelcapi logs controller and
application up and down events.
In addition, every registered CAPI controller has an associated traceflag
parameter controlling how CAPI messages sent from and to the controller are
logged. The traceflag parameter is initialized with the value of the
showcapimsgs parameter when the controller is registered, but can later be
changed via the MANUFACTURER_REQ command KCAPI_CMD_TRACE.
If the value of traceflag is non-zero, CAPI messages are logged.
DATA_B3 messages are only logged if the value of traceflag is > 2.
If the lowest bit of traceflag is set, only the command/subcommand and message
length are logged. Otherwise, kernelcapi logs a readable representation of
the entire message.

9
Documentation/isdn/m_isdn.rst
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@ -1,9 +0,0 @@
============
mISDN Driver
============
mISDN is a new modular ISDN driver, in the long term it should replace
the old I4L driver architecture for passive ISDN cards.
It was designed to allow a broad range of applications and interfaces
but only have the basic function in kernel, the interface to the user
space is based on sockets with a own address family AF_ISDN.

191
Documentation/networking/6pack.rst
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@ -1,191 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0
==============
6pack Protocol
==============
This is the 6pack-mini-HOWTO, written by
Andreas Könsgen DG3KQ
:Internet: ajk@comnets.uni-bremen.de
:AMPR-net: dg3kq@db0pra.ampr.org
:AX.25: dg3kq@db0ach.#nrw.deu.eu
Last update: April 7, 1998
1. What is 6pack, and what are the advantages to KISS?
======================================================
6pack is a transmission protocol for data exchange between the PC and
the TNC over a serial line. It can be used as an alternative to KISS.
6pack has two major advantages:
- The PC is given full control over the radio
channel. Special control data is exchanged between the PC and the TNC so
that the PC knows at any time if the TNC is receiving data, if a TNC
buffer underrun or overrun has occurred, if the PTT is
set and so on. This control data is processed at a higher priority than
normal data, so a data stream can be interrupted at any time to issue an
important event. This helps to improve the channel access and timing
algorithms as everything is computed in the PC. It would even be possible
to experiment with something completely different from the known CSMA and
DAMA channel access methods.
This kind of real-time control is especially important to supply several
TNCs that are connected between each other and the PC by a daisy chain
(however, this feature is not supported yet by the Linux 6pack driver).
- Each packet transferred over the serial line is supplied with a checksum,
so it is easy to detect errors due to problems on the serial line.
Received packets that are corrupt are not passed on to the AX.25 layer.
Damaged packets that the TNC has received from the PC are not transmitted.
More details about 6pack are described in the file 6pack.ps that is located
in the doc directory of the AX.25 utilities package.
2. Who has developed the 6pack protocol?
========================================
The 6pack protocol has been developed by Ekki Plicht DF4OR, Henning Rech
DF9IC and Gunter Jost DK7WJ. A driver for 6pack, written by Gunter Jost and
Matthias Welwarsky DG2FEF, comes along with the PC version of FlexNet.
They have also written a firmware for TNCs to perform the 6pack
protocol (see section 4 below).
3. Where can I get the latest version of 6pack for LinuX?
=========================================================
At the moment, the 6pack stuff can obtained via anonymous ftp from
db0bm.automation.fh-aachen.de. In the directory /incoming/dg3kq,
there is a file named 6pack.tgz.
4. Preparing the TNC for 6pack operation
========================================
To be able to use 6pack, a special firmware for the TNC is needed. The EPROM
of a newly bought TNC does not contain 6pack, so you will have to
program an EPROM yourself. The image file for 6pack EPROMs should be
available on any packet radio box where PC/FlexNet can be found. The name of
the file is 6pack.bin. This file is copyrighted and maintained by the FlexNet
team. It can be used under the terms of the license that comes along
with PC/FlexNet. Please do not ask me about the internals of this file as I
don't know anything about it. I used a textual description of the 6pack
protocol to program the Linux driver.
TNCs contain a 64kByte EPROM, the lower half of which is used for
the firmware/KISS. The upper half is either empty or is sometimes
programmed with software called TAPR. In the latter case, the TNC
is supplied with a DIP switch so you can easily change between the
two systems. When programming a new EPROM, one of the systems is replaced
by 6pack. It is useful to replace TAPR, as this software is rarely used
nowadays. If your TNC is not equipped with the switch mentioned above, you
can build in one yourself that switches over the highest address pin
of the EPROM between HIGH and LOW level. After having inserted the new EPROM
and switched to 6pack, apply power to the TNC for a first test. The connect
and the status LED are lit for about a second if the firmware initialises
the TNC correctly.
5. Building and installing the 6pack driver
===========================================
The driver has been tested with kernel version 2.1.90. Use with older
kernels may lead to a compilation error because the interface to a kernel
function has been changed in the 2.1.8x kernels.
How to turn on 6pack support:
-----------------------------
- In the linux kernel configuration program, select the code maturity level
options menu and turn on the prompting for development drivers.
- Select the amateur radio support menu and turn on the serial port 6pack
driver.
- Compile and install the kernel and the modules.
To use the driver, the kissattach program delivered with the AX.25 utilities
has to be modified.
- Do a cd to the directory that holds the kissattach sources. Edit the
kissattach.c file. At the top, insert the following lines::
#ifndef N_6PACK
#define N_6PACK (N_AX25+1)
#endif
Then find the line:
int disc = N_AX25;
and replace N_AX25 by N_6PACK.
- Recompile kissattach. Rename it to spattach to avoid confusions.
Installing the driver:
----------------------
- Do an insmod 6pack. Look at your /var/log/messages file to check if the
module has printed its initialization message.
- Do a spattach as you would launch kissattach when starting a KISS port.
Check if the kernel prints the message '6pack: TNC found'.
- From here, everything should work as if you were setting up a KISS port.
The only difference is that the network device that represents
the 6pack port is called sp instead of sl or ax. So, sp0 would be the
first 6pack port.
Although the driver has been tested on various platforms, I still declare it
ALPHA. BE CAREFUL! Sync your disks before insmoding the 6pack module
and spattaching. Watch out if your computer behaves strangely. Read section
6 of this file about known problems.
Note that the connect and status LEDs of the TNC are controlled in a
different way than they are when the TNC is used with PC/FlexNet. When using
FlexNet, the connect LED is on if there is a connection; the status LED is
on if there is data in the buffer of the PC's AX.25 engine that has to be
transmitted. Under Linux, the 6pack layer is beyond the AX.25 layer,
so the 6pack driver doesn't know anything about connects or data that
has not yet been transmitted. Therefore the LEDs are controlled
as they are in KISS mode: The connect LED is turned on if data is transferred
from the PC to the TNC over the serial line, the status LED if data is
sent to the PC.
6. Known problems
=================
When testing the driver with 2.0.3x kernels and
operating with data rates on the radio channel of 9600 Baud or higher,
the driver may, on certain systems, sometimes print the message '6pack:
bad checksum', which is due to data loss if the other station sends two
or more subsequent packets. I have been told that this is due to a problem
with the serial driver of 2.0.3x kernels. I don't know yet if the problem
still exists with 2.1.x kernels, as I have heard that the serial driver
code has been changed with 2.1.x.
When shutting down the sp interface with ifconfig, the kernel crashes if
there is still an AX.25 connection left over which an IP connection was
running, even if that IP connection is already closed. The problem does not
occur when there is a bare AX.25 connection still running. I don't know if
this is a problem of the 6pack driver or something else in the kernel.
The driver has been tested as a module, not yet as a kernel-builtin driver.
The 6pack protocol supports daisy-chaining of TNCs in a token ring, which is
connected to one serial port of the PC. This feature is not implemented
and at least at the moment I won't be able to do it because I do not have
the opportunity to build a TNC daisy-chain and test it.
Some of the comments in the source code are inaccurate. They are left from
the SLIP/KISS driver, from which the 6pack driver has been derived.
I haven't modified or removed them yet -- sorry! The code itself needs
some cleaning and optimizing. This will be done in a later release.
If you encounter a bug or if you have a question or suggestion concerning the
driver, feel free to mail me, using the addresses given at the beginning of
this file.
Have fun!
Andreas

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.. SPDX-License-Identifier: GPL-2.0
=====
AX.25
=====
To use the amateur radio protocols within Linux you will need to get a
suitable copy of the AX.25 Utilities. More detailed information about
AX.25, NET/ROM and ROSE, associated programs and utilities can be
found on https://linux-ax25.in-berlin.de.
There is a mailing list for discussing Linux amateur radio matters
called linux-hams@vger.kernel.org. To subscribe to it, send a message to
linux-hams+subscribe@vger.kernel.org or use the web interface at
https://vger.kernel.org. The subject and body of the message are
ignored. You don't need to be subscribed to post but of course that
means you might miss an answer.

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.. SPDX-License-Identifier: GPL-2.0
.. include:: <isonum.txt>
================
Using Linux CAIF
================
:Copyright: |copy| ST-Ericsson AB 2010
:Author: Sjur Brendeland/ sjur.brandeland@stericsson.com
Start
=====
If you have compiled CAIF for modules do::
$modprobe crc_ccitt
$modprobe caif
$modprobe caif_socket
$modprobe chnl_net
Preparing the setup with a STE modem
====================================
If you are working on integration of CAIF you should make sure
that the kernel is built with module support.
There are some things that need to be tweaked to get the host TTY correctly
set up to talk to the modem.
Since the CAIF stack is running in the kernel and we want to use the existing
TTY, we are installing our physical serial driver as a line discipline above
the TTY device.
To achieve this we need to install the N_CAIF ldisc from user space.
The benefit is that we can hook up to any TTY.
The use of Start-of-frame-extension (STX) must also be set as
module parameter "ser_use_stx".
Normally Frame Checksum is always used on UART, but this is also provided as a
module parameter "ser_use_fcs".
::
$ modprobe caif_serial ser_ttyname=/dev/ttyS0 ser_use_stx=yes
$ ifconfig caif_ttyS0 up
PLEASE NOTE:
There is a limitation in Android shell.
It only accepts one argument to insmod/modprobe!
Trouble shooting
================
There are debugfs parameters provided for serial communication.
/sys/kernel/debug/caif_serial/<tty-name>/
* ser_state: Prints the bit-mask status where
- 0x02 means SENDING, this is a transient state.
- 0x10 means FLOW_OFF_SENT, i.e. the previous frame has not been sent
and is blocking further send operation. Flow OFF has been propagated
to all CAIF Channels using this TTY.
* tty_status: Prints the bit-mask tty status information
- 0x01 - tty->warned is on.
- 0x04 - tty->packed is on.
- 0x08 - tty->flow.tco_stopped is on.
- 0x10 - tty->hw_stopped is on.
- 0x20 - tty->flow.stopped is on.
* last_tx_msg: Binary blob Prints the last transmitted frame.
This can be printed with::
$od --format=x1 /sys/kernel/debug/caif_serial/<tty>/last_rx_msg.
The first two tx messages sent look like this. Note: The initial
byte 02 is start of frame extension (STX) used for re-syncing
upon errors.
- Enumeration::
0000000 02 05 00 00 03 01 d2 02
| | | | | |
STX(1) | | | |
Length(2)| | |
Control Channel(1)
Command:Enumeration(1)
Link-ID(1)
Checksum(2)
- Channel Setup::
0000000 02 07 00 00 00 21 a1 00 48 df
| | | | | | | |
STX(1) | | | | | |
Length(2)| | | | |
Control Channel(1)
Command:Channel Setup(1)
Channel Type(1)
Priority and Link-ID(1)
Endpoint(1)
Checksum(2)
* last_rx_msg: Prints the last transmitted frame.
The RX messages for LinkSetup look almost identical but they have the
bit 0x20 set in the command bit, and Channel Setup has added one byte
before Checksum containing Channel ID.
NOTE:
Several CAIF Messages might be concatenated. The maximum debug
buffer size is 128 bytes.
Error Scenarios
===============
- last_tx_msg contains channel setup message and last_rx_msg is empty ->
The host seems to be able to send over the UART, at least the CAIF ldisc get
notified that sending is completed.
- last_tx_msg contains enumeration message and last_rx_msg is empty ->
The host is not able to send the message from UART, the tty has not been
able to complete the transmit operation.
- if /sys/kernel/debug/caif_serial/<tty>/tty_status is non-zero there
might be problems transmitting over UART.
E.g. host and modem wiring is not correct you will typically see
tty_status = 0x10 (hw_stopped) and ser_state = 0x10 (FLOW_OFF_SENT).
You will probably see the enumeration message in last_tx_message
and empty last_rx_message.

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.. SPDX-License-Identifier: GPL-2.0
CAIF
====
Contents:
.. toctree::
:maxdepth: 2
linux_caif
caif

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.. SPDX-License-Identifier: GPL-2.0
.. include:: <isonum.txt>
==========
Linux CAIF
==========
Copyright |copy| ST-Ericsson AB 2010
:Author: Sjur Brendeland/ sjur.brandeland@stericsson.com
:License terms: GNU General Public License (GPL) version 2
Introduction
============
CAIF is a MUX protocol used by ST-Ericsson cellular modems for
communication between Modem and host. The host processes can open virtual AT
channels, initiate GPRS Data connections, Video channels and Utility Channels.
The Utility Channels are general purpose pipes between modem and host.
ST-Ericsson modems support a number of transports between modem
and host. Currently, UART and Loopback are available for Linux.
Architecture
============
The implementation of CAIF is divided into:
* CAIF Socket Layer and GPRS IP Interface.
* CAIF Core Protocol Implementation
* CAIF Link Layer, implemented as NET devices.
::
RTNL
!
! +------+ +------+
! +------+! +------+!
! ! IP !! !Socket!!
+-------> !interf!+ ! API !+ <- CAIF Client APIs
! +------+ +------!
! ! !
! +-----------+
! !
! +------+ <- CAIF Core Protocol
! ! CAIF !
! ! Core !
! +------+
! +----------!---------+
! ! ! !
! +------+ +-----+ +------+
+--> ! HSI ! ! TTY ! ! USB ! <- Link Layer (Net Devices)
+------+ +-----+ +------+
Implementation
==============
CAIF Core Protocol Layer
------------------------
CAIF Core layer implements the CAIF protocol as defined by ST-Ericsson.
It implements the CAIF protocol stack in a layered approach, where
each layer described in the specification is implemented as a separate layer.
The architecture is inspired by the design patterns "Protocol Layer" and
"Protocol Packet".
CAIF structure
^^^^^^^^^^^^^^
The Core CAIF implementation contains:
- Simple implementation of CAIF.
- Layered architecture (a la Streams), each layer in the CAIF
specification is implemented in a separate c-file.
- Clients must call configuration function to add PHY layer.
- Clients must implement CAIF layer to consume/produce
CAIF payload with receive and transmit functions.
- Clients must call configuration function to add and connect the
Client layer.
- When receiving / transmitting CAIF Packets (cfpkt), ownership is passed
to the called function (except for framing layers' receive function)
Layered Architecture
====================
The CAIF protocol can be divided into two parts: Support functions and Protocol
Implementation. The support functions include:
- CFPKT CAIF Packet. Implementation of CAIF Protocol Packet. The
CAIF Packet has functions for creating, destroying and adding content
and for adding/extracting header and trailers to protocol packets.
The CAIF Protocol implementation contains:
- CFCNFG CAIF Configuration layer. Configures the CAIF Protocol
Stack and provides a Client interface for adding Link-Layer and
Driver interfaces on top of the CAIF Stack.
- CFCTRL CAIF Control layer. Encodes and Decodes control messages
such as enumeration and channel setup. Also matches request and
response messages.
- CFSERVL General CAIF Service Layer functionality; handles flow
control and remote shutdown requests.
- CFVEI CAIF VEI layer. Handles CAIF AT Channels on VEI (Virtual
External Interface). This layer encodes/decodes VEI frames.
- CFDGML CAIF Datagram layer. Handles CAIF Datagram layer (IP
traffic), encodes/decodes Datagram frames.
- CFMUX CAIF Mux layer. Handles multiplexing between multiple
physical bearers and multiple channels such as VEI, Datagram, etc.
The MUX keeps track of the existing CAIF Channels and
Physical Instances and selects the appropriate instance based
on Channel-Id and Physical-ID.
- CFFRML CAIF Framing layer. Handles Framing i.e. Frame length
and frame checksum.
- CFSERL CAIF Serial layer. Handles concatenation/split of frames
into CAIF Frames with correct length.
::
+---------+
| Config |
| CFCNFG |
+---------+
!
+---------+ +---------+ +---------+
| AT | | Control | | Datagram|
| CFVEIL | | CFCTRL | | CFDGML |
+---------+ +---------+ +---------+
\_____________!______________/
!
+---------+
| MUX |
| |
+---------+
_____!_____
/ \
+---------+ +---------+
| CFFRML | | CFFRML |
| Framing | | Framing |
+---------+ +---------+
! !
+---------+ +---------+
| | | Serial |
| | | CFSERL |
+---------+ +---------+
In this layered approach the following "rules" apply.
- All layers embed the same structure "struct cflayer"
- A layer does not depend on any other layer's private data.
- Layers are stacked by setting the pointers::
layer->up , layer->dn
- In order to send data upwards, each layer should do::
layer->up->receive(layer->up, packet);
- In order to send data downwards, each layer should do::
layer->dn->transmit(layer->dn, packet);
CAIF Socket and IP interface
============================
The IP interface and CAIF socket API are implemented on top of the
CAIF Core protocol. The IP Interface and CAIF socket have an instance of
'struct cflayer', just like the CAIF Core protocol stack.
Net device and Socket implement the 'receive()' function defined by
'struct cflayer', just like the rest of the CAIF stack. In this way, transmit and
receive of packets is handled as by the rest of the layers: the 'dn->transmit()'
function is called in order to transmit data.
Configuration of Link Layer
---------------------------
The Link Layer is implemented as Linux network devices (struct net_device).
Payload handling and registration is done using standard Linux mechanisms.
The CAIF Protocol relies on a loss-less link layer without implementing
retransmission. This implies that packet drops must not happen.
Therefore a flow-control mechanism is implemented where the physical
interface can initiate flow stop for all CAIF Channels.

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.. SPDX-License-Identifier: GPL-2.0
=============================================
FORE Systems PCA-200E/SBA-200E ATM NIC driver
=============================================
This driver adds support for the FORE Systems 200E-series ATM adapters
to the Linux operating system. It is based on the earlier PCA-200E driver
written by Uwe Dannowski.
The driver simultaneously supports PCA-200E and SBA-200E adapters on
i386, alpha (untested), powerpc, sparc and sparc64 archs.
The intent is to enable the use of different models of FORE adapters at the
same time, by hosts that have several bus interfaces (such as PCI+SBUS,
or PCI+EISA).
Only PCI and SBUS devices are currently supported by the driver, but support
for other bus interfaces such as EISA should not be too hard to add.
Firmware Copyright Notice
-------------------------
Please read the fore200e_firmware_copyright file present
in the linux/drivers/atm directory for details and restrictions.
Firmware Updates
----------------
The FORE Systems 200E-series driver is shipped with firmware data being
uploaded to the ATM adapters at system boot time or at module loading time.
The supplied firmware images should work with all adapters.
However, if you encounter problems (the firmware doesn't start or the driver
is unable to read the PROM data), you may consider trying another firmware
version. Alternative binary firmware images can be found somewhere on the
ForeThought CD-ROM supplied with your adapter by FORE Systems.
You can also get the latest firmware images from FORE Systems at
https://en.wikipedia.org/wiki/FORE_Systems. Register TACTics Online and go to
the 'software updates' pages. The firmware binaries are part of
the various ForeThought software distributions.
Notice that different versions of the PCA-200E firmware exist, depending
on the endianness of the host architecture. The driver is shipped with
both little and big endian PCA firmware images.
Name and location of the new firmware images can be set at kernel
configuration time:
1. Copy the new firmware binary files (with .bin, .bin1 or .bin2 suffix)
to some directory, such as linux/drivers/atm.
2. Reconfigure your kernel to set the new firmware name and location.
Expected pathnames are absolute or relative to the drivers/atm directory.
3. Rebuild and re-install your kernel or your module.
Feedback
--------
Feedback is welcome. Please send success stories/bug reports/
patches/improvement/comments/flames to <lizzi@cnam.fr>.

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:maxdepth: 2
cxacru
fore200e
iphase

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.. SPDX-License-Identifier: GPL-2.0
==================================
ATM (i)Chip IA Linux Driver Source
==================================
READ ME FIRST
--------------------------------------------------------------------------------
Read This Before You Begin!
--------------------------------------------------------------------------------
Description
===========
This is the README file for the Interphase PCI ATM (i)Chip IA Linux driver
source release.
The features and limitations of this driver are as follows:
- A single VPI (VPI value of 0) is supported.
- Supports 4K VCs for the server board (with 512K control memory) and 1K
VCs for the client board (with 128K control memory).
- UBR, ABR and CBR service categories are supported.
- Only AAL5 is supported.
- Supports setting of PCR on the VCs.
- Multiple adapters in a system are supported.
- All variants of Interphase ATM PCI (i)Chip adapter cards are supported,
including x575 (OC3, control memory 128K , 512K and packet memory 128K,
512K and 1M), x525 (UTP25) and x531 (DS3 and E3). See
http://www.iphase.com/
for details.
- Only x86 platforms are supported.
- SMP is supported.
Before You Start
================
Installation
------------
1. Installing the adapters in the system
To install the ATM adapters in the system, follow the steps below.
a. Login as root.
b. Shut down the system and power off the system.
c. Install one or more ATM adapters in the system.
d. Connect each adapter to a port on an ATM switch. The green 'Link'
LED on the front panel of the adapter will be on if the adapter is
connected to the switch properly when the system is powered up.
e. Power on and boot the system.
2. [ Removed ]
3. Rebuild kernel with ABR support
[ a. and b. removed ]
c. Reconfigure the kernel, choose the Interphase ia driver through "make
menuconfig" or "make xconfig".
d. Rebuild the kernel, loadable modules and the atm tools.
e. Install the new built kernel and modules and reboot.
4. Load the adapter hardware driver (ia driver) if it is built as a module
a. Login as root.
b. Change directory to /lib/modules/<kernel-version>/atm.
c. Run "insmod suni.o;insmod iphase.o"
The yellow 'status' LED on the front panel of the adapter will blink
while the driver is loaded in the system.
d. To verify that the 'ia' driver is loaded successfully, run the
following command::
cat /proc/atm/devices
If the driver is loaded successfully, the output of the command will
be similar to the following lines::
Itf Type ESI/"MAC"addr AAL(TX,err,RX,err,drop) ...
0 ia xxxxxxxxx 0 ( 0 0 0 0 0 ) 5 ( 0 0 0 0 0 )
You can also check the system log file /var/log/messages for messages
related to the ATM driver.
5. Ia Driver Configuration
5.1 Configuration of adapter buffers
The (i)Chip boards have 3 different packet RAM size variants: 128K, 512K and
1M. The RAM size decides the number of buffers and buffer size. The default
size and number of buffers are set as following:
========= ======= ====== ====== ====== ====== ======
Total Rx RAM Tx RAM Rx Buf Tx Buf Rx buf Tx buf
RAM size size size size size cnt cnt
========= ======= ====== ====== ====== ====== ======
128K 64K 64K 10K 10K 6 6
512K 256K 256K 10K 10K 25 25
1M 512K 512K 10K 10K 51 51
========= ======= ====== ====== ====== ====== ======
These setting should work well in most environments, but can be
changed by typing the following command::
insmod <IA_DIR>/ia.o IA_RX_BUF=<RX_CNT> IA_RX_BUF_SZ=<RX_SIZE> \
IA_TX_BUF=<TX_CNT> IA_TX_BUF_SZ=<TX_SIZE>
Where:
- RX_CNT = number of receive buffers in the range (1-128)
- RX_SIZE = size of receive buffers in the range (48-64K)
- TX_CNT = number of transmit buffers in the range (1-128)
- TX_SIZE = size of transmit buffers in the range (48-64K)
1. Transmit and receive buffer size must be a multiple of 4.
2. Care should be taken so that the memory required for the
transmit and receive buffers is less than or equal to the
total adapter packet memory.
5.2 Turn on ia debug trace
When the ia driver is built with the CONFIG_ATM_IA_DEBUG flag, the driver
can provide more debug trace if needed. There is a bit mask variable,
IADebugFlag, which controls the output of the traces. You can find the bit
map of the IADebugFlag in iphase.h.
The debug trace can be turn on through the insmod command line option, for
example, "insmod iphase.o IADebugFlag=0xffffffff" can turn on all the debug
traces together with loading the driver.
6. Ia Driver Test Using ttcp_atm and PVC
For the PVC setup, the test machines can either be connected back-to-back or
through a switch. If connected through the switch, the switch must be
configured for the PVC(s).
a. For UBR test:
At the test machine intended to receive data, type::
ttcp_atm -r -a -s 0.100
At the other test machine, type::
ttcp_atm -t -a -s 0.100 -n 10000
Run "ttcp_atm -h" to display more options of the ttcp_atm tool.
b. For ABR test:
It is the same as the UBR testing, but with an extra command option::
-Pabr:max_pcr=<xxx>
where:
xxx = the maximum peak cell rate, from 170 - 353207.
This option must be set on both the machines.
c. For CBR test:
It is the same as the UBR testing, but with an extra command option::
-Pcbr:max_pcr=<xxx>
where:
xxx = the maximum peak cell rate, from 170 - 353207.
This option may only be set on the transmit machine.
Outstanding Issues
==================
Contact Information
-------------------
::
Customer Support:
United States: Telephone: (214) 654-5555
Fax: (214) 654-5500
E-Mail: intouch@iphase.com
Europe: Telephone: 33 (0)1 41 15 44 00
Fax: 33 (0)1 41 15 12 13
World Wide Web: http://www.iphase.com
Anonymous FTP: ftp.iphase.com

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.. SPDX-License-Identifier: GPL-2.0
=============================================================================
Linux and the 3Com EtherLink III Series Ethercards (driver v1.18c and higher)
=============================================================================
This file contains the instructions and caveats for v1.18c and higher versions
of the 3c509 driver. You should not use the driver without reading this file.
release 1.0
28 February 2002
Current maintainer (corrections to):
David Ruggiero <jdr@farfalle.com>
Introduction
============
The following are notes and information on using the 3Com EtherLink III series
ethercards in Linux. These cards are commonly known by the most widely-used
card's 3Com model number, 3c509. They are all 10mb/s ISA-bus cards and shouldn't
be (but sometimes are) confused with the similarly-numbered PCI-bus "3c905"
(aka "Vortex" or "Boomerang") series. Kernel support for the 3c509 family is
provided by the module 3c509.c, which has code to support all of the following
models:
- 3c509 (original ISA card)
- 3c509B (later revision of the ISA card; supports full-duplex)
- 3c589 (PCMCIA)
- 3c589B (later revision of the 3c589; supports full-duplex)
- 3c579 (EISA)
Large portions of this documentation were heavily borrowed from the guide
written the original author of the 3c509 driver, Donald Becker. The master
copy of that document, which contains notes on older versions of the driver,
currently resides on Scyld web server: http://www.scyld.com/.
Special Driver Features
=======================
Overriding card settings
The driver allows boot- or load-time overriding of the card's detected IOADDR,
IRQ, and transceiver settings, although this capability shouldn't generally be
needed except to enable full-duplex mode (see below). An example of the syntax
for LILO parameters for doing this::
ether=10,0x310,3,0x3c509,eth0
This configures the first found 3c509 card for IRQ 10, base I/O 0x310, and
transceiver type 3 (10base2). The flag "0x3c509" must be set to avoid conflicts
with other card types when overriding the I/O address. When the driver is
loaded as a module, only the IRQ may be overridden. For example,
setting two cards to IRQ10 and IRQ11 is done by using the irq module
option::
options 3c509 irq=10,11
Full-duplex mode
================
The v1.18c driver added support for the 3c509B's full-duplex capabilities.
In order to enable and successfully use full-duplex mode, three conditions
must be met:
(a) You must have a Etherlink III card model whose hardware supports full-
duplex operations. Currently, the only members of the 3c509 family that are
positively known to support full-duplex are the 3c509B (ISA bus) and 3c589B
(PCMCIA) cards. Cards without the "B" model designation do *not* support
full-duplex mode; these include the original 3c509 (no "B"), the original
3c589, the 3c529 (MCA bus), and the 3c579 (EISA bus).
(b) You must be using your card's 10baseT transceiver (i.e., the RJ-45
connector), not its AUI (thick-net) or 10base2 (thin-net/coax) interfaces.
AUI and 10base2 network cabling is physically incapable of full-duplex
operation.
(c) Most importantly, your 3c509B must be connected to a link partner that is
itself full-duplex capable. This is almost certainly one of two things: a full-
duplex-capable Ethernet switch (*not* a hub), or a full-duplex-capable NIC on
another system that's connected directly to the 3c509B via a crossover cable.
Full-duplex mode can be enabled using 'ethtool'.
.. warning::
Extremely important caution concerning full-duplex mode
Understand that the 3c509B's hardware's full-duplex support is much more
limited than that provide by more modern network interface cards. Although
at the physical layer of the network it fully supports full-duplex operation,
the card was designed before the current Ethernet auto-negotiation (N-way)
spec was written. This means that the 3c509B family ***cannot and will not
auto-negotiate a full-duplex connection with its link partner under any
circumstances, no matter how it is initialized***. If the full-duplex mode
of the 3c509B is enabled, its link partner will very likely need to be
independently _forced_ into full-duplex mode as well; otherwise various nasty
failures will occur - at the very least, you'll see massive numbers of packet
collisions. This is one of very rare circumstances where disabling auto-
negotiation and forcing the duplex mode of a network interface card or switch
would ever be necessary or desirable.
Available Transceiver Types
===========================
For versions of the driver v1.18c and above, the available transceiver types are:
== =========================================================================
0 transceiver type from EEPROM config (normally 10baseT); force half-duplex
1 AUI (thick-net / DB15 connector)
2 (undefined)
3 10base2 (thin-net == coax / BNC connector)
4 10baseT (RJ-45 connector); force half-duplex mode
8 transceiver type and duplex mode taken from card's EEPROM config settings
12 10baseT (RJ-45 connector); force full-duplex mode
== =========================================================================
Prior to driver version 1.18c, only transceiver codes 0-4 were supported. Note
that the new transceiver codes 8 and 12 are the *only* ones that will enable
full-duplex mode, no matter what the card's detected EEPROM settings might be.
This insured that merely upgrading the driver from an earlier version would
never automatically enable full-duplex mode in an existing installation;
it must always be explicitly enabled via one of these code in order to be
activated.
The transceiver type can be changed using 'ethtool'.
Interpretation of error messages and common problems
----------------------------------------------------
Error Messages
^^^^^^^^^^^^^^
eth0: Infinite loop in interrupt, status 2011.
These are "mostly harmless" message indicating that the driver had too much
work during that interrupt cycle. With a status of 0x2011 you are receiving
packets faster than they can be removed from the card. This should be rare
or impossible in normal operation. Possible causes of this error report are:
- a "green" mode enabled that slows the processor down when there is no
keyboard activity.
- some other device or device driver hogging the bus or disabling interrupts.
Check /proc/interrupts for excessive interrupt counts. The timer tick
interrupt should always be incrementing faster than the others.
No received packets
^^^^^^^^^^^^^^^^^^^
If a 3c509, 3c562 or 3c589 can successfully transmit packets, but never
receives packets (as reported by /proc/net/dev or 'ifconfig') you likely
have an interrupt line problem. Check /proc/interrupts to verify that the
card is actually generating interrupts. If the interrupt count is not
increasing you likely have a physical conflict with two devices trying to
use the same ISA IRQ line. The common conflict is with a sound card on IRQ10
or IRQ5, and the easiest solution is to move the 3c509 to a different
interrupt line. If the device is receiving packets but 'ping' doesn't work,
you have a routing problem.
Tx Carrier Errors Reported in /proc/net/dev
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
If an EtherLink III appears to transmit packets, but the "Tx carrier errors"
field in /proc/net/dev increments as quickly as the Tx packet count, you
likely have an unterminated network or the incorrect media transceiver selected.
3c509B card is not detected on machines with an ISA PnP BIOS.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
While the updated driver works with most PnP BIOS programs, it does not work
with all. This can be fixed by disabling PnP support using the 3Com-supplied
setup program.
3c509 card is not detected on overclocked machines
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Increase the delay time in id_read_eeprom() from the current value, 500,
to an absurdly high value, such as 5000.
Decoding Status and Error Messages
----------------------------------
The bits in the main status register are:
===== ======================================
value description
===== ======================================
0x01 Interrupt latch
0x02 Tx overrun, or Rx underrun
0x04 Tx complete
0x08 Tx FIFO room available
0x10 A complete Rx packet has arrived
0x20 A Rx packet has started to arrive
0x40 The driver has requested an interrupt
0x80 Statistics counter nearly full
===== ======================================
The bits in the transmit (Tx) status word are:
===== ============================================
value description
===== ============================================
0x02 Out-of-window collision.
0x04 Status stack overflow (normally impossible).
0x08 16 collisions.
0x10 Tx underrun (not enough PCI bus bandwidth).
0x20 Tx jabber.
0x40 Tx interrupt requested.
0x80 Status is valid (this should always be set).
===== ============================================
When a transmit error occurs the driver produces a status message such as::
eth0: Transmit error, Tx status register 82
The two values typically seen here are:
0x82
^^^^
Out of window collision. This typically occurs when some other Ethernet
host is incorrectly set to full duplex on a half duplex network.
0x88
^^^^
16 collisions. This typically occurs when the network is exceptionally busy
or when another host doesn't correctly back off after a collision. If this
error is mixed with 0x82 errors it is the result of a host incorrectly set
to full duplex (see above).
Both of these errors are the result of network problems that should be
corrected. They do not represent driver malfunction.
Revision history (this file)
============================
28Feb02 v1.0 DR New; major portions based on Becker original 3c509 docs

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@ -10,7 +10,6 @@ Contents:
.. toctree::
:maxdepth: 2
3com/3c509
3com/vortex
amazon/ena
altera/altera_tse
@ -52,7 +51,6 @@ Contents:
pensando/ionic
pensando/ionic_rdma
qualcomm/ppe/ppe
smsc/smc9
stmicro/stmmac
ti/cpsw
ti/cpsw_switchdev

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.. SPDX-License-Identifier: GPL-2.0
================
SMC 9xxxx Driver
================
Revision 0.12
3/5/96
Copyright 1996 Erik Stahlman
Released under terms of the GNU General Public License.
This file contains the instructions and caveats for my SMC9xxx driver. You
should not be using the driver without reading this file.
Things to note about installation:
1. The driver should work on all kernels from 1.2.13 until 1.3.71.
(A kernel patch is supplied for 1.3.71 )
2. If you include this into the kernel, you might need to change some
options, such as for forcing IRQ.
3. To compile as a module, run 'make'.
Make will give you the appropriate options for various kernel support.
4. Loading the driver as a module::
use: insmod smc9194.o
optional parameters:
io=xxxx : your base address
irq=xx : your irq
ifport=x : 0 for whatever is default
1 for twisted pair
2 for AUI ( or BNC on some cards )
How to obtain the latest version?
FTP:
ftp://fenris.campus.vt.edu/smc9/smc9-12.tar.gz
ftp://sfbox.vt.edu/filebox/F/fenris/smc9/smc9-12.tar.gz
Contacting me:
erik@mail.vt.edu

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.. SPDX-License-Identifier: GPL-2.0
===============================
Linux Drivers for Baycom Modems
===============================
Thomas M. Sailer, HB9JNX/AE4WA, <sailer@ife.ee.ethz.ch>
The drivers for the baycom modems have been split into
separate drivers as they did not share any code, and the driver
and device names have changed.
This document describes the Linux Kernel Drivers for simple Baycom style
amateur radio modems.
The following drivers are available:
====================================
baycom_ser_fdx:
This driver supports the SER12 modems either full or half duplex.
Its baud rate may be changed via the ``baud`` module parameter,
therefore it supports just about every bit bang modem on a
serial port. Its devices are called bcsf0 through bcsf3.
This is the recommended driver for SER12 type modems,
however if you have a broken UART clone that does not have working
delta status bits, you may try baycom_ser_hdx.
baycom_ser_hdx:
This is an alternative driver for SER12 type modems.
It only supports half duplex, and only 1200 baud. Its devices
are called bcsh0 through bcsh3. Use this driver only if baycom_ser_fdx
does not work with your UART.
baycom_par:
This driver supports the par96 and picpar modems.
Its devices are called bcp0 through bcp3.
baycom_epp:
This driver supports the EPP modem.
Its devices are called bce0 through bce3.
This driver is work-in-progress.
The following modems are supported:
======= ========================================================================
ser12 This is a very simple 1200 baud AFSK modem. The modem consists only
of a modulator/demodulator chip, usually a TI TCM3105. The computer
is responsible for regenerating the receiver bit clock, as well as
for handling the HDLC protocol. The modem connects to a serial port,
hence the name. Since the serial port is not used as an async serial
port, the kernel driver for serial ports cannot be used, and this
driver only supports standard serial hardware (8250, 16450, 16550)
par96 This is a modem for 9600 baud FSK compatible to the G3RUH standard.
The modem does all the filtering and regenerates the receiver clock.
Data is transferred from and to the PC via a shift register.
The shift register is filled with 16 bits and an interrupt is signalled.
The PC then empties the shift register in a burst. This modem connects
to the parallel port, hence the name. The modem leaves the
implementation of the HDLC protocol and the scrambler polynomial to
the PC.
picpar This is a redesign of the par96 modem by Henning Rech, DF9IC. The modem
is protocol compatible to par96, but uses only three low power ICs
and can therefore be fed from the parallel port and does not require
an additional power supply. Furthermore, it incorporates a carrier
detect circuitry.
EPP This is a high-speed modem adaptor that connects to an enhanced parallel
port.
Its target audience is users working over a high speed hub (76.8kbit/s).
eppfpga This is a redesign of the EPP adaptor.
======= ========================================================================
All of the above modems only support half duplex communications. However,
the driver supports the KISS (see below) fullduplex command. It then simply
starts to send as soon as there's a packet to transmit and does not care
about DCD, i.e. it starts to send even if there's someone else on the channel.
This command is required by some implementations of the DAMA channel
access protocol.
The Interface of the drivers
============================
Unlike previous drivers, these drivers are no longer character devices,
but they are now true kernel network interfaces. Installation is therefore
simple. Once installed, four interfaces named bc{sf,sh,p,e}[0-3] are available.
sethdlc from the ax25 utilities may be used to set driver states etc.
Users of userland AX.25 stacks may use the net2kiss utility (also available
in the ax25 utilities package) to convert packets of a network interface
to a KISS stream on a pseudo tty. There's also a patch available from
me for WAMPES which allows attaching a kernel network interface directly.
Configuring the driver
======================
Every time a driver is inserted into the kernel, it has to know which
modems it should access at which ports. This can be done with the setbaycom
utility. If you are only using one modem, you can also configure the
driver from the insmod command line (or by means of an option line in
``/etc/modprobe.d/*.conf``).
Examples::
modprobe baycom_ser_fdx mode="ser12*" iobase=0x3f8 irq=4
sethdlc -i bcsf0 -p mode "ser12*" io 0x3f8 irq 4
Both lines configure the first port to drive a ser12 modem at the first
serial port (COM1 under DOS). The * in the mode parameter instructs the driver
to use the software DCD algorithm (see below)::
insmod baycom_par mode="picpar" iobase=0x378
sethdlc -i bcp0 -p mode "picpar" io 0x378
Both lines configure the first port to drive a picpar modem at the
first parallel port (LPT1 under DOS). (Note: picpar implies
hardware DCD, par96 implies software DCD).
The channel access parameters can be set with sethdlc -a or kissparms.
Note that both utilities interpret the values slightly differently.
Hardware DCD versus Software DCD
================================
To avoid collisions on the air, the driver must know when the channel is
busy. This is the task of the DCD circuitry/software. The driver may either
utilise a software DCD algorithm (options=1) or use a DCD signal from
the hardware (options=0).
======= =================================================================
ser12 if software DCD is utilised, the radio's squelch should always be
open. It is highly recommended to use the software DCD algorithm,
as it is much faster than most hardware squelch circuitry. The
disadvantage is a slightly higher load on the system.
par96 the software DCD algorithm for this type of modem is rather poor.
The modem simply does not provide enough information to implement
a reasonable DCD algorithm in software. Therefore, if your radio
feeds the DCD input of the PAR96 modem, the use of the hardware
DCD circuitry is recommended.
picpar the picpar modem features a builtin DCD hardware, which is highly
recommended.
======= =================================================================
Compatibility with the rest of the Linux kernel
===============================================
The serial driver and the baycom serial drivers compete
for the same hardware resources. Of course only one driver can access a given
interface at a time. The serial driver grabs all interfaces it can find at
startup time. Therefore the baycom drivers subsequently won't be able to
access a serial port. You might therefore find it necessary to release
a port owned by the serial driver with 'setserial /dev/ttyS# uart none', where
# is the number of the interface. The baycom drivers do not reserve any
ports at startup, unless one is specified on the 'insmod' command line. Another
method to solve the problem is to compile all drivers as modules and
leave it to kmod to load the correct driver depending on the application.
The parallel port drivers (baycom_par, baycom_epp) now use the parport subsystem
to arbitrate the ports between different client drivers.
vy 73s de
Tom Sailer, sailer@ife.ee.ethz.ch
hb9jnx @ hb9w.ampr.org

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.. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Amateur Radio Device Drivers
============================
Contents:
.. toctree::
:maxdepth: 2
baycom
z8530drv

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.. SPDX-License-Identifier: GPL-2.0
.. include:: <isonum.txt>
=========================================================
SCC.C - Linux driver for Z8530 based HDLC cards for AX.25
=========================================================
This is a subset of the documentation. To use this driver you MUST have the
full package from:
Internet:
1. ftp://ftp.ccac.rwth-aachen.de/pub/jr/z8530drv-utils_3.0-3.tar.gz
2. ftp://ftp.pspt.fi/pub/ham/linux/ax25/z8530drv-utils_3.0-3.tar.gz
Please note that the information in this document may be hopelessly outdated.
A new version of the documentation, along with links to other important
Linux Kernel AX.25 documentation and programs, is available on
http://yaina.de/jreuter
Copyright |copy| 1993,2000 by Joerg Reuter DL1BKE <jreuter@yaina.de>
portions Copyright |copy| 1993 Guido ten Dolle PE1NNZ
for the complete copyright notice see >> Copying.Z8530DRV <<
1. Initialization of the driver
===============================
To use the driver, 3 steps must be performed:
1. if compiled as module: loading the module
2. Setup of hardware, MODEM and KISS parameters with sccinit
3. Attach each channel to the Linux kernel AX.25 with "ifconfig"
Unlike the versions below 2.4 this driver is a real network device
driver. If you want to run xNOS instead of our fine kernel AX.25
use a 2.x version (available from above sites) or read the
AX.25-HOWTO on how to emulate a KISS TNC on network device drivers.
1.1 Loading the module
======================
(If you're going to compile the driver as a part of the kernel image,
skip this chapter and continue with 1.2)
Before you can use a module, you'll have to load it with::
insmod scc.o
please read 'man insmod' that comes with module-init-tools.
You should include the insmod in one of the /etc/rc.d/rc.* files,
and don't forget to insert a call of sccinit after that. It
will read your /etc/z8530drv.conf.
1.2. /etc/z8530drv.conf
=======================
To setup all parameters you must run /sbin/sccinit from one
of your rc.*-files. This has to be done BEFORE you can
"ifconfig" an interface. Sccinit reads the file /etc/z8530drv.conf
and sets the hardware, MODEM and KISS parameters. A sample file is
delivered with this package. Change it to your needs.
The file itself consists of two main sections.
1.2.1 configuration of hardware parameters
==========================================
The hardware setup section defines the following parameters for each
Z8530::
chip 1
data_a 0x300 # data port A
ctrl_a 0x304 # control port A
data_b 0x301 # data port B
ctrl_b 0x305 # control port B
irq 5 # IRQ No. 5
pclock 4915200 # clock
board BAYCOM # hardware type
escc no # enhanced SCC chip? (8580/85180/85280)
vector 0 # latch for interrupt vector
special no # address of special function register
option 0 # option to set via sfr
chip
- this is just a delimiter to make sccinit a bit simpler to
program. A parameter has no effect.
data_a
- the address of the data port A of this Z8530 (needed)
ctrl_a
- the address of the control port A (needed)
data_b
- the address of the data port B (needed)
ctrl_b
- the address of the control port B (needed)
irq
- the used IRQ for this chip. Different chips can use different
IRQs or the same. If they share an interrupt, it needs to be
specified within one chip-definition only.
pclock - the clock at the PCLK pin of the Z8530 (option, 4915200 is
default), measured in Hertz
board
- the "type" of the board:
======================= ========
SCC type value
======================= ========
PA0HZP SCC card PA0HZP
EAGLE card EAGLE
PC100 card PC100
PRIMUS-PC (DG9BL) card PRIMUS
BayCom (U)SCC card BAYCOM
======================= ========
escc
- if you want support for ESCC chips (8580, 85180, 85280), set
this to "yes" (option, defaults to "no")
vector
- address of the vector latch (aka "intack port") for PA0HZP
cards. There can be only one vector latch for all chips!
(option, defaults to 0)
special
- address of the special function register on several cards.
(option, defaults to 0)
option - The value you write into that register (option, default is 0)
You can specify up to four chips (8 channels). If this is not enough,
just change::
#define MAXSCC 4
to a higher value.
Example for the BAYCOM USCC:
----------------------------
::
chip 1
data_a 0x300 # data port A
ctrl_a 0x304 # control port A
data_b 0x301 # data port B
ctrl_b 0x305 # control port B
irq 5 # IRQ No. 5 (#)
board BAYCOM # hardware type (*)
#
# SCC chip 2
#
chip 2
data_a 0x302
ctrl_a 0x306
data_b 0x303
ctrl_b 0x307
board BAYCOM
An example for a PA0HZP card:
-----------------------------
::
chip 1
data_a 0x153
data_b 0x151
ctrl_a 0x152
ctrl_b 0x150
irq 9
pclock 4915200
board PA0HZP
vector 0x168
escc no
#
#
#
chip 2
data_a 0x157
data_b 0x155
ctrl_a 0x156
ctrl_b 0x154
irq 9
pclock 4915200
board PA0HZP
vector 0x168
escc no
A DRSI would should probably work with this:
--------------------------------------------
(actually: two DRSI cards...)
::
chip 1
data_a 0x303
data_b 0x301
ctrl_a 0x302
ctrl_b 0x300
irq 7
pclock 4915200
board DRSI
escc no
#
#
#
chip 2
data_a 0x313
data_b 0x311
ctrl_a 0x312
ctrl_b 0x310
irq 7
pclock 4915200
board DRSI
escc no
Note that you cannot use the on-board baudrate generator off DRSI
cards. Use "mode dpll" for clock source (see below).
This is based on information provided by Mike Bilow (and verified
by Paul Helay)
The utility "gencfg"
--------------------
If you only know the parameters for the PE1CHL driver for DOS,
run gencfg. It will generate the correct port addresses (I hope).
Its parameters are exactly the same as the ones you use with
the "attach scc" command in net, except that the string "init" must
not appear. Example::
gencfg 2 0x150 4 2 0 1 0x168 9 4915200
will print a skeleton z8530drv.conf for the OptoSCC to stdout.
::
gencfg 2 0x300 2 4 5 -4 0 7 4915200 0x10
does the same for the BAYCOM USCC card. In my opinion it is much easier
to edit scc_config.h...
1.2.2 channel configuration
===========================
The channel definition is divided into three sub sections for each
channel:
An example for scc0::
# DEVICE
device scc0 # the device for the following params
# MODEM / BUFFERS
speed 1200 # the default baudrate
clock dpll # clock source:
# dpll = normal half duplex operation
# external = MODEM provides own Rx/Tx clock
# divider = use full duplex divider if
# installed (1)
mode nrzi # HDLC encoding mode
# nrzi = 1k2 MODEM, G3RUH 9k6 MODEM
# nrz = DF9IC 9k6 MODEM
#
bufsize 384 # size of buffers. Note that this must include
# the AX.25 header, not only the data field!
# (optional, defaults to 384)
# KISS (Layer 1)
txdelay 36 # (see chapter 1.4)
persist 64
slot 8
tail 8
fulldup 0
wait 12
min 3
maxkey 7
idle 3
maxdef 120
group 0
txoff off
softdcd on
slip off
The order WITHIN these sections is unimportant. The order OF these
sections IS important. The MODEM parameters are set with the first
recognized KISS parameter...
Please note that you can initialize the board only once after boot
(or insmod). You can change all parameters but "mode" and "clock"
later with the Sccparam program or through KISS. Just to avoid
security holes...
(1) this divider is usually mounted on the SCC-PBC (PA0HZP) or not
present at all (BayCom). It feeds back the output of the DPLL
(digital pll) as transmit clock. Using this mode without a divider
installed will normally result in keying the transceiver until
maxkey expires --- of course without sending anything (useful).
2. Attachment of a channel by your AX.25 software
=================================================
2.1 Kernel AX.25
================
To set up an AX.25 device you can simply type::
ifconfig scc0 44.128.1.1 hw ax25 dl0tha-7
This will create a network interface with the IP number 44.128.20.107
and the callsign "dl0tha". If you do not have any IP number (yet) you
can use any of the 44.128.0.0 network. Note that you do not need
axattach. The purpose of axattach (like slattach) is to create a KISS
network device linked to a TTY. Please read the documentation of the
ax25-utils and the AX.25-HOWTO to learn how to set the parameters of
the kernel AX.25.
2.2 NOS, NET and TFKISS
=======================
Since the TTY driver (aka KISS TNC emulation) is gone you need
to emulate the old behaviour. The cost of using these programs is
that you probably need to compile the kernel AX.25, regardless of whether
you actually use it or not. First setup your /etc/ax25/axports,
for example::
9k6 dl0tha-9 9600 255 4 9600 baud port (scc3)
axlink dl0tha-15 38400 255 4 Link to NOS
Now "ifconfig" the scc device::
ifconfig scc3 44.128.1.1 hw ax25 dl0tha-9
You can now axattach a pseudo-TTY::
axattach /dev/ptys0 axlink
and start your NOS and attach /dev/ptys0 there. The problem is that
NOS is reachable only via digipeating through the kernel AX.25
(disastrous on a DAMA controlled channel). To solve this problem,
configure "rxecho" to echo the incoming frames from "9k6" to "axlink"
and outgoing frames from "axlink" to "9k6" and start::
rxecho
Or simply use "kissbridge" coming with z8530drv-utils::
ifconfig scc3 hw ax25 dl0tha-9
kissbridge scc3 /dev/ptys0
3. Adjustment and Display of parameters
=======================================
3.1 Displaying SCC Parameters:
==============================
Once a SCC channel has been attached, the parameter settings and
some statistic information can be shown using the param program::
dl1bke-u:~$ sccstat scc0
Parameters:
speed : 1200 baud
txdelay : 36
persist : 255
slottime : 0
txtail : 8
fulldup : 1
waittime : 12
mintime : 3 sec
maxkeyup : 7 sec
idletime : 3 sec
maxdefer : 120 sec
group : 0x00
txoff : off
softdcd : on
SLIP : off
Status:
HDLC Z8530 Interrupts Buffers
-----------------------------------------------------------------------
Sent : 273 RxOver : 0 RxInts : 125074 Size : 384
Received : 1095 TxUnder: 0 TxInts : 4684 NoSpace : 0
RxErrors : 1591 ExInts : 11776
TxErrors : 0 SpInts : 1503
Tx State : idle
The status info shown is:
============== ==============================================================
Sent number of frames transmitted
Received number of frames received
RxErrors number of receive errors (CRC, ABORT)
TxErrors number of discarded Tx frames (due to various reasons)
Tx State status of the Tx interrupt handler: idle/busy/active/tail (2)
RxOver number of receiver overruns
TxUnder number of transmitter underruns
RxInts number of receiver interrupts
TxInts number of transmitter interrupts
EpInts number of receiver special condition interrupts
SpInts number of external/status interrupts
Size maximum size of an AX.25 frame (*with* AX.25 headers!)
NoSpace number of times a buffer could not get allocated
============== ==============================================================
An overrun is abnormal. If lots of these occur, the product of
baudrate and number of interfaces is too high for the processing
power of your computer. NoSpace errors are unlikely to be caused by the
driver or the kernel AX.25.
3.2 Setting Parameters
======================
The setting of parameters of the emulated KISS TNC is done in the
same way in the SCC driver. You can change parameters by using
the kissparms program from the ax25-utils package or use the program
"sccparam"::
sccparam <device> <paramname> <decimal-|hexadecimal value>
You can change the following parameters:
=========== =====
param value
=========== =====
speed 1200
txdelay 36
persist 255
slottime 0
txtail 8
fulldup 1
waittime 12
mintime 3
maxkeyup 7
idletime 3
maxdefer 120
group 0x00
txoff off
softdcd on
SLIP off
=========== =====
The parameters have the following meaning:
speed:
The baudrate on this channel in bits/sec
Example: sccparam /dev/scc3 speed 9600
txdelay:
The delay (in units of 10 ms) after keying of the
transmitter, until the first byte is sent. This is usually
called "TXDELAY" in a TNC. When 0 is specified, the driver
will just wait until the CTS signal is asserted. This
assumes the presence of a timer or other circuitry in the
MODEM and/or transmitter, that asserts CTS when the
transmitter is ready for data.
A normal value of this parameter is 30-36.
Example: sccparam /dev/scc0 txd 20
persist:
This is the probability that the transmitter will be keyed
when the channel is found to be free. It is a value from 0
to 255, and the probability is (value+1)/256. The value
should be somewhere near 50-60, and should be lowered when
the channel is used more heavily.
Example: sccparam /dev/scc2 persist 20
slottime:
This is the time between samples of the channel. It is
expressed in units of 10 ms. About 200-300 ms (value 20-30)
seems to be a good value.
Example: sccparam /dev/scc0 slot 20
tail:
The time the transmitter will remain keyed after the last
byte of a packet has been transferred to the SCC. This is
necessary because the CRC and a flag still have to leave the
SCC before the transmitter is keyed down. The value depends
on the baudrate selected. A few character times should be
sufficient, e.g. 40ms at 1200 baud. (value 4)
The value of this parameter is in 10 ms units.
Example: sccparam /dev/scc2 4
full:
The full-duplex mode switch. This can be one of the following
values:
0: The interface will operate in CSMA mode (the normal
half-duplex packet radio operation)
1: Fullduplex mode, i.e. the transmitter will be keyed at
any time, without checking the received carrier. It
will be unkeyed when there are no packets to be sent.
2: Like 1, but the transmitter will remain keyed, also
when there are no packets to be sent. Flags will be
sent in that case, until a timeout (parameter 10)
occurs.
Example: sccparam /dev/scc0 fulldup off
wait:
The initial waittime before any transmit attempt, after the
frame has been queue for transmit. This is the length of
the first slot in CSMA mode. In full duplex modes it is
set to 0 for maximum performance.
The value of this parameter is in 10 ms units.
Example: sccparam /dev/scc1 wait 4
maxkey:
The maximal time the transmitter will be keyed to send
packets, in seconds. This can be useful on busy CSMA
channels, to avoid "getting a bad reputation" when you are
generating a lot of traffic. After the specified time has
elapsed, no new frame will be started. Instead, the trans-
mitter will be switched off for a specified time (parameter
min), and then the selected algorithm for keyup will be
started again.
The value 0 as well as "off" will disable this feature,
and allow infinite transmission time.
Example: sccparam /dev/scc0 maxk 20
min:
This is the time the transmitter will be switched off when
the maximum transmission time is exceeded.
Example: sccparam /dev/scc3 min 10
idle:
This parameter specifies the maximum idle time in full duplex
2 mode, in seconds. When no frames have been sent for this
time, the transmitter will be keyed down. A value of 0 is
has same result as the fullduplex mode 1. This parameter
can be disabled.
Example: sccparam /dev/scc2 idle off # transmit forever
maxdefer
This is the maximum time (in seconds) to wait for a free channel
to send. When this timer expires the transmitter will be keyed
IMMEDIATELY. If you love to get trouble with other users you
should set this to a very low value ;-)
Example: sccparam /dev/scc0 maxdefer 240 # 2 minutes
txoff:
When this parameter has the value 0, the transmission of packets
is enable. Otherwise it is disabled.
Example: sccparam /dev/scc2 txoff on
group:
It is possible to build special radio equipment to use more than
one frequency on the same band, e.g. using several receivers and
only one transmitter that can be switched between frequencies.
Also, you can connect several radios that are active on the same
band. In these cases, it is not possible, or not a good idea, to
transmit on more than one frequency. The SCC driver provides a
method to lock transmitters on different interfaces, using the
"param <interface> group <x>" command. This will only work when
you are using CSMA mode (parameter full = 0).
The number <x> must be 0 if you want no group restrictions, and
can be computed as follows to create restricted groups:
<x> is the sum of some OCTAL numbers:
=== =======================================================
200 This transmitter will only be keyed when all other
transmitters in the group are off.
100 This transmitter will only be keyed when the carrier
detect of all other interfaces in the group is off.
0xx A byte that can be used to define different groups.
Interfaces are in the same group, when the logical AND
between their xx values is nonzero.
=== =======================================================
Examples:
When 2 interfaces use group 201, their transmitters will never be
keyed at the same time.
When 2 interfaces use group 101, the transmitters will only key
when both channels are clear at the same time. When group 301,
the transmitters will not be keyed at the same time.
Don't forget to convert the octal numbers into decimal before
you set the parameter.
Example: (to be written)
softdcd:
use a software dcd instead of the real one... Useful for a very
slow squelch.
Example: sccparam /dev/scc0 soft on
4. Problems
===========
If you have tx-problems with your BayCom USCC card please check
the manufacturer of the 8530. SGS chips have a slightly
different timing. Try Zilog... A solution is to write to register 8
instead to the data port, but this won't work with the ESCC chips.
*SIGH!*
A very common problem is that the PTT locks until the maxkeyup timer
expires, although interrupts and clock source are correct. In most
cases compiling the driver with CONFIG_SCC_DELAY (set with
make config) solves the problems. For more hints read the (pseudo) FAQ
and the documentation coming with z8530drv-utils.
I got reports that the driver has problems on some 386-based systems.
(i.e. Amstrad) Those systems have a bogus AT bus timing which will
lead to delayed answers on interrupts. You can recognize these
problems by looking at the output of Sccstat for the suspected
port. If it shows under- and overruns you own such a system.
Delayed processing of received data: This depends on
- the kernel version
- kernel profiling compiled or not
- a high interrupt load
- a high load of the machine --- running X, Xmorph, XV and Povray,
while compiling the kernel... hmm ... even with 32 MB RAM ... ;-)
Or running a named for the whole .ampr.org domain on an 8 MB
box...
- using information from rxecho or kissbridge.
Kernel panics: please read /linux/README and find out if it
really occurred within the scc driver.
If you cannot solve a problem, send me
- a description of the problem,
- information on your hardware (computer system, scc board, modem)
- your kernel version
- the output of cat /proc/net/z8530
4. Thor RLC100
==============
Mysteriously this board seems not to work with the driver. Anyone
got it up-and-running?
Many thanks to Linus Torvalds and Alan Cox for including the driver
in the Linux standard distribution and their support.
::
Joerg Reuter ampr-net: dl1bke@db0pra.ampr.org
AX-25 : DL1BKE @ DB0ABH.#BAY.DEU.EU
Internet: jreuter@yaina.de
WWW : http://yaina.de/jreuter

1
Documentation/networking/device_drivers/index.rst
View File

@ -13,6 +13,5 @@ Contents:
cellular/index
ethernet/index
fddi/index
hamradio/index
wifi/index
wwan/index

3
Documentation/networking/index.rst
View File

@ -17,7 +17,6 @@ Contents:
diagnostic/index
dsa/index
devlink/index
caif/index
ethtool-netlink
ieee802154
iso15765-2
@ -41,11 +40,9 @@ Contents:
tls-handshake
nfc
6lowpan
6pack
arcnet-hardware
arcnet
atm
ax25
bonding
cdc_mbim
dctcp

3
Documentation/staging/magic-number.rst
View File

@ -72,11 +72,8 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/uapi/l
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip/slip.h``
BAYCOM_MAGIC 19730510 baycom_state ``drivers/net/hamradio/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
CODA_MAGIC 0xC0DAC0DA coda_file_info ``fs/coda/coda_fs_i.h``
YAM_MAGIC 0xF10A7654 yam_port ``drivers/net/hamradio/yam.c``
CCB_MAGIC 0xf2691ad2 ccb ``drivers/scsi/ncr53c8xx.c``
QUEUE_MAGIC_FREE 0xf7e1c9a3 queue_entry ``drivers/scsi/arm/queue.c``
QUEUE_MAGIC_USED 0xf7e1cc33 queue_entry ``drivers/scsi/arm/queue.c``

1
Documentation/subsystem-apis.rst
View File

@ -46,7 +46,6 @@ Networking interfaces
networking/index
netlabel/index
infiniband/index
isdn/index
mhi/index
Storage interfaces

3
Documentation/translations/it_IT/staging/magic-number.rst
View File

@ -78,11 +78,8 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
CODA_MAGIC 0xC0DAC0DA coda_file_info ``fs/coda/coda_fs_i.h``
YAM_MAGIC 0xF10A7654 yam_port ``drivers/net/hamradio/yam.c``
CCB_MAGIC 0xf2691ad2 ccb ``drivers/scsi/ncr53c8xx.c``
QUEUE_MAGIC_FREE 0xf7e1c9a3 queue_entry ``drivers/scsi/arm/queue.c``
QUEUE_MAGIC_USED 0xf7e1cc33 queue_entry ``drivers/scsi/arm/queue.c``

3
Documentation/translations/sp_SP/process/magic-number.rst
View File

@ -77,11 +77,8 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
CODA_MAGIC 0xC0DAC0DA coda_file_info ``fs/coda/coda_fs_i.h``
YAM_MAGIC 0xF10A7654 yam_port ``drivers/net/hamradio/yam.c``
CCB_MAGIC 0xf2691ad2 ccb ``drivers/scsi/ncr53c8xx.c``
QUEUE_MAGIC_FREE 0xf7e1c9a3 queue_entry ``drivers/scsi/arm/queue.c``
QUEUE_MAGIC_USED 0xf7e1cc33 queue_entry ``drivers/scsi/arm/queue.c``

1
Documentation/translations/zh_CN/networking/index.rst
View File

@ -42,7 +42,6 @@ Todolist:
* diagnostic/index
* dsa/index
* devlink/index
* caif/index
* ethtool-netlink
* ieee802154
* iso15765-2

3
Documentation/translations/zh_CN/process/magic-number.rst
View File

@ -70,11 +70,8 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
CODA_MAGIC 0xC0DAC0DA coda_file_info ``fs/coda/coda_fs_i.h``
YAM_MAGIC 0xF10A7654 yam_port ``drivers/net/hamradio/yam.c``
CCB_MAGIC 0xf2691ad2 ccb ``drivers/scsi/ncr53c8xx.c``
QUEUE_MAGIC_FREE 0xf7e1c9a3 queue_entry ``drivers/scsi/arm/queue.c``
QUEUE_MAGIC_USED 0xf7e1cc33 queue_entry ``drivers/scsi/arm/queue.c``

3
Documentation/translations/zh_TW/process/magic-number.rst
View File

@ -64,11 +64,8 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
CODA_MAGIC 0xC0DAC0DA coda_file_info ``fs/coda/coda_fs_i.h``
YAM_MAGIC 0xF10A7654 yam_port ``drivers/net/hamradio/yam.c``
CCB_MAGIC 0xf2691ad2 ccb ``drivers/scsi/ncr53c8xx.c``
QUEUE_MAGIC_FREE 0xf7e1c9a3 queue_entry ``drivers/scsi/arm/queue.c``
QUEUE_MAGIC_USED 0xf7e1cc33 queue_entry ``drivers/scsi/arm/queue.c``

105
MAINTAINERS
View File

@ -103,12 +103,6 @@ F: Documentation/networking/6lowpan.rst
F: include/net/6lowpan.h
F: net/6lowpan/
6PACK NETWORK DRIVER FOR AX.25
M: Andreas Koensgen <ajk@comnets.uni-bremen.de>
L: linux-hams@vger.kernel.org
S: Maintained
F: drivers/net/hamradio/6pack.c
802.11 (including CFG80211/NL80211)
M: Johannes Berg <johannes@sipsolutions.net>
L: linux-wireless@vger.kernel.org
@ -144,7 +138,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git
F: drivers/tty/serial/8250*
F: include/linux/serial_8250.h
8390 NETWORK DRIVERS [WD80x3/SMC-ELITE, SMC-ULTRA, NE2000, 3C503, etc.]
8390 NETWORK DRIVERS [NE2000, 3C503, etc.]
L: netdev@vger.kernel.org
S: Orphan / Obsolete
F: drivers/net/ethernet/8390/
@ -4158,10 +4152,12 @@ L: netdev@vger.kernel.org
S: Maintained
W: http://linux-atm.sourceforge.net
F: drivers/atm/
F: drivers/usb/atm/
F: include/linux/atm*
F: include/linux/sonet.h
F: include/uapi/linux/atm*
F: include/uapi/linux/sonet.h
F: net/atm/
ATMEL MACB ETHERNET DRIVER
M: Nicolas Ferre <nicolas.ferre@microchip.com>
@ -4281,14 +4277,6 @@ S: Maintained
F: Documentation/devicetree/bindings/leds/backlight/awinic,aw99706.yaml
F: drivers/video/backlight/aw99706.c
AX.25 NETWORK LAYER
L: linux-hams@vger.kernel.org
S: Orphan
W: https://linux-ax25.in-berlin.de
F: include/net/ax25.h
F: include/uapi/linux/ax25.h
F: net/ax25/
AXENTIA ARM DEVICES
M: Peter Rosin <peda@axentia.se>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -4430,13 +4418,6 @@ F: include/uapi/linux/batadv_packet.h
F: include/uapi/linux/batman_adv.h
F: net/batman-adv/
BAYCOM/HDLCDRV DRIVERS FOR AX.25
M: Thomas Sailer <t.sailer@alumni.ethz.ch>
L: linux-hams@vger.kernel.org
S: Maintained
W: http://www.baycom.org/~tom/ham/ham.html
F: drivers/net/hamradio/baycom*
BCACHE (BLOCK LAYER CACHE)
M: Coly Li <colyli@fnnas.com>
M: Kent Overstreet <kent.overstreet@linux.dev>
@ -5675,15 +5656,6 @@ T: git git://linuxtv.org/media.git
F: Documentation/admin-guide/media/cafe_ccic*
F: drivers/media/platform/marvell/
CAIF NETWORK LAYER
L: netdev@vger.kernel.org
S: Orphan
F: Documentation/networking/caif/
F: drivers/net/caif/
F: include/net/caif/
F: include/uapi/linux/caif/
F: net/caif/
CAKE QDISC
M: Toke Høiland-Jørgensen <toke@toke.dk>
L: cake@lists.bufferbloat.net (moderated for non-subscribers)
@ -7030,20 +7002,6 @@ S: Maintained
F: drivers/rtc/rtc-ds1685.c
F: include/linux/rtc/ds1685.h
DAMA SLAVE for AX.25
M: Joerg Reuter <jreuter@yaina.de>
L: linux-hams@vger.kernel.org
S: Maintained
W: http://yaina.de/jreuter/
W: http://www.qsl.net/dl1bke/
F: net/ax25/af_ax25.c
F: net/ax25/ax25_dev.c
F: net/ax25/ax25_ds_*
F: net/ax25/ax25_in.c
F: net/ax25/ax25_out.c
F: net/ax25/ax25_timer.c
F: net/ax25/sysctl_net_ax25.c
DASHARO ACPI PLATFORM DRIVER
M: Michał Kopeć <michal.kopec@3mdeb.com>
S: Maintained
@ -11523,11 +11481,6 @@ T: git https://github.com/Rust-for-Linux/linux.git timekeeping-next
F: rust/kernel/time.rs
F: rust/kernel/time/
HIGH-SPEED SCC DRIVER FOR AX.25
L: linux-hams@vger.kernel.org
S: Orphan
F: drivers/net/hamradio/scc.c
HIGHPOINT ROCKETRAID 3xxx RAID DRIVER
M: HighPoint Linux Team <linux@highpoint-tech.com>
S: Supported
@ -13677,25 +13630,6 @@ S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending.git master
F: drivers/infiniband/ulp/isert
ISDN/CMTP OVER BLUETOOTH
L: netdev@vger.kernel.org
S: Orphan
W: http://www.isdn4linux.de
F: Documentation/isdn/
F: drivers/isdn/capi/
F: include/linux/isdn/
F: include/uapi/linux/isdn/
F: net/bluetooth/cmtp/
ISDN/mISDN SUBSYSTEM
L: netdev@vger.kernel.org
S: Orphan
W: http://www.isdn4linux.de
F: drivers/isdn/Kconfig
F: drivers/isdn/Makefile
F: drivers/isdn/hardware/
F: drivers/isdn/mISDN/
ISL28022 HARDWARE MONITORING DRIVER
M: Carsten Spieß <mail@carsten-spiess.de>
L: linux-hwmon@vger.kernel.org
@ -18442,14 +18376,6 @@ F: net/bridge/br_netfilter*.c
F: net/netfilter/
F: tools/testing/selftests/net/netfilter/
NETROM NETWORK LAYER
L: linux-hams@vger.kernel.org
S: Orphan
W: https://linux-ax25.in-berlin.de
F: include/net/netrom.h
F: include/uapi/linux/netrom.h
F: net/netrom/
NETRONIX EMBEDDED CONTROLLER
M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
S: Maintained
@ -23284,14 +23210,6 @@ F: include/linux/mfd/rohm-bd96802.h
F: include/linux/mfd/rohm-generic.h
F: include/linux/mfd/rohm-shared.h
ROSE NETWORK LAYER
L: linux-hams@vger.kernel.org
S: Orphan
W: https://linux-ax25.in-berlin.de
F: include/net/rose.h
F: include/uapi/linux/rose.h
F: net/rose/
ROTATION DRIVER FOR ALLWINNER A83T
M: Jernej Skrabec <jernej.skrabec@gmail.com>
L: linux-media@vger.kernel.org
@ -29346,13 +29264,6 @@ F: lib/decompress_unxz.c
F: lib/xz/
F: scripts/xz_wrap.sh
YAM DRIVER FOR AX.25
M: Jean-Paul Roubelat <jpr@f6fbb.org>
L: linux-hams@vger.kernel.org
S: Maintained
F: drivers/net/hamradio/yam*
F: include/linux/yam.h
YAMA SECURITY MODULE
M: Kees Cook <kees@kernel.org>
S: Supported
@ -29374,16 +29285,6 @@ S: Maintained
F: Documentation/input/devices/yealink.rst
F: drivers/input/misc/yealink.*
Z8530 DRIVER FOR AX.25
M: Joerg Reuter <jreuter@yaina.de>
L: linux-hams@vger.kernel.org
S: Maintained
W: http://yaina.de/jreuter/
W: http://www.qsl.net/dl1bke/
F: Documentation/networking/device_drivers/hamradio/z8530drv.rst
F: drivers/net/hamradio/*scc.c
F: drivers/net/hamradio/z8530.h
ZD1211RW WIRELESS DRIVER
L: linux-wireless@vger.kernel.org
S: Orphan

1
arch/alpha/configs/defconfig
View File

@ -45,7 +45,6 @@ CONFIG_NET_TULIP=y
CONFIG_DE2104X=m
CONFIG_TULIP=y
CONFIG_TULIP_MMIO=y
CONFIG_YELLOWFIN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_RTC_CLASS=y

4
arch/arm/configs/ixp4xx_defconfig
View File

@ -52,9 +52,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
@ -108,7 +105,6 @@ CONFIG_ATA=y
CONFIG_PATA_IXP4XX_CF=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_ATM_TCP=m
CONFIG_IXP4XX_ETH=y
CONFIG_WAN=y
CONFIG_HDLC=y

1
arch/arm/configs/neponset_defconfig
View File

@ -40,7 +40,6 @@ CONFIG_BLK_DEV_SD=m
CONFIG_NETDEVICES=y
CONFIG_NET_VENDOR_SMC=y
CONFIG_PCMCIA_PCNET=y
CONFIG_SMC9194=y
CONFIG_SMC91X=y
CONFIG_NET_PCMCIA=y
# CONFIG_INPUT_MOUSE is not set

1
arch/arm/configs/u8500_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_CFG80211=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_MAC80211=y
CONFIG_MAC80211_LEDS=y
CONFIG_CAIF=y
CONFIG_NFC=m
CONFIG_NFC_HCI=m
CONFIG_NFC_SHDLC=y

1
arch/mips/configs/bcm47xx_defconfig
View File

@ -28,7 +28,6 @@ CONFIG_NETFILTER=y
CONFIG_VLAN_8021Q=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_HAMRADIO=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_MTD=y

10
arch/mips/configs/bigsur_defconfig
View File

@ -84,16 +84,6 @@ CONFIG_IP_VS_FTP=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_HAMRADIO=y
CONFIG_AX25=m
CONFIG_NETROM=m
CONFIG_ROSE=m
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
CONFIG_YAM=m
CONFIG_FW_LOADER=m
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_NBD=m

1
arch/mips/configs/db1xxx_defconfig
View File

@ -105,7 +105,6 @@ CONFIG_PATA_PCMCIA=y
CONFIG_PATA_PLATFORM=y
CONFIG_NETDEVICES=y
CONFIG_NLMON=y
CONFIG_PCMCIA_3C589=y
CONFIG_MIPS_AU1X00_ENET=y
CONFIG_SMC91X=y
CONFIG_SMSC911X=y

24
arch/mips/configs/gpr_defconfig
View File

@ -87,9 +87,6 @@ CONFIG_BRIDGE_EBT_LOG=m
CONFIG_IP_SCTP=m
CONFIG_TIPC=m
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
@ -104,7 +101,6 @@ CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
@ -130,17 +126,6 @@ CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_PKTGEN=m
CONFIG_HAMRADIO=y
CONFIG_AX25=m
# CONFIG_AX25_DAMA_SLAVE is not set
CONFIG_NETROM=m
CONFIG_ROSE=m
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
CONFIG_YAM=m
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_MTD=y
@ -167,15 +152,6 @@ CONFIG_SCSI_SAS_LIBSAS=m
CONFIG_NETDEVICES=y
CONFIG_NET_FC=y
CONFIG_NETCONSOLE=m
CONFIG_ATM_TCP=m
CONFIG_ATM_LANAI=m
CONFIG_ATM_ENI=m
CONFIG_ATM_NICSTAR=m
CONFIG_ATM_IDT77252=m
CONFIG_ATM_IA=m
CONFIG_ATM_FORE200E=m
CONFIG_ATM_HE=m
CONFIG_ATM_HE_USE_SUNI=y
CONFIG_MIPS_AU1X00_ENET=y
CONFIG_CICADA_PHY=m
CONFIG_DAVICOM_PHY=m

32
arch/mips/configs/mtx1_defconfig
View File

@ -132,9 +132,6 @@ CONFIG_BRIDGE_EBT_LOG=m
CONFIG_IP_SCTP=m
CONFIG_TIPC=m
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
@ -149,7 +146,6 @@ CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
@ -175,17 +171,6 @@ CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_PKTGEN=m
CONFIG_HAMRADIO=y
CONFIG_AX25=m
# CONFIG_AX25_DAMA_SLAVE is not set
CONFIG_NETROM=m
CONFIG_ROSE=m
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
CONFIG_YAM=m
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
@ -242,23 +227,11 @@ CONFIG_ARCNET_RIM_I=m
CONFIG_ARCNET_COM20020=m
CONFIG_ARCNET_COM20020_PCI=m
CONFIG_ARCNET_COM20020_CS=m
CONFIG_ATM_TCP=m
CONFIG_ATM_LANAI=m
CONFIG_ATM_ENI=m
CONFIG_ATM_NICSTAR=m
CONFIG_ATM_IDT77252=m
CONFIG_ATM_IA=m
CONFIG_ATM_FORE200E=m
CONFIG_ATM_HE=m
CONFIG_ATM_HE_USE_SUNI=y
CONFIG_PCMCIA_3C574=m
CONFIG_PCMCIA_3C589=m
CONFIG_VORTEX=m
CONFIG_TYPHOON=m
CONFIG_ADAPTEC_STARFIRE=m
CONFIG_AMD8111_ETH=m
CONFIG_PCNET32=m
CONFIG_PCMCIA_NMCLAN=m
CONFIG_B44=m
CONFIG_BNX2=m
CONFIG_TIGON3=m
@ -272,7 +245,6 @@ CONFIG_ULI526X=m
CONFIG_PCMCIA_XIRCOM=m
CONFIG_DL2K=m
CONFIG_SUNDANCE=m
CONFIG_PCMCIA_FMVJ18X=m
CONFIG_E100=m
CONFIG_E1000=m
CONFIG_SKGE=m
@ -281,12 +253,9 @@ CONFIG_MYRI10GE=m
CONFIG_FEALNX=m
CONFIG_NATSEMI=m
CONFIG_NS83820=m
CONFIG_PCMCIA_AXNET=m
CONFIG_NE2K_PCI=m
CONFIG_PCMCIA_PCNET=m
CONFIG_FORCEDETH=m
CONFIG_HAMACHI=m
CONFIG_YELLOWFIN=m
CONFIG_QLA3XXX=m
CONFIG_8139CP=m
CONFIG_8139TOO=m
@ -295,7 +264,6 @@ CONFIG_8139TOO_8129=y
CONFIG_R8169=m
CONFIG_SIS900=m
CONFIG_SIS190=m
CONFIG_PCMCIA_SMC91C92=m
CONFIG_EPIC100=m
CONFIG_HAPPYMEAL=m
CONFIG_SUNGEM=m

1
arch/mips/configs/rb532_defconfig
View File

@ -95,7 +95,6 @@ CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_HAMRADIO=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_BLOCK2MTD=y

7
arch/mips/configs/rm200_defconfig
View File

@ -147,13 +147,6 @@ CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_HAMRADIO=y
CONFIG_AX25=m
CONFIG_NETROM=m
CONFIG_ROSE=m
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_CONNECTOR=m
CONFIG_PARPORT=m
CONFIG_PARPORT_PC=m

1
arch/mips/configs/rt305x_defconfig
View File

@ -64,7 +64,6 @@ CONFIG_BRIDGE=y
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
CONFIG_VLAN_8021Q=y
CONFIG_NET_SCHED=y
CONFIG_HAMRADIO=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y

1
arch/mips/configs/xway_defconfig
View File

@ -66,7 +66,6 @@ CONFIG_BRIDGE=y
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
CONFIG_VLAN_8021Q=y
CONFIG_NET_SCHED=y
CONFIG_HAMRADIO=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y

19
arch/powerpc/configs/ppc6xx_defconfig
View File

@ -225,8 +225,6 @@ CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_TIPC=m
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
CONFIG_ATM_LANE=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
@ -238,7 +236,6 @@ CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
@ -396,21 +393,11 @@ CONFIG_NETCONSOLE=m
CONFIG_TUN=m
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_ATM_TCP=m
CONFIG_ATM_LANAI=m
CONFIG_ATM_ENI=m
CONFIG_ATM_NICSTAR=m
CONFIG_ATM_IDT77252=m
CONFIG_ATM_HE=m
CONFIG_EL3=m
CONFIG_PCMCIA_3C574=m
CONFIG_PCMCIA_3C589=m
CONFIG_VORTEX=m
CONFIG_TYPHOON=m
CONFIG_ADAPTEC_STARFIRE=m
CONFIG_AMD8111_ETH=m
CONFIG_PCNET32=m
CONFIG_PCMCIA_NMCLAN=m
CONFIG_MACE=m
CONFIG_BMAC=m
CONFIG_ATL1=m
@ -433,7 +420,6 @@ CONFIG_DL2K=m
CONFIG_SUNDANCE=m
CONFIG_FEC_MPC52xx=m
CONFIG_GIANFAR=m
CONFIG_PCMCIA_FMVJ18X=m
CONFIG_E100=m
CONFIG_E1000=m
CONFIG_E1000E=m
@ -446,14 +432,10 @@ CONFIG_MYRI10GE=m
CONFIG_FEALNX=m
CONFIG_NATSEMI=m
CONFIG_NS83820=m
CONFIG_PCMCIA_AXNET=m
CONFIG_NE2000=m
CONFIG_NE2K_PCI=m
CONFIG_PCMCIA_PCNET=m
CONFIG_ULTRA=m
CONFIG_FORCEDETH=m
CONFIG_HAMACHI=m
CONFIG_YELLOWFIN=m
CONFIG_QLA3XXX=m
CONFIG_NETXEN_NIC=m
CONFIG_8139CP=m
@ -466,7 +448,6 @@ CONFIG_SC92031=m
CONFIG_SIS900=m
CONFIG_SIS190=m
CONFIG_SFC=m
CONFIG_PCMCIA_SMC91C92=m
CONFIG_EPIC100=m
CONFIG_HAPPYMEAL=m
CONFIG_SUNGEM=m

2
drivers/Kconfig
View File

@ -61,8 +61,6 @@ source "drivers/macintosh/Kconfig"
source "drivers/net/Kconfig"
source "drivers/isdn/Kconfig"
# input before char - char/joystick depends on it. As does USB.
source "drivers/input/Kconfig"

1
drivers/Makefile
View File

@ -124,7 +124,6 @@ obj-$(CONFIG_WATCHDOG) += watchdog/
obj-$(CONFIG_MD) += md/
obj-$(CONFIG_BT) += bluetooth/
obj-$(CONFIG_ACCESSIBILITY) += accessibility/
obj-$(CONFIG_ISDN) += isdn/
obj-$(CONFIG_EDAC) += edac/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_PM_OPP) += opp/

5
drivers/atm/.gitignore vendored
View File

@ -1,5 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
fore200e_mkfirm
fore200e_pca_fw.c
pca200e.bin
pca200e_ecd.bin2

300
drivers/atm/Kconfig
View File

@ -15,306 +15,6 @@ menuconfig ATM_DRIVERS
if ATM_DRIVERS && NETDEVICES && ATM
config ATM_DUMMY
tristate "Dummy ATM driver"
help
Dummy ATM driver. Useful for proxy signalling, testing,
and development. If unsure, say N.
config ATM_TCP
tristate "ATM over TCP"
depends on INET
help
ATM over TCP driver. Useful mainly for development and for
experiments. If unsure, say N.
config ATM_LANAI
tristate "Efficient Networks Speedstream 3010"
depends on PCI && ATM
help
Supports ATM cards based on the Efficient Networks "Lanai"
chipset such as the Speedstream 3010 and the ENI-25p. The
Speedstream 3060 is currently not supported since we don't
have the code to drive the on-board Alcatel DSL chipset (yet).
config ATM_ENI
tristate "Efficient Networks ENI155P"
depends on PCI
help
Driver for the Efficient Networks ENI155p series and SMC ATM
Power155 155 Mbps ATM adapters. Both, the versions with 512KB and
2MB on-board RAM (Efficient calls them "C" and "S", respectively),
and the FPGA and the ASIC Tonga versions of the board are supported.
The driver works with MMF (-MF or ...F) and UTP-5 (-U5 or ...D)
adapters.
To compile this driver as a module, choose M here: the module will
be called eni.
config ATM_ENI_DEBUG
bool "Enable extended debugging"
depends on ATM_ENI
help
Extended debugging records various events and displays that list
when an inconsistency is detected. This mechanism is faster than
generally using printks, but still has some impact on performance.
Note that extended debugging may create certain race conditions
itself. Enable this ONLY if you suspect problems with the driver.
config ATM_ENI_TUNE_BURST
bool "Fine-tune burst settings"
depends on ATM_ENI
help
In order to obtain good throughput, the ENI NIC can transfer
multiple words of data per PCI bus access cycle. Such a multi-word
transfer is called a burst.
The default settings for the burst sizes are suitable for most PCI
chipsets. However, in some cases, large bursts may overrun buffers
in the PCI chipset and cause data corruption. In such cases, large
bursts must be disabled and only (slower) small bursts can be used.
The burst sizes can be set independently in the send (TX) and
receive (RX) direction.
Note that enabling many different burst sizes in the same direction
may increase the cost of setting up a transfer such that the
resulting throughput is lower than when using only the largest
available burst size.
Also, sometimes larger bursts lead to lower throughput, e.g. on an
Intel 440FX board, a drop from 135 Mbps to 103 Mbps was observed
when going from 8W to 16W bursts.
config ATM_ENI_BURST_TX_16W
bool "Enable 16W TX bursts (discouraged)"
depends on ATM_ENI_TUNE_BURST
help
Burst sixteen words at once in the send direction. This may work
with recent PCI chipsets, but is known to fail with older chipsets.
config ATM_ENI_BURST_TX_8W
bool "Enable 8W TX bursts (recommended)"
depends on ATM_ENI_TUNE_BURST
help
Burst eight words at once in the send direction. This is the default
setting.
config ATM_ENI_BURST_TX_4W
bool "Enable 4W TX bursts (optional)"
depends on ATM_ENI_TUNE_BURST
help
Burst four words at once in the send direction. You may want to try
this if you have disabled 8W bursts. Enabling 4W if 8W is also set
may or may not improve throughput.
config ATM_ENI_BURST_TX_2W
bool "Enable 2W TX bursts (optional)"
depends on ATM_ENI_TUNE_BURST
help
Burst two words at once in the send direction. You may want to try
this if you have disabled 4W and 8W bursts. Enabling 2W if 4W or 8W
are also set may or may not improve throughput.
config ATM_ENI_BURST_RX_16W
bool "Enable 16W RX bursts (discouraged)"
depends on ATM_ENI_TUNE_BURST
help
Burst sixteen words at once in the receive direction. This may work
with recent PCI chipsets, but is known to fail with older chipsets.
config ATM_ENI_BURST_RX_8W
bool "Enable 8W RX bursts (discouraged)"
depends on ATM_ENI_TUNE_BURST
help
Burst eight words at once in the receive direction. This may work
with recent PCI chipsets, but is known to fail with older chipsets,
such as the Intel Neptune series.
config ATM_ENI_BURST_RX_4W
bool "Enable 4W RX bursts (recommended)"
depends on ATM_ENI_TUNE_BURST
help
Burst four words at once in the receive direction. This is the
default setting. Enabling 4W if 8W is also set may or may not
improve throughput.
config ATM_ENI_BURST_RX_2W
bool "Enable 2W RX bursts (optional)"
depends on ATM_ENI_TUNE_BURST
help
Burst two words at once in the receive direction. You may want to
try this if you have disabled 4W and 8W bursts. Enabling 2W if 4W or
8W are also set may or may not improve throughput.
config ATM_NICSTAR
tristate "IDT 77201 (NICStAR) (ForeRunnerLE)"
depends on PCI
help
The NICStAR chipset family is used in a large number of ATM NICs for
25 and for 155 Mbps, including IDT cards and the Fore ForeRunnerLE
series. Say Y if you have one of those.
To compile this driver as a module, choose M here: the module will
be called nicstar.
config ATM_NICSTAR_USE_SUNI
bool "Use suni PHY driver (155Mbps)"
depends on ATM_NICSTAR
help
Support for the S-UNI and compatible PHYsical layer chips. These are
found in most 155Mbps NICStAR based ATM cards, namely in the
ForeRunner LE155 cards. This driver provides detection of cable~
removal and reinsertion and provides some statistics. This driver
doesn't have removal capability when compiled as a module, so if you
need that capability don't include S-UNI support (it's not needed to
make the card work).
config ATM_NICSTAR_USE_IDT77105
bool "Use IDT77105 PHY driver (25Mbps)"
depends on ATM_NICSTAR
help
Support for the PHYsical layer chip in ForeRunner LE25 cards. In
addition to cable removal/reinsertion detection, this driver allows
you to control the loopback mode of the chip via a dedicated IOCTL.
This driver is required for proper handling of temporary carrier
loss, so if you have a 25Mbps NICStAR based ATM card you must say Y.
config ATM_IDT77252
tristate "IDT 77252 (NICStAR II)"
depends on PCI
help
Driver for the IDT 77252 ATM PCI chips.
To compile this driver as a module, choose M here: the module will
be called idt77252.
config ATM_IDT77252_DEBUG
bool "Enable debugging messages"
depends on ATM_IDT77252
help
Somewhat useful debugging messages are available. The choice of
messages is controlled by a bitmap. This may be specified as a
module argument. See the file <file:drivers/atm/idt77252.h> for
the meanings of the bits in the mask.
When active, these messages can have a significant impact on the
speed of the driver, and the size of your syslog files! When
inactive, they will have only a modest impact on performance.
config ATM_IDT77252_RCV_ALL
bool "Receive ALL cells in raw queue"
depends on ATM_IDT77252
help
Enable receiving of all cells on the ATM link, that do not match
an open connection in the raw cell queue of the driver. Useful
for debugging or special applications only, so the safe answer is N.
config ATM_IDT77252_USE_SUNI
bool
depends on ATM_IDT77252
default y
config ATM_IA
tristate "Interphase ATM PCI x575/x525/x531"
depends on PCI
help
This is a driver for the Interphase (i)ChipSAR adapter cards
which include a variety of variants in term of the size of the
control memory (128K-1KVC, 512K-4KVC), the size of the packet
memory (128K, 512K, 1M), and the PHY type (Single/Multi mode OC3,
UTP155, UTP25, DS3 and E3). Go to:
<http://www.iphase.com/>
for more info about the cards. Say Y (or M to compile as a module
named iphase) here if you have one of these cards.
See the file
<file:Documentation/networking/device_drivers/atm/iphase.rst>
for further details.
config ATM_IA_DEBUG
bool "Enable debugging messages"
depends on ATM_IA
help
Somewhat useful debugging messages are available. The choice of
messages is controlled by a bitmap. This may be specified as a
module argument (kernel command line argument as well?), changed
dynamically using an ioctl (Get the debug utility, iadbg, from
<ftp://ftp.iphase.com/pub/atm/pci/>).
See the file <file:drivers/atm/iphase.h> for the meanings of the
bits in the mask.
When active, these messages can have a significant impact on the
speed of the driver, and the size of your syslog files! When
inactive, they will have only a modest impact on performance.
config ATM_FORE200E
tristate "FORE Systems 200E-series"
depends on (PCI || SBUS)
select FW_LOADER
help
This is a driver for the FORE Systems 200E-series ATM adapter
cards. It simultaneously supports PCA-200E and SBA-200E models
on PCI and SBUS hosts. Say Y (or M to compile as a module
named fore_200e) here if you have one of these ATM adapters.
See the file
<file:Documentation/networking/device_drivers/atm/fore200e.rst> for
further details.
config ATM_FORE200E_USE_TASKLET
bool "Defer interrupt work to a tasklet"
depends on ATM_FORE200E
default n
help
This defers work to be done by the interrupt handler to a
tasklet instead of handling everything at interrupt time. This
may improve the responsive of the host.
config ATM_FORE200E_TX_RETRY
int "Maximum number of tx retries"
depends on ATM_FORE200E
default "16"
help
Specifies the number of times the driver attempts to transmit
a message before giving up, if the transmit queue of the ATM card
is transiently saturated.
Saturation of the transmit queue may occur only under extreme
conditions, e.g. when a fast host continuously submits very small
frames (<64 bytes) or raw AAL0 cells (48 bytes) to the ATM adapter.
Note that under common conditions, it is unlikely that you encounter
a saturation of the transmit queue, so the retry mechanism never
comes into play.
config ATM_FORE200E_DEBUG
int "Debugging level (0-3)"
depends on ATM_FORE200E
default "0"
help
Specifies the level of debugging messages issued by the driver.
The verbosity of the driver increases with the value of this
parameter.
When active, these messages can have a significant impact on
the performances of the driver, and the size of your syslog files!
Keep the debugging level to 0 during normal operations.
config ATM_HE
tristate "ForeRunner HE Series"
depends on PCI
help
This is a driver for the Marconi ForeRunner HE-series ATM adapter
cards. It simultaneously supports the 155 and 622 versions.
config ATM_HE_USE_SUNI
bool "Use S/UNI PHY driver"
depends on ATM_HE
help
Support for the S/UNI-Ultra and S/UNI-622 found in the ForeRunner
HE cards. This driver provides carrier detection some statistics.
config ATM_SOLOS
tristate "Solos ADSL2+ PCI Multiport card driver"
depends on PCI

29
drivers/atm/Makefile
View File

@ -1,32 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the Linux network (ATM) device drivers.
#
fore_200e-y := fore200e.o
obj-$(CONFIG_ATM_NICSTAR) += nicstar.o
obj-$(CONFIG_ATM_IA) += iphase.o suni.o
obj-$(CONFIG_ATM_FORE200E) += fore_200e.o
obj-$(CONFIG_ATM_ENI) += eni.o suni.o
obj-$(CONFIG_ATM_IDT77252) += idt77252.o
obj-$(CONFIG_ATM_SOLOS) += solos-pci.o
ifeq ($(CONFIG_ATM_NICSTAR_USE_SUNI),y)
obj-$(CONFIG_ATM_NICSTAR) += suni.o
endif
ifeq ($(CONFIG_ATM_NICSTAR_USE_IDT77105),y)
obj-$(CONFIG_ATM_NICSTAR) += idt77105.o
endif
ifeq ($(CONFIG_ATM_IDT77252_USE_SUNI),y)
obj-$(CONFIG_ATM_IDT77252) += suni.o
endif
obj-$(CONFIG_ATM_DUMMY) += adummy.o
obj-$(CONFIG_ATM_TCP) += atmtcp.o
obj-$(CONFIG_ATM_LANAI) += lanai.o
obj-$(CONFIG_ATM_HE) += he.o
ifeq ($(CONFIG_ATM_HE_USE_SUNI),y)
obj-$(CONFIG_ATM_HE) += suni.o
endif

202
drivers/atm/adummy.c
View File

@ -1,202 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* adummy.c: a dummy ATM driver
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/skbuff.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <linux/uaccess.h>
#include <linux/atmdev.h>
#include <linux/atm.h>
#include <linux/sonet.h>
/* version definition */
#define DRV_VERSION "1.0"
#define DEV_LABEL "adummy"
#define ADUMMY_DEV(dev) ((struct adummy_dev *) (dev)->dev_data)
struct adummy_dev {
struct atm_dev *atm_dev;
struct list_head entry;
};
/* globals */
static LIST_HEAD(adummy_devs);
static ssize_t __set_signal(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct atm_dev *atm_dev = container_of(dev, struct atm_dev, class_dev);
int signal;
if (sscanf(buf, "%d", &signal) == 1) {
if (signal < ATM_PHY_SIG_LOST || signal > ATM_PHY_SIG_FOUND)
signal = ATM_PHY_SIG_UNKNOWN;
atm_dev_signal_change(atm_dev, signal);
return 1;
}
return -EINVAL;
}
static ssize_t __show_signal(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct atm_dev *atm_dev = container_of(dev, struct atm_dev, class_dev);
return sprintf(buf, "%d\n", atm_dev->signal);
}
static DEVICE_ATTR(signal, 0644, __show_signal, __set_signal);
static struct attribute *adummy_attrs[] = {
&dev_attr_signal.attr,
NULL
};
static const struct attribute_group adummy_group_attrs = {
.name = NULL, /* We want them in dev's root folder */
.attrs = adummy_attrs
};
static int __init
adummy_start(struct atm_dev *dev)
{
dev->ci_range.vpi_bits = 4;
dev->ci_range.vci_bits = 12;
return 0;
}
static int
adummy_open(struct atm_vcc *vcc)
{
short vpi = vcc->vpi;
int vci = vcc->vci;
if (vci == ATM_VCI_UNSPEC || vpi == ATM_VPI_UNSPEC)
return 0;
set_bit(ATM_VF_ADDR, &vcc->flags);
set_bit(ATM_VF_READY, &vcc->flags);
return 0;
}
static void
adummy_close(struct atm_vcc *vcc)
{
clear_bit(ATM_VF_READY, &vcc->flags);
clear_bit(ATM_VF_ADDR, &vcc->flags);
}
static int
adummy_send(struct atm_vcc *vcc, struct sk_buff *skb)
{
if (vcc->pop)
vcc->pop(vcc, skb);
else
dev_kfree_skb_any(skb);
atomic_inc(&vcc->stats->tx);
return 0;
}
static int
adummy_proc_read(struct atm_dev *dev, loff_t *pos, char *page)
{
int left = *pos;
if (!left--)
return sprintf(page, "version %s\n", DRV_VERSION);
return 0;
}
static const struct atmdev_ops adummy_ops =
{
.open = adummy_open,
.close = adummy_close,
.send = adummy_send,
.proc_read = adummy_proc_read,
.owner = THIS_MODULE
};
static int __init adummy_init(void)
{
struct atm_dev *atm_dev;
struct adummy_dev *adummy_dev;
int err = 0;
printk(KERN_ERR "adummy: version %s\n", DRV_VERSION);
adummy_dev = kzalloc_obj(struct adummy_dev);
if (!adummy_dev) {
printk(KERN_ERR DEV_LABEL ": kzalloc() failed\n");
err = -ENOMEM;
goto out;
}
atm_dev = atm_dev_register(DEV_LABEL, NULL, &adummy_ops, -1, NULL);
if (!atm_dev) {
printk(KERN_ERR DEV_LABEL ": atm_dev_register() failed\n");
err = -ENODEV;
goto out_kfree;
}
adummy_dev->atm_dev = atm_dev;
atm_dev->dev_data = adummy_dev;
if (sysfs_create_group(&atm_dev->class_dev.kobj, &adummy_group_attrs))
dev_err(&atm_dev->class_dev, "Could not register attrs for adummy\n");
if (adummy_start(atm_dev)) {
printk(KERN_ERR DEV_LABEL ": adummy_start() failed\n");
err = -ENODEV;
goto out_unregister;
}
list_add(&adummy_dev->entry, &adummy_devs);
out:
return err;
out_unregister:
atm_dev_deregister(atm_dev);
out_kfree:
kfree(adummy_dev);
goto out;
}
static void __exit adummy_cleanup(void)
{
struct adummy_dev *adummy_dev, *next;
list_for_each_entry_safe(adummy_dev, next, &adummy_devs, entry) {
atm_dev_deregister(adummy_dev->atm_dev);
kfree(adummy_dev);
}
}
module_init(adummy_init);
module_exit(adummy_cleanup);
MODULE_AUTHOR("chas williams <chas@cmf.nrl.navy.mil>");
MODULE_DESCRIPTION("dummy ATM driver");
MODULE_LICENSE("GPL");

513
drivers/atm/atmtcp.c
View File

@ -1,513 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* drivers/atm/atmtcp.c - ATM over TCP "device" driver */
/* Written 1997-2000 by Werner Almesberger, EPFL LRC/ICA */
#include <linux/module.h>
#include <linux/wait.h>
#include <linux/atmdev.h>
#include <linux/atm_tcp.h>
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/atomic.h>
extern int atm_init_aal5(struct atm_vcc *vcc); /* "raw" AAL5 transport */
#define PRIV(dev) ((struct atmtcp_dev_data *) ((dev)->dev_data))
struct atmtcp_dev_data {
struct atm_vcc *vcc; /* control VCC; NULL if detached */
int persist; /* non-zero if persistent */
};
#define DEV_LABEL "atmtcp"
#define MAX_VPI_BITS 8 /* simplifies life */
#define MAX_VCI_BITS 16
/*
* Hairy code ahead: the control VCC may be closed while we're still
* waiting for an answer, so we need to re-validate out_vcc every once
* in a while.
*/
static int atmtcp_send_control(struct atm_vcc *vcc,int type,
const struct atmtcp_control *msg,int flag)
{
DECLARE_WAITQUEUE(wait,current);
struct atm_vcc *out_vcc;
struct sk_buff *skb;
struct atmtcp_control *new_msg;
int old_test;
int error = 0;
out_vcc = PRIV(vcc->dev) ? PRIV(vcc->dev)->vcc : NULL;
if (!out_vcc) return -EUNATCH;
skb = alloc_skb(sizeof(*msg),GFP_KERNEL);
if (!skb) return -ENOMEM;
mb();
out_vcc = PRIV(vcc->dev) ? PRIV(vcc->dev)->vcc : NULL;
if (!out_vcc) {
dev_kfree_skb(skb);
return -EUNATCH;
}
atm_force_charge(out_vcc,skb->truesize);
new_msg = skb_put(skb, sizeof(*new_msg));
*new_msg = *msg;
new_msg->hdr.length = ATMTCP_HDR_MAGIC;
new_msg->type = type;
memset(&new_msg->vcc,0,sizeof(atm_kptr_t));
*(struct atm_vcc **) &new_msg->vcc = vcc;
old_test = test_bit(flag,&vcc->flags);
out_vcc->push(out_vcc,skb);
add_wait_queue(sk_sleep(sk_atm(vcc)), &wait);
while (test_bit(flag,&vcc->flags) == old_test) {
mb();
out_vcc = PRIV(vcc->dev) ? PRIV(vcc->dev)->vcc : NULL;
if (!out_vcc) {
error = -EUNATCH;
break;
}
set_current_state(TASK_UNINTERRUPTIBLE);
schedule();
}
set_current_state(TASK_RUNNING);
remove_wait_queue(sk_sleep(sk_atm(vcc)), &wait);
return error;
}
static int atmtcp_recv_control(const struct atmtcp_control *msg)
{
struct atm_vcc *vcc = *(struct atm_vcc **) &msg->vcc;
vcc->vpi = msg->addr.sap_addr.vpi;
vcc->vci = msg->addr.sap_addr.vci;
vcc->qos = msg->qos;
sk_atm(vcc)->sk_err = -msg->result;
switch (msg->type) {
case ATMTCP_CTRL_OPEN:
change_bit(ATM_VF_READY,&vcc->flags);
break;
case ATMTCP_CTRL_CLOSE:
change_bit(ATM_VF_ADDR,&vcc->flags);
break;
default:
printk(KERN_ERR "atmtcp_recv_control: unknown type %d\n",
msg->type);
return -EINVAL;
}
wake_up(sk_sleep(sk_atm(vcc)));
return 0;
}
static void atmtcp_v_dev_close(struct atm_dev *dev)
{
/* Nothing.... Isn't this simple :-) -- REW */
}
static int atmtcp_v_open(struct atm_vcc *vcc)
{
struct atmtcp_control msg;
int error;
short vpi = vcc->vpi;
int vci = vcc->vci;
memset(&msg,0,sizeof(msg));
msg.addr.sap_family = AF_ATMPVC;
msg.hdr.vpi = htons(vpi);
msg.addr.sap_addr.vpi = vpi;
msg.hdr.vci = htons(vci);
msg.addr.sap_addr.vci = vci;
if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) return 0;
msg.type = ATMTCP_CTRL_OPEN;
msg.qos = vcc->qos;
set_bit(ATM_VF_ADDR,&vcc->flags);
clear_bit(ATM_VF_READY,&vcc->flags); /* just in case ... */
error = atmtcp_send_control(vcc,ATMTCP_CTRL_OPEN,&msg,ATM_VF_READY);
if (error) return error;
return -sk_atm(vcc)->sk_err;
}
static void atmtcp_v_close(struct atm_vcc *vcc)
{
struct atmtcp_control msg;
memset(&msg,0,sizeof(msg));
msg.addr.sap_family = AF_ATMPVC;
msg.addr.sap_addr.vpi = vcc->vpi;
msg.addr.sap_addr.vci = vcc->vci;
clear_bit(ATM_VF_READY,&vcc->flags);
(void) atmtcp_send_control(vcc,ATMTCP_CTRL_CLOSE,&msg,ATM_VF_ADDR);
}
static int atmtcp_v_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
{
struct atm_cirange ci;
struct atm_vcc *vcc;
struct sock *s;
int i;
if (cmd != ATM_SETCIRANGE) return -ENOIOCTLCMD;
if (copy_from_user(&ci, arg,sizeof(ci))) return -EFAULT;
if (ci.vpi_bits == ATM_CI_MAX) ci.vpi_bits = MAX_VPI_BITS;
if (ci.vci_bits == ATM_CI_MAX) ci.vci_bits = MAX_VCI_BITS;
if (ci.vpi_bits > MAX_VPI_BITS || ci.vpi_bits < 0 ||
ci.vci_bits > MAX_VCI_BITS || ci.vci_bits < 0) return -EINVAL;
read_lock(&vcc_sklist_lock);
for(i = 0; i < VCC_HTABLE_SIZE; ++i) {
struct hlist_head *head = &vcc_hash[i];
sk_for_each(s, head) {
vcc = atm_sk(s);
if (vcc->dev != dev)
continue;
if ((vcc->vpi >> ci.vpi_bits) ||
(vcc->vci >> ci.vci_bits)) {
read_unlock(&vcc_sklist_lock);
return -EBUSY;
}
}
}
read_unlock(&vcc_sklist_lock);
dev->ci_range = ci;
return 0;
}
static int atmtcp_v_send(struct atm_vcc *vcc,struct sk_buff *skb)
{
struct atmtcp_dev_data *dev_data;
struct atm_vcc *out_vcc=NULL; /* Initializer quietens GCC warning */
struct sk_buff *new_skb;
struct atmtcp_hdr *hdr;
int size;
if (vcc->qos.txtp.traffic_class == ATM_NONE) {
if (vcc->pop) vcc->pop(vcc,skb);
else dev_kfree_skb(skb);
return -EINVAL;
}
dev_data = PRIV(vcc->dev);
if (dev_data) out_vcc = dev_data->vcc;
if (!dev_data || !out_vcc) {
if (vcc->pop) vcc->pop(vcc,skb);
else dev_kfree_skb(skb);
if (dev_data) return 0;
atomic_inc(&vcc->stats->tx_err);
return -ENOLINK;
}
size = skb->len+sizeof(struct atmtcp_hdr);
new_skb = atm_alloc_charge(out_vcc,size,GFP_ATOMIC);
if (!new_skb) {
if (vcc->pop) vcc->pop(vcc,skb);
else dev_kfree_skb(skb);
atomic_inc(&vcc->stats->tx_err);
return -ENOBUFS;
}
hdr = skb_put(new_skb, sizeof(struct atmtcp_hdr));
hdr->vpi = htons(vcc->vpi);
hdr->vci = htons(vcc->vci);
hdr->length = htonl(skb->len);
skb_copy_from_linear_data(skb, skb_put(new_skb, skb->len), skb->len);
if (vcc->pop) vcc->pop(vcc,skb);
else dev_kfree_skb(skb);
out_vcc->push(out_vcc,new_skb);
atomic_inc(&vcc->stats->tx);
atomic_inc(&out_vcc->stats->rx);
return 0;
}
static int atmtcp_v_proc(struct atm_dev *dev,loff_t *pos,char *page)
{
struct atmtcp_dev_data *dev_data = PRIV(dev);
if (*pos) return 0;
if (!dev_data->persist) return sprintf(page,"ephemeral\n");
return sprintf(page,"persistent, %sconnected\n",
dev_data->vcc ? "" : "dis");
}
static void atmtcp_c_close(struct atm_vcc *vcc)
{
struct atm_dev *atmtcp_dev;
struct atmtcp_dev_data *dev_data;
atmtcp_dev = (struct atm_dev *) vcc->dev_data;
dev_data = PRIV(atmtcp_dev);
dev_data->vcc = NULL;
if (dev_data->persist) return;
atmtcp_dev->dev_data = NULL;
kfree(dev_data);
atm_dev_deregister(atmtcp_dev);
vcc->dev_data = NULL;
module_put(THIS_MODULE);
}
static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
{
struct hlist_head *head;
struct atm_vcc *vcc;
struct sock *s;
head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
sk_for_each(s, head) {
vcc = atm_sk(s);
if (vcc->dev == dev &&
vcc->vci == vci && vcc->vpi == vpi &&
vcc->qos.rxtp.traffic_class != ATM_NONE) {
return vcc;
}
}
return NULL;
}
static int atmtcp_c_pre_send(struct atm_vcc *vcc, struct sk_buff *skb)
{
struct atmtcp_hdr *hdr;
if (skb->len < sizeof(struct atmtcp_hdr))
return -EINVAL;
hdr = (struct atmtcp_hdr *)skb->data;
if (hdr->length == ATMTCP_HDR_MAGIC)
return -EINVAL;
return 0;
}
static int atmtcp_c_send(struct atm_vcc *vcc,struct sk_buff *skb)
{
struct atm_dev *dev;
struct atmtcp_hdr *hdr;
struct atm_vcc *out_vcc;
struct sk_buff *new_skb;
int result = 0;
dev = vcc->dev_data;
hdr = (struct atmtcp_hdr *) skb->data;
if (hdr->length == ATMTCP_HDR_MAGIC) {
result = atmtcp_recv_control(
(struct atmtcp_control *) skb->data);
goto done;
}
read_lock(&vcc_sklist_lock);
out_vcc = find_vcc(dev, ntohs(hdr->vpi), ntohs(hdr->vci));
read_unlock(&vcc_sklist_lock);
if (!out_vcc) {
result = -EUNATCH;
atomic_inc(&vcc->stats->tx_err);
goto done;
}
skb_pull(skb,sizeof(struct atmtcp_hdr));
new_skb = atm_alloc_charge(out_vcc,skb->len,GFP_KERNEL);
if (!new_skb) {
result = -ENOBUFS;
goto done;
}
__net_timestamp(new_skb);
skb_copy_from_linear_data(skb, skb_put(new_skb, skb->len), skb->len);
out_vcc->push(out_vcc,new_skb);
atomic_inc(&vcc->stats->tx);
atomic_inc(&out_vcc->stats->rx);
done:
if (vcc->pop) vcc->pop(vcc,skb);
else dev_kfree_skb(skb);
return result;
}
/*
* Device operations for the virtual ATM devices created by ATMTCP.
*/
static const struct atmdev_ops atmtcp_v_dev_ops = {
.dev_close = atmtcp_v_dev_close,
.open = atmtcp_v_open,
.close = atmtcp_v_close,
.ioctl = atmtcp_v_ioctl,
.send = atmtcp_v_send,
.proc_read = atmtcp_v_proc,
.owner = THIS_MODULE
};
/*
* Device operations for the ATMTCP control device.
*/
static const struct atmdev_ops atmtcp_c_dev_ops = {
.close = atmtcp_c_close,
.pre_send = atmtcp_c_pre_send,
.send = atmtcp_c_send
};
static struct atm_dev atmtcp_control_dev = {
.ops = &atmtcp_c_dev_ops,
.type = "atmtcp",
.number = 999,
.lock = __SPIN_LOCK_UNLOCKED(atmtcp_control_dev.lock)
};
static int atmtcp_create(int itf,int persist,struct atm_dev **result)
{
struct atmtcp_dev_data *dev_data;
struct atm_dev *dev;
dev_data = kmalloc_obj(*dev_data);
if (!dev_data)
return -ENOMEM;
dev = atm_dev_register(DEV_LABEL,NULL,&atmtcp_v_dev_ops,itf,NULL);
if (!dev) {
kfree(dev_data);
return itf == -1 ? -ENOMEM : -EBUSY;
}
dev->ci_range.vpi_bits = MAX_VPI_BITS;
dev->ci_range.vci_bits = MAX_VCI_BITS;
dev->dev_data = dev_data;
PRIV(dev)->vcc = NULL;
PRIV(dev)->persist = persist;
if (result) *result = dev;
return 0;
}
static int atmtcp_attach(struct atm_vcc *vcc,int itf)
{
struct atm_dev *dev;
dev = NULL;
if (itf != -1) dev = atm_dev_lookup(itf);
if (dev) {
if (dev->ops != &atmtcp_v_dev_ops) {
atm_dev_put(dev);
return -EMEDIUMTYPE;
}
if (PRIV(dev)->vcc) {
atm_dev_put(dev);
return -EBUSY;
}
}
else {
int error;
error = atmtcp_create(itf,0,&dev);
if (error) return error;
}
PRIV(dev)->vcc = vcc;
vcc->dev = &atmtcp_control_dev;
vcc_insert_socket(sk_atm(vcc));
set_bit(ATM_VF_META,&vcc->flags);
set_bit(ATM_VF_READY,&vcc->flags);
vcc->dev_data = dev;
(void) atm_init_aal5(vcc); /* @@@ losing AAL in transit ... */
vcc->stats = &atmtcp_control_dev.stats.aal5;
return dev->number;
}
static int atmtcp_create_persistent(int itf)
{
return atmtcp_create(itf,1,NULL);
}
static int atmtcp_remove_persistent(int itf)
{
struct atm_dev *dev;
struct atmtcp_dev_data *dev_data;
dev = atm_dev_lookup(itf);
if (!dev) return -ENODEV;
if (dev->ops != &atmtcp_v_dev_ops) {
atm_dev_put(dev);
return -EMEDIUMTYPE;
}
dev_data = PRIV(dev);
if (!dev_data->persist) {
atm_dev_put(dev);
return 0;
}
dev_data->persist = 0;
if (PRIV(dev)->vcc) {
atm_dev_put(dev);
return 0;
}
kfree(dev_data);
atm_dev_put(dev);
atm_dev_deregister(dev);
return 0;
}
static int atmtcp_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg)
{
int err = 0;
struct atm_vcc *vcc = ATM_SD(sock);
if (cmd != SIOCSIFATMTCP && cmd != ATMTCP_CREATE && cmd != ATMTCP_REMOVE)
return -ENOIOCTLCMD;
if (!capable(CAP_NET_ADMIN))
return -EPERM;
switch (cmd) {
case SIOCSIFATMTCP:
err = atmtcp_attach(vcc, (int) arg);
if (err >= 0) {
sock->state = SS_CONNECTED;
__module_get(THIS_MODULE);
}
break;
case ATMTCP_CREATE:
err = atmtcp_create_persistent((int) arg);
break;
case ATMTCP_REMOVE:
err = atmtcp_remove_persistent((int) arg);
break;
}
return err;
}
static struct atm_ioctl atmtcp_ioctl_ops = {
.owner = THIS_MODULE,
.ioctl = atmtcp_ioctl,
};
static __init int atmtcp_init(void)
{
register_atm_ioctl(&atmtcp_ioctl_ops);
return 0;
}
static void __exit atmtcp_exit(void)
{
deregister_atm_ioctl(&atmtcp_ioctl_ops);
}
MODULE_DESCRIPTION("ATM over TCP");
MODULE_LICENSE("GPL");
module_init(atmtcp_init);
module_exit(atmtcp_exit);

2321
drivers/atm/eni.c
View File

File diff suppressed because it is too large Load Diff

136
drivers/atm/eni.h
View File

@ -1,136 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/eni.h - Efficient Networks ENI155P device driver declarations */
/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
#ifndef DRIVER_ATM_ENI_H
#define DRIVER_ATM_ENI_H
#include <linux/atm.h>
#include <linux/atmdev.h>
#include <linux/interrupt.h>
#include <linux/sonet.h>
#include <linux/skbuff.h>
#include <linux/time.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/atomic.h>
#include "midway.h"
#define DEV_LABEL "eni"
#define UBR_BUFFER (128*1024) /* UBR buffer size */
#define RX_DMA_BUF 8 /* burst and skip a few things */
#define TX_DMA_BUF 100 /* should be enough for 64 kB */
#define DEFAULT_RX_MULT 300 /* max_sdu*3 */
#define DEFAULT_TX_MULT 300 /* max_sdu*3 */
#define ENI_ZEROES_SIZE 4 /* need that many DMA-able zero bytes */
struct eni_free {
void __iomem *start; /* counting in bytes */
int order;
};
struct eni_tx {
void __iomem *send; /* base, 0 if unused */
int prescaler; /* shaping prescaler */
int resolution; /* shaping divider */
unsigned long tx_pos; /* current TX write position */
unsigned long words; /* size of TX queue */
int index; /* TX channel number */
int reserved; /* reserved peak cell rate */
int shaping; /* shaped peak cell rate */
struct sk_buff_head backlog; /* queue of waiting TX buffers */
};
struct eni_vcc {
int (*rx)(struct atm_vcc *vcc); /* RX function, NULL if none */
void __iomem *recv; /* receive buffer */
unsigned long words; /* its size in words */
unsigned long descr; /* next descriptor (RX) */
unsigned long rx_pos; /* current RX descriptor pos */
struct eni_tx *tx; /* TXer, NULL if none */
int rxing; /* number of pending PDUs */
int servicing; /* number of waiting VCs (0 or 1) */
int txing; /* number of pending TX bytes */
ktime_t timestamp; /* for RX timing */
struct atm_vcc *next; /* next pending RX */
struct sk_buff *last; /* last PDU being DMAed (used to carry
discard information) */
};
struct eni_dev {
/*-------------------------------- spinlock */
spinlock_t lock; /* sync with interrupt */
struct tasklet_struct task; /* tasklet for interrupt work */
u32 events; /* pending events */
/*-------------------------------- base pointers into Midway address
space */
void __iomem *ioaddr;
void __iomem *phy; /* PHY interface chip registers */
void __iomem *reg; /* register base */
void __iomem *ram; /* RAM base */
void __iomem *vci; /* VCI table */
void __iomem *rx_dma; /* RX DMA queue */
void __iomem *tx_dma; /* TX DMA queue */
void __iomem *service; /* service list */
/*-------------------------------- TX part */
struct eni_tx tx[NR_CHAN]; /* TX channels */
struct eni_tx *ubr; /* UBR channel */
struct sk_buff_head tx_queue; /* PDUs currently being TX DMAed*/
wait_queue_head_t tx_wait; /* for close */
int tx_bw; /* remaining bandwidth */
u32 dma[TX_DMA_BUF*2]; /* DMA request scratch area */
struct eni_zero { /* aligned "magic" zeroes */
u32 *addr;
dma_addr_t dma;
} zero;
int tx_mult; /* buffer size multiplier (percent) */
/*-------------------------------- RX part */
u32 serv_read; /* host service read index */
struct atm_vcc *fast,*last_fast;/* queues of VCCs with pending PDUs */
struct atm_vcc *slow,*last_slow;
struct atm_vcc **rx_map; /* for fast lookups */
struct sk_buff_head rx_queue; /* PDUs currently being RX-DMAed */
wait_queue_head_t rx_wait; /* for close */
int rx_mult; /* buffer size multiplier (percent) */
/*-------------------------------- statistics */
unsigned long lost; /* number of lost cells (RX) */
/*-------------------------------- memory management */
unsigned long base_diff; /* virtual-real base address */
int free_len; /* free list length */
struct eni_free *free_list; /* free list */
int free_list_size; /* maximum size of free list */
/*-------------------------------- ENI links */
struct atm_dev *more; /* other ENI devices */
/*-------------------------------- general information */
int mem; /* RAM on board (in bytes) */
int asic; /* PCI interface type, 0 for FPGA */
unsigned int irq; /* IRQ */
struct pci_dev *pci_dev; /* PCI stuff */
};
#define ENI_DEV(d) ((struct eni_dev *) (d)->dev_data)
#define ENI_VCC(d) ((struct eni_vcc *) (d)->dev_data)
struct eni_skb_prv {
struct atm_skb_data _; /* reserved */
unsigned long pos; /* position of next descriptor */
int size; /* PDU size in reassembly buffer */
dma_addr_t paddr; /* DMA handle */
};
#define ENI_PRV_SIZE(skb) (((struct eni_skb_prv *) (skb)->cb)->size)
#define ENI_PRV_POS(skb) (((struct eni_skb_prv *) (skb)->cb)->pos)
#define ENI_PRV_PADDR(skb) (((struct eni_skb_prv *) (skb)->cb)->paddr)
#endif

3012
drivers/atm/fore200e.c
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File diff suppressed because it is too large Load Diff

973
drivers/atm/fore200e.h
View File

@ -1,973 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _FORE200E_H
#define _FORE200E_H
#ifdef __KERNEL__
/* rx buffer sizes */
#define SMALL_BUFFER_SIZE 384 /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
#define LARGE_BUFFER_SIZE 4032 /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
#define RBD_BLK_SIZE 32 /* nbr of supplied rx buffers per rbd */
#define MAX_PDU_SIZE 65535 /* maximum PDU size supported by AALs */
#define BUFFER_S1_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 1 */
#define BUFFER_L1_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 1 */
#define BUFFER_S2_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 2 */
#define BUFFER_L2_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 2 */
#define BUFFER_S1_NBR (RBD_BLK_SIZE * 6)
#define BUFFER_L1_NBR (RBD_BLK_SIZE * 4)
#define BUFFER_S2_NBR (RBD_BLK_SIZE * 6)
#define BUFFER_L2_NBR (RBD_BLK_SIZE * 4)
#define QUEUE_SIZE_CMD 16 /* command queue capacity */
#define QUEUE_SIZE_RX 64 /* receive queue capacity */
#define QUEUE_SIZE_TX 256 /* transmit queue capacity */
#define QUEUE_SIZE_BS 32 /* buffer supply queue capacity */
#define FORE200E_VPI_BITS 0
#define FORE200E_VCI_BITS 10
#define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */
#define TSD_FIXED 2
#define TSD_EXTENSION 0
#define TSD_NBR (TSD_FIXED + TSD_EXTENSION)
/* the cp starts putting a received PDU into one *small* buffer,
then it uses a number of *large* buffers for the trailing data.
we compute here the total number of receive segment descriptors
required to hold the largest possible PDU */
#define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)
#define RSD_FIXED 3
/* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
but we have to keep the size of the receive PDU descriptor multiple of 32 bytes,
so we add one extra RSD to RSD_EXTENSION
(WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */
#define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
#define RSD_NBR (RSD_FIXED + RSD_EXTENSION)
#define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
#define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
/* bitfields endian games */
#if defined(__LITTLE_ENDIAN_BITFIELD)
#define BITFIELD2(b1, b2) b1; b2;
#define BITFIELD3(b1, b2, b3) b1; b2; b3;
#define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4;
#define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5;
#define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6;
#elif defined(__BIG_ENDIAN_BITFIELD)
#define BITFIELD2(b1, b2) b2; b1;
#define BITFIELD3(b1, b2, b3) b3; b2; b1;
#define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1;
#define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1;
#define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1;
#else
#error unknown bitfield endianess
#endif
/* ATM cell header (minus HEC byte) */
typedef struct atm_header {
BITFIELD5(
u32 clp : 1, /* cell loss priority */
u32 plt : 3, /* payload type */
u32 vci : 16, /* virtual channel identifier */
u32 vpi : 8, /* virtual path identifier */
u32 gfc : 4 /* generic flow control */
)
} atm_header_t;
/* ATM adaptation layer id */
typedef enum fore200e_aal {
FORE200E_AAL0 = 0,
FORE200E_AAL34 = 4,
FORE200E_AAL5 = 5,
} fore200e_aal_t;
/* transmit PDU descriptor specification */
typedef struct tpd_spec {
BITFIELD4(
u32 length : 16, /* total PDU length */
u32 nseg : 8, /* number of transmit segments */
enum fore200e_aal aal : 4, /* adaptation layer */
u32 intr : 4 /* interrupt requested */
)
} tpd_spec_t;
/* transmit PDU rate control */
typedef struct tpd_rate
{
BITFIELD2(
u32 idle_cells : 16, /* number of idle cells to insert */
u32 data_cells : 16 /* number of data cells to transmit */
)
} tpd_rate_t;
/* transmit segment descriptor */
typedef struct tsd {
u32 buffer; /* transmit buffer DMA address */
u32 length; /* number of bytes in buffer */
} tsd_t;
/* transmit PDU descriptor */
typedef struct tpd {
struct atm_header atm_header; /* ATM header minus HEC byte */
struct tpd_spec spec; /* tpd specification */
struct tpd_rate rate; /* tpd rate control */
u32 pad; /* reserved */
struct tsd tsd[ TSD_NBR ]; /* transmit segment descriptors */
} tpd_t;
/* receive segment descriptor */
typedef struct rsd {
u32 handle; /* host supplied receive buffer handle */
u32 length; /* number of bytes in buffer */
} rsd_t;
/* receive PDU descriptor */
typedef struct rpd {
struct atm_header atm_header; /* ATM header minus HEC byte */
u32 nseg; /* number of receive segments */
struct rsd rsd[ RSD_NBR ]; /* receive segment descriptors */
} rpd_t;
/* buffer scheme */
typedef enum buffer_scheme {
BUFFER_SCHEME_ONE,
BUFFER_SCHEME_TWO,
BUFFER_SCHEME_NBR /* always last */
} buffer_scheme_t;
/* buffer magnitude */
typedef enum buffer_magn {
BUFFER_MAGN_SMALL,
BUFFER_MAGN_LARGE,
BUFFER_MAGN_NBR /* always last */
} buffer_magn_t;
/* receive buffer descriptor */
typedef struct rbd {
u32 handle; /* host supplied handle */
u32 buffer_haddr; /* host DMA address of host buffer */
} rbd_t;
/* receive buffer descriptor block */
typedef struct rbd_block {
struct rbd rbd[ RBD_BLK_SIZE ]; /* receive buffer descriptor */
} rbd_block_t;
/* tpd DMA address */
typedef struct tpd_haddr {
BITFIELD3(
u32 size : 4, /* tpd size expressed in 32 byte blocks */
u32 pad : 1, /* reserved */
u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */
)
} tpd_haddr_t;
#define TPD_HADDR_SHIFT 5 /* addr aligned on 32 byte boundary */
/* cp resident transmit queue entry */
typedef struct cp_txq_entry {
struct tpd_haddr tpd_haddr; /* host DMA address of tpd */
u32 status_haddr; /* host DMA address of completion status */
} cp_txq_entry_t;
/* cp resident receive queue entry */
typedef struct cp_rxq_entry {
u32 rpd_haddr; /* host DMA address of rpd */
u32 status_haddr; /* host DMA address of completion status */
} cp_rxq_entry_t;
/* cp resident buffer supply queue entry */
typedef struct cp_bsq_entry {
u32 rbd_block_haddr; /* host DMA address of rbd block */
u32 status_haddr; /* host DMA address of completion status */
} cp_bsq_entry_t;
/* completion status */
typedef volatile enum status {
STATUS_PENDING = (1<<0), /* initial status (written by host) */
STATUS_COMPLETE = (1<<1), /* completion status (written by cp) */
STATUS_FREE = (1<<2), /* initial status (written by host) */
STATUS_ERROR = (1<<3) /* completion status (written by cp) */
} status_t;
/* cp operation code */
typedef enum opcode {
OPCODE_INITIALIZE = 1, /* initialize board */
OPCODE_ACTIVATE_VCIN, /* activate incoming VCI */
OPCODE_ACTIVATE_VCOUT, /* activate outgoing VCI */
OPCODE_DEACTIVATE_VCIN, /* deactivate incoming VCI */
OPCODE_DEACTIVATE_VCOUT, /* deactivate incoing VCI */
OPCODE_GET_STATS, /* get board statistics */
OPCODE_SET_OC3, /* set OC-3 registers */
OPCODE_GET_OC3, /* get OC-3 registers */
OPCODE_RESET_STATS, /* reset board statistics */
OPCODE_GET_PROM, /* get expansion PROM data (PCI specific) */
OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the
firmware to be low order bits from
the VPI field of the ATM cell header */
OPCODE_REQUEST_INTR = (1<<7) /* request interrupt */
} opcode_t;
/* virtual path / virtual channel identifiers */
typedef struct vpvc {
BITFIELD3(
u32 vci : 16, /* virtual channel identifier */
u32 vpi : 8, /* virtual path identifier */
u32 pad : 8 /* reserved */
)
} vpvc_t;
/* activate VC command opcode */
typedef struct activate_opcode {
BITFIELD4(
enum opcode opcode : 8, /* cp opcode */
enum fore200e_aal aal : 8, /* adaptation layer */
enum buffer_scheme scheme : 8, /* buffer scheme */
u32 pad : 8 /* reserved */
)
} activate_opcode_t;
/* activate VC command block */
typedef struct activate_block {
struct activate_opcode opcode; /* activate VC command opcode */
struct vpvc vpvc; /* VPI/VCI */
u32 mtu; /* for AAL0 only */
} activate_block_t;
/* deactivate VC command opcode */
typedef struct deactivate_opcode {
BITFIELD2(
enum opcode opcode : 8, /* cp opcode */
u32 pad : 24 /* reserved */
)
} deactivate_opcode_t;
/* deactivate VC command block */
typedef struct deactivate_block {
struct deactivate_opcode opcode; /* deactivate VC command opcode */
struct vpvc vpvc; /* VPI/VCI */
} deactivate_block_t;
/* OC-3 registers */
typedef struct oc3_regs {
u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite
Saturn User Network Interface documentation
for a description of the OC-3 chip registers */
} oc3_regs_t;
/* set/get OC-3 regs command opcode */
typedef struct oc3_opcode {
BITFIELD4(
enum opcode opcode : 8, /* cp opcode */
u32 reg : 8, /* register index */
u32 value : 8, /* register value */
u32 mask : 8 /* register mask that specifies which
bits of the register value field
are significant */
)
} oc3_opcode_t;
/* set/get OC-3 regs command block */
typedef struct oc3_block {
struct oc3_opcode opcode; /* set/get OC-3 regs command opcode */
u32 regs_haddr; /* host DMA address of OC-3 regs buffer */
} oc3_block_t;
/* physical encoding statistics */
typedef struct stats_phy {
__be32 crc_header_errors; /* cells received with bad header CRC */
__be32 framing_errors; /* cells received with bad framing */
__be32 pad[ 2 ]; /* i960 padding */
} stats_phy_t;
/* OC-3 statistics */
typedef struct stats_oc3 {
__be32 section_bip8_errors; /* section 8 bit interleaved parity */
__be32 path_bip8_errors; /* path 8 bit interleaved parity */
__be32 line_bip24_errors; /* line 24 bit interleaved parity */
__be32 line_febe_errors; /* line far end block errors */
__be32 path_febe_errors; /* path far end block errors */
__be32 corr_hcs_errors; /* correctable header check sequence */
__be32 ucorr_hcs_errors; /* uncorrectable header check sequence */
__be32 pad[ 1 ]; /* i960 padding */
} stats_oc3_t;
/* ATM statistics */
typedef struct stats_atm {
__be32 cells_transmitted; /* cells transmitted */
__be32 cells_received; /* cells received */
__be32 vpi_bad_range; /* cell drops: VPI out of range */
__be32 vpi_no_conn; /* cell drops: no connection for VPI */
__be32 vci_bad_range; /* cell drops: VCI out of range */
__be32 vci_no_conn; /* cell drops: no connection for VCI */
__be32 pad[ 2 ]; /* i960 padding */
} stats_atm_t;
/* AAL0 statistics */
typedef struct stats_aal0 {
__be32 cells_transmitted; /* cells transmitted */
__be32 cells_received; /* cells received */
__be32 cells_dropped; /* cells dropped */
__be32 pad[ 1 ]; /* i960 padding */
} stats_aal0_t;
/* AAL3/4 statistics */
typedef struct stats_aal34 {
__be32 cells_transmitted; /* cells transmitted from segmented PDUs */
__be32 cells_received; /* cells reassembled into PDUs */
__be32 cells_crc_errors; /* payload CRC error count */
__be32 cells_protocol_errors; /* SAR or CS layer protocol errors */
__be32 cells_dropped; /* cells dropped: partial reassembly */
__be32 cspdus_transmitted; /* CS PDUs transmitted */
__be32 cspdus_received; /* CS PDUs received */
__be32 cspdus_protocol_errors; /* CS layer protocol errors */
__be32 cspdus_dropped; /* reassembled PDUs drop'd (in cells) */
__be32 pad[ 3 ]; /* i960 padding */
} stats_aal34_t;
/* AAL5 statistics */
typedef struct stats_aal5 {
__be32 cells_transmitted; /* cells transmitted from segmented SDUs */
__be32 cells_received; /* cells reassembled into SDUs */
__be32 cells_dropped; /* reassembled PDUs dropped (in cells) */
__be32 congestion_experienced; /* CRC error and length wrong */
__be32 cspdus_transmitted; /* CS PDUs transmitted */
__be32 cspdus_received; /* CS PDUs received */
__be32 cspdus_crc_errors; /* CS PDUs CRC errors */
__be32 cspdus_protocol_errors; /* CS layer protocol errors */
__be32 cspdus_dropped; /* reassembled PDUs dropped */
__be32 pad[ 3 ]; /* i960 padding */
} stats_aal5_t;
/* auxiliary statistics */
typedef struct stats_aux {
__be32 small_b1_failed; /* receive BD allocation failures */
__be32 large_b1_failed; /* receive BD allocation failures */
__be32 small_b2_failed; /* receive BD allocation failures */
__be32 large_b2_failed; /* receive BD allocation failures */
__be32 rpd_alloc_failed; /* receive PDU allocation failures */
__be32 receive_carrier; /* no carrier = 0, carrier = 1 */
__be32 pad[ 2 ]; /* i960 padding */
} stats_aux_t;
/* whole statistics buffer */
typedef struct stats {
struct stats_phy phy; /* physical encoding statistics */
struct stats_oc3 oc3; /* OC-3 statistics */
struct stats_atm atm; /* ATM statistics */
struct stats_aal0 aal0; /* AAL0 statistics */
struct stats_aal34 aal34; /* AAL3/4 statistics */
struct stats_aal5 aal5; /* AAL5 statistics */
struct stats_aux aux; /* auxiliary statistics */
} stats_t;
/* get statistics command opcode */
typedef struct stats_opcode {
BITFIELD2(
enum opcode opcode : 8, /* cp opcode */
u32 pad : 24 /* reserved */
)
} stats_opcode_t;
/* get statistics command block */
typedef struct stats_block {
struct stats_opcode opcode; /* get statistics command opcode */
u32 stats_haddr; /* host DMA address of stats buffer */
} stats_block_t;
/* expansion PROM data (PCI specific) */
typedef struct prom_data {
u32 hw_revision; /* hardware revision */
u32 serial_number; /* board serial number */
u8 mac_addr[ 8 ]; /* board MAC address */
} prom_data_t;
/* get expansion PROM data command opcode */
typedef struct prom_opcode {
BITFIELD2(
enum opcode opcode : 8, /* cp opcode */
u32 pad : 24 /* reserved */
)
} prom_opcode_t;
/* get expansion PROM data command block */
typedef struct prom_block {
struct prom_opcode opcode; /* get PROM data command opcode */
u32 prom_haddr; /* host DMA address of PROM buffer */
} prom_block_t;
/* cp command */
typedef union cmd {
enum opcode opcode; /* operation code */
struct activate_block activate_block; /* activate VC */
struct deactivate_block deactivate_block; /* deactivate VC */
struct stats_block stats_block; /* get statistics */
struct prom_block prom_block; /* get expansion PROM data */
struct oc3_block oc3_block; /* get/set OC-3 registers */
u32 pad[ 4 ]; /* i960 padding */
} cmd_t;
/* cp resident command queue */
typedef struct cp_cmdq_entry {
union cmd cmd; /* command */
u32 status_haddr; /* host DMA address of completion status */
u32 pad[ 3 ]; /* i960 padding */
} cp_cmdq_entry_t;
/* host resident transmit queue entry */
typedef struct host_txq_entry {
struct cp_txq_entry __iomem *cp_entry; /* addr of cp resident tx queue entry */
enum status* status; /* addr of host resident status */
struct tpd* tpd; /* addr of transmit PDU descriptor */
u32 tpd_dma; /* DMA address of tpd */
struct sk_buff* skb; /* related skb */
void* data; /* copy of misaligned data */
unsigned long incarn; /* vc_map incarnation when submitted for tx */
struct fore200e_vc_map* vc_map;
} host_txq_entry_t;
/* host resident receive queue entry */
typedef struct host_rxq_entry {
struct cp_rxq_entry __iomem *cp_entry; /* addr of cp resident rx queue entry */
enum status* status; /* addr of host resident status */
struct rpd* rpd; /* addr of receive PDU descriptor */
u32 rpd_dma; /* DMA address of rpd */
} host_rxq_entry_t;
/* host resident buffer supply queue entry */
typedef struct host_bsq_entry {
struct cp_bsq_entry __iomem *cp_entry; /* addr of cp resident buffer supply queue entry */
enum status* status; /* addr of host resident status */
struct rbd_block* rbd_block; /* addr of receive buffer descriptor block */
u32 rbd_block_dma; /* DMA address od rdb */
} host_bsq_entry_t;
/* host resident command queue entry */
typedef struct host_cmdq_entry {
struct cp_cmdq_entry __iomem *cp_entry; /* addr of cp resident cmd queue entry */
enum status *status; /* addr of host resident status */
} host_cmdq_entry_t;
/* chunk of memory */
typedef struct chunk {
void* alloc_addr; /* base address of allocated chunk */
void* align_addr; /* base address of aligned chunk */
dma_addr_t dma_addr; /* DMA address of aligned chunk */
int direction; /* direction of DMA mapping */
u32 alloc_size; /* length of allocated chunk */
u32 align_size; /* length of aligned chunk */
} chunk_t;
#define dma_size align_size /* DMA useable size */
/* host resident receive buffer */
typedef struct buffer {
struct buffer* next; /* next receive buffer */
enum buffer_scheme scheme; /* buffer scheme */
enum buffer_magn magn; /* buffer magnitude */
struct chunk data; /* data buffer */
#ifdef FORE200E_BSQ_DEBUG
unsigned long index; /* buffer # in queue */
int supplied; /* 'buffer supplied' flag */
#endif
} buffer_t;
#if (BITS_PER_LONG == 32)
#define FORE200E_BUF2HDL(buffer) ((u32)(buffer))
#define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle))
#else /* deal with 64 bit pointers */
#define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))
#define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
#endif
/* host resident command queue */
typedef struct host_cmdq {
struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ]; /* host resident cmd queue entries */
int head; /* head of cmd queue */
struct chunk status; /* array of completion status */
} host_cmdq_t;
/* host resident transmit queue */
typedef struct host_txq {
struct host_txq_entry host_entry[ QUEUE_SIZE_TX ]; /* host resident tx queue entries */
int head; /* head of tx queue */
int tail; /* tail of tx queue */
struct chunk tpd; /* array of tpds */
struct chunk status; /* arry of completion status */
int txing; /* number of pending PDUs in tx queue */
} host_txq_t;
/* host resident receive queue */
typedef struct host_rxq {
struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ]; /* host resident rx queue entries */
int head; /* head of rx queue */
struct chunk rpd; /* array of rpds */
struct chunk status; /* array of completion status */
} host_rxq_t;
/* host resident buffer supply queues */
typedef struct host_bsq {
struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ]; /* host resident buffer supply queue entries */
int head; /* head of buffer supply queue */
struct chunk rbd_block; /* array of rbds */
struct chunk status; /* array of completion status */
struct buffer* buffer; /* array of rx buffers */
struct buffer* freebuf; /* list of free rx buffers */
volatile int freebuf_count; /* count of free rx buffers */
} host_bsq_t;
/* header of the firmware image */
typedef struct fw_header {
__le32 magic; /* magic number */
__le32 version; /* firmware version id */
__le32 load_offset; /* fw load offset in board memory */
__le32 start_offset; /* fw execution start address in board memory */
} fw_header_t;
#define FW_HEADER_MAGIC 0x65726f66 /* 'fore' */
/* receive buffer supply queues scheme specification */
typedef struct bs_spec {
u32 queue_length; /* queue capacity */
u32 buffer_size; /* host buffer size */
u32 pool_size; /* number of rbds */
u32 supply_blksize; /* num of rbds in I/O block (multiple
of 4 between 4 and 124 inclusive) */
} bs_spec_t;
/* initialization command block (one-time command, not in cmd queue) */
typedef struct init_block {
enum opcode opcode; /* initialize command */
enum status status; /* related status word */
u32 receive_threshold; /* not used */
u32 num_connect; /* ATM connections */
u32 cmd_queue_len; /* length of command queue */
u32 tx_queue_len; /* length of transmit queue */
u32 rx_queue_len; /* length of receive queue */
u32 rsd_extension; /* number of extra 32 byte blocks */
u32 tsd_extension; /* number of extra 32 byte blocks */
u32 conless_vpvc; /* not used */
u32 pad[ 2 ]; /* force quad alignment */
struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues spec */
} init_block_t;
typedef enum media_type {
MEDIA_TYPE_CAT5_UTP = 0x06, /* unshielded twisted pair */
MEDIA_TYPE_MM_OC3_ST = 0x16, /* multimode fiber ST */
MEDIA_TYPE_MM_OC3_SC = 0x26, /* multimode fiber SC */
MEDIA_TYPE_SM_OC3_ST = 0x36, /* single-mode fiber ST */
MEDIA_TYPE_SM_OC3_SC = 0x46 /* single-mode fiber SC */
} media_type_t;
#define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4)
/* cp resident queues */
typedef struct cp_queues {
u32 cp_cmdq; /* command queue */
u32 cp_txq; /* transmit queue */
u32 cp_rxq; /* receive queue */
u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */
u32 imask; /* 1 enables cp to host interrupts */
u32 istat; /* 1 for interrupt posted */
u32 heap_base; /* offset form beginning of ram */
u32 heap_size; /* space available for queues */
u32 hlogger; /* non zero for host logging */
u32 heartbeat; /* cp heartbeat */
u32 fw_release; /* firmware version */
u32 mon960_release; /* i960 monitor version */
u32 tq_plen; /* transmit throughput measurements */
/* make sure the init block remains on a quad word boundary */
struct init_block init; /* one time cmd, not in cmd queue */
enum media_type media_type; /* media type id */
u32 oc3_revision; /* OC-3 revision number */
} cp_queues_t;
/* boot status */
typedef enum boot_status {
BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */
BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */
BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */
BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */
BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */
} boot_status_t;
/* software UART */
typedef struct soft_uart {
u32 send; /* write register */
u32 recv; /* read register */
} soft_uart_t;
#define FORE200E_CP_MONITOR_UART_FREE 0x00000000
#define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000
/* i960 monitor */
typedef struct cp_monitor {
struct soft_uart soft_uart; /* software UART */
enum boot_status bstat; /* boot status */
u32 app_base; /* application base offset */
u32 mon_version; /* i960 monitor version */
} cp_monitor_t;
/* device state */
typedef enum fore200e_state {
FORE200E_STATE_BLANK, /* initial state */
FORE200E_STATE_REGISTER, /* device registered */
FORE200E_STATE_CONFIGURE, /* bus interface configured */
FORE200E_STATE_MAP, /* board space mapped in host memory */
FORE200E_STATE_RESET, /* board resetted */
FORE200E_STATE_START_FW, /* firmware started */
FORE200E_STATE_INITIALIZE, /* initialize command successful */
FORE200E_STATE_INIT_CMDQ, /* command queue initialized */
FORE200E_STATE_INIT_TXQ, /* transmit queue initialized */
FORE200E_STATE_INIT_RXQ, /* receive queue initialized */
FORE200E_STATE_INIT_BSQ, /* buffer supply queue initialized */
FORE200E_STATE_ALLOC_BUF, /* receive buffers allocated */
FORE200E_STATE_IRQ, /* host interrupt requested */
FORE200E_STATE_COMPLETE /* initialization completed */
} fore200e_state;
/* PCA-200E registers */
typedef struct fore200e_pca_regs {
volatile u32 __iomem * hcr; /* address of host control register */
volatile u32 __iomem * imr; /* address of host interrupt mask register */
volatile u32 __iomem * psr; /* address of PCI specific register */
} fore200e_pca_regs_t;
/* SBA-200E registers */
typedef struct fore200e_sba_regs {
u32 __iomem *hcr; /* address of host control register */
u32 __iomem *bsr; /* address of burst transfer size register */
u32 __iomem *isr; /* address of interrupt level selection register */
} fore200e_sba_regs_t;
/* model-specific registers */
typedef union fore200e_regs {
struct fore200e_pca_regs pca; /* PCA-200E registers */
struct fore200e_sba_regs sba; /* SBA-200E registers */
} fore200e_regs;
struct fore200e;
/* bus-dependent data */
typedef struct fore200e_bus {
char* model_name; /* board model name */
char* proc_name; /* board name under /proc/atm */
int descr_alignment; /* tpd/rpd/rbd DMA alignment requirement */
int buffer_alignment; /* rx buffers DMA alignment requirement */
int status_alignment; /* status words DMA alignment requirement */
u32 (*read)(volatile u32 __iomem *);
void (*write)(u32, volatile u32 __iomem *);
int (*configure)(struct fore200e*);
int (*map)(struct fore200e*);
void (*reset)(struct fore200e*);
int (*prom_read)(struct fore200e*, struct prom_data*);
void (*unmap)(struct fore200e*);
void (*irq_enable)(struct fore200e*);
int (*irq_check)(struct fore200e*);
void (*irq_ack)(struct fore200e*);
int (*proc_read)(struct fore200e*, char*);
} fore200e_bus_t;
/* vc mapping */
typedef struct fore200e_vc_map {
struct atm_vcc* vcc; /* vcc entry */
unsigned long incarn; /* vcc incarnation number */
} fore200e_vc_map_t;
#define FORE200E_VC_MAP(fore200e, vpi, vci) \
(& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ])
/* per-device data */
typedef struct fore200e {
const struct fore200e_bus* bus; /* bus-dependent code and data */
union fore200e_regs regs; /* bus-dependent registers */
struct atm_dev* atm_dev; /* ATM device */
enum fore200e_state state; /* device state */
char name[16]; /* device name */
struct device *dev;
int irq; /* irq number */
unsigned long phys_base; /* physical base address */
void __iomem * virt_base; /* virtual base address */
unsigned char esi[ ESI_LEN ]; /* end system identifier */
struct cp_monitor __iomem * cp_monitor; /* i960 monitor address */
struct cp_queues __iomem * cp_queues; /* cp resident queues */
struct host_cmdq host_cmdq; /* host resident cmd queue */
struct host_txq host_txq; /* host resident tx queue */
struct host_rxq host_rxq; /* host resident rx queue */
/* host resident buffer supply queues */
struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
u32 available_cell_rate; /* remaining pseudo-CBR bw on link */
int loop_mode; /* S/UNI loopback mode */
struct stats* stats; /* last snapshot of the stats */
struct mutex rate_mtx; /* protects rate reservation ops */
spinlock_t q_lock; /* protects queue ops */
#ifdef FORE200E_USE_TASKLET
struct tasklet_struct tx_tasklet; /* performs tx interrupt work */
struct tasklet_struct rx_tasklet; /* performs rx interrupt work */
#endif
unsigned long tx_sat; /* tx queue saturation count */
unsigned long incarn_count;
struct fore200e_vc_map vc_map[ NBR_CONNECT ]; /* vc mapping */
} fore200e_t;
/* per-vcc data */
typedef struct fore200e_vcc {
enum buffer_scheme scheme; /* rx buffer scheme */
struct tpd_rate rate; /* tx rate control data */
int rx_min_pdu; /* size of smallest PDU received */
int rx_max_pdu; /* size of largest PDU received */
int tx_min_pdu; /* size of smallest PDU transmitted */
int tx_max_pdu; /* size of largest PDU transmitted */
unsigned long tx_pdu; /* nbr of tx pdus */
unsigned long rx_pdu; /* nbr of rx pdus */
} fore200e_vcc_t;
/* 200E-series common memory layout */
#define FORE200E_CP_MONITOR_OFFSET 0x00000400 /* i960 monitor interface */
#define FORE200E_CP_QUEUES_OFFSET 0x00004d40 /* cp resident queues */
/* PCA-200E memory layout */
#define PCA200E_IOSPACE_LENGTH 0x00200000
#define PCA200E_HCR_OFFSET 0x00100000 /* board control register */
#define PCA200E_IMR_OFFSET 0x00100004 /* host IRQ mask register */
#define PCA200E_PSR_OFFSET 0x00100008 /* PCI specific register */
/* PCA-200E host control register */
#define PCA200E_HCR_RESET (1<<0) /* read / write */
#define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */
#define PCA200E_HCR_I960FAIL (1<<2) /* read */
#define PCA200E_HCR_INTRB (1<<2) /* write */
#define PCA200E_HCR_HOLD_ACK (1<<3) /* read */
#define PCA200E_HCR_INTRA (1<<3) /* write */
#define PCA200E_HCR_OUTFULL (1<<4) /* read */
#define PCA200E_HCR_CLRINTR (1<<4) /* write */
#define PCA200E_HCR_ESPHOLD (1<<5) /* read */
#define PCA200E_HCR_INFULL (1<<6) /* read */
#define PCA200E_HCR_TESTMODE (1<<7) /* read */
/* PCA-200E PCI bus interface regs (offsets in PCI config space) */
#define PCA200E_PCI_LATENCY 0x40 /* maximum slave latenty */
#define PCA200E_PCI_MASTER_CTRL 0x41 /* master control */
#define PCA200E_PCI_THRESHOLD 0x42 /* burst / continuous req threshold */
/* PBI master control register */
#define PCA200E_CTRL_DIS_CACHE_RD (1<<0) /* disable cache-line reads */
#define PCA200E_CTRL_DIS_WRT_INVAL (1<<1) /* disable writes and invalidates */
#define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2) /* require 2 cache-lines for writes and invalidates */
#define PCA200E_CTRL_IGN_LAT_TIMER (1<<3) /* ignore the latency timer */
#define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4) /* enable continuous request mode */
#define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5) /* force large PCI bus bursts */
#define PCA200E_CTRL_CONVERT_ENDIAN (1<<6) /* convert endianess of slave RAM accesses */
#define SBA200E_PROM_NAME "FORE,sba-200e" /* device name in openprom tree */
/* size of SBA-200E registers */
#define SBA200E_HCR_LENGTH 4
#define SBA200E_BSR_LENGTH 4
#define SBA200E_ISR_LENGTH 4
#define SBA200E_RAM_LENGTH 0x40000
/* SBA-200E SBUS burst transfer size register */
#define SBA200E_BSR_BURST4 0x04
#define SBA200E_BSR_BURST8 0x08
#define SBA200E_BSR_BURST16 0x10
/* SBA-200E host control register */
#define SBA200E_HCR_RESET (1<<0) /* read / write (sticky) */
#define SBA200E_HCR_HOLD_LOCK (1<<1) /* read / write (sticky) */
#define SBA200E_HCR_I960FAIL (1<<2) /* read */
#define SBA200E_HCR_I960SETINTR (1<<2) /* write */
#define SBA200E_HCR_OUTFULL (1<<3) /* read */
#define SBA200E_HCR_INTR_CLR (1<<3) /* write */
#define SBA200E_HCR_INTR_ENA (1<<4) /* read / write (sticky) */
#define SBA200E_HCR_ESPHOLD (1<<5) /* read */
#define SBA200E_HCR_INFULL (1<<6) /* read */
#define SBA200E_HCR_TESTMODE (1<<7) /* read */
#define SBA200E_HCR_INTR_REQ (1<<8) /* read */
#define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)
#endif /* __KERNEL__ */
#endif /* _FORE200E_H */

2861
drivers/atm/he.c
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845
drivers/atm/he.h
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/*
he.h
ForeRunnerHE ATM Adapter driver for ATM on Linux
Copyright (C) 1999-2001 Naval Research Laboratory
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
he.h
ForeRunnerHE ATM Adapter driver for ATM on Linux
Copyright (C) 1999-2000 Naval Research Laboratory
Permission to use, copy, modify and distribute this software and its
documentation is hereby granted, provided that both the copyright
notice and this permission notice appear in all copies of the software,
derivative works or modified versions, and any portions thereof, and
that both notices appear in supporting documentation.
NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
RESULTING FROM THE USE OF THIS SOFTWARE.
*/
#ifndef _HE_H_
#define _HE_H_
#define DEV_LABEL "he"
#define CONFIG_DEFAULT_VCIBITS 12
#define CONFIG_DEFAULT_VPIBITS 0
#define CONFIG_IRQ_SIZE 128
#define CONFIG_IRQ_THRESH (CONFIG_IRQ_SIZE/2)
#define CONFIG_TPDRQ_SIZE 512
#define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1))
#define CONFIG_RBRQ_SIZE 512
#define CONFIG_RBRQ_THRESH 400
#define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1))
#define CONFIG_TBRQ_SIZE 512
#define CONFIG_TBRQ_THRESH 400
#define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1))
#define CONFIG_RBPL_SIZE 512
#define CONFIG_RBPL_THRESH 64
#define CONFIG_RBPL_BUFSIZE 4096
#define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1))
/* 5.1.3 initialize connection memory */
#define CONFIG_RSRA 0x00000
#define CONFIG_RCMLBM 0x08000
#define CONFIG_RCMABR 0x0d800
#define CONFIG_RSRB 0x0e000
#define CONFIG_TSRA 0x00000
#define CONFIG_TSRB 0x08000
#define CONFIG_TSRC 0x0c000
#define CONFIG_TSRD 0x0e000
#define CONFIG_TMABR 0x0f000
#define CONFIG_TPDBA 0x10000
#define HE_MAXCIDBITS 12
/* 2.9.3.3 interrupt encodings */
struct he_irq {
volatile u32 isw;
};
#define IRQ_ALIGNMENT 0x1000
#define NEXT_ENTRY(base, tail, mask) \
(((unsigned long)base)|(((unsigned long)(tail+1))&mask))
#define ITYPE_INVALID 0xffffffff
#define ITYPE_TBRQ_THRESH (0<<3)
#define ITYPE_TPD_COMPLETE (1<<3)
#define ITYPE_RBPS_THRESH (2<<3)
#define ITYPE_RBPL_THRESH (3<<3)
#define ITYPE_RBRQ_THRESH (4<<3)
#define ITYPE_RBRQ_TIMER (5<<3)
#define ITYPE_PHY (6<<3)
#define ITYPE_OTHER 0x80
#define ITYPE_PARITY 0x81
#define ITYPE_ABORT 0x82
#define ITYPE_GROUP(x) (x & 0x7)
#define ITYPE_TYPE(x) (x & 0xf8)
#define HE_NUM_GROUPS 8
/* 2.1.4 transmit packet descriptor */
struct he_tpd {
/* read by the adapter */
volatile u32 status;
volatile u32 reserved;
#define TPD_MAXIOV 3
struct {
u32 addr, len;
} iovec[TPD_MAXIOV];
#define address0 iovec[0].addr
#define length0 iovec[0].len
/* linux-atm extensions */
struct sk_buff *skb;
struct atm_vcc *vcc;
struct list_head entry;
};
#define TPD_ALIGNMENT 64
#define TPD_LEN_MASK 0xffff
#define TPD_ADDR_SHIFT 6
#define TPD_MASK 0xffffffc0
#define TPD_ADDR(x) ((x) & TPD_MASK)
#define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT)
/* table 2.3 transmit buffer return elements */
struct he_tbrq {
volatile u32 tbre;
};
#define TBRQ_ALIGNMENT CONFIG_TBRQ_SIZE
#define TBRQ_TPD(tbrq) ((tbrq)->tbre & 0xffffffc0)
#define TBRQ_EOS(tbrq) ((tbrq)->tbre & (1<<3))
#define TBRQ_MULTIPLE(tbrq) ((tbrq)->tbre & (1))
/* table 2.21 receive buffer return queue element field organization */
struct he_rbrq {
volatile u32 addr;
volatile u32 cidlen;
};
#define RBRQ_ALIGNMENT CONFIG_RBRQ_SIZE
#define RBRQ_ADDR(rbrq) ((rbrq)->addr & 0xffffffc0)
#define RBRQ_CRC_ERR(rbrq) ((rbrq)->addr & (1<<5))
#define RBRQ_LEN_ERR(rbrq) ((rbrq)->addr & (1<<4))
#define RBRQ_END_PDU(rbrq) ((rbrq)->addr & (1<<3))
#define RBRQ_AAL5_PROT(rbrq) ((rbrq)->addr & (1<<2))
#define RBRQ_CON_CLOSED(rbrq) ((rbrq)->addr & (1<<1))
#define RBRQ_HBUF_ERR(rbrq) ((rbrq)->addr & 1)
#define RBRQ_CID(rbrq) (((rbrq)->cidlen >> 16) & 0x1fff)
#define RBRQ_BUFLEN(rbrq) ((rbrq)->cidlen & 0xffff)
/* figure 2.3 transmit packet descriptor ready queue */
struct he_tpdrq {
volatile u32 tpd;
volatile u32 cid;
};
#define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE
/* table 2.30 host status page detail */
#define HSP_ALIGNMENT 0x400 /* must align on 1k boundary */
struct he_hsp {
struct he_hsp_entry {
volatile u32 tbrq_tail;
volatile u32 reserved1[15];
volatile u32 rbrq_tail;
volatile u32 reserved2[15];
} group[HE_NUM_GROUPS];
};
/*
* figure 2.9 receive buffer pools
*
* since a virtual address might be more than 32 bits, we store an index
* in the virt member of he_rbp. NOTE: the lower six bits in the rbrq
* addr member are used for buffer status further limiting us to 26 bits.
*/
struct he_rbp {
volatile u32 phys;
volatile u32 idx; /* virt */
};
#define RBP_IDX_OFFSET 6
/*
* the he dma engine will try to hold an extra 16 buffers in its local
* caches. and add a couple buffers for safety.
*/
#define RBPL_TABLE_SIZE (CONFIG_RBPL_SIZE + 16 + 2)
struct he_buff {
struct list_head entry;
dma_addr_t mapping;
unsigned long len;
u8 data[];
};
#ifdef notyet
struct he_group {
u32 rpbl_size, rpbl_qsize;
struct he_rpb_entry *rbpl_ba;
};
#endif
#define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc)
struct he_vcc_table
{
struct atm_vcc *vcc;
};
struct he_cs_stper
{
long pcr;
int inuse;
};
#define HE_NUM_CS_STPER 16
struct he_dev {
unsigned int number;
unsigned int irq;
void __iomem *membase;
char prod_id[30];
char mac_addr[6];
int media;
unsigned int vcibits, vpibits;
unsigned int cells_per_row;
unsigned int bytes_per_row;
unsigned int cells_per_lbuf;
unsigned int r0_numrows, r0_startrow, r0_numbuffs;
unsigned int r1_numrows, r1_startrow, r1_numbuffs;
unsigned int tx_numrows, tx_startrow, tx_numbuffs;
unsigned int buffer_limit;
struct he_vcc_table *he_vcc_table;
#ifdef notyet
struct he_group group[HE_NUM_GROUPS];
#endif
struct he_cs_stper cs_stper[HE_NUM_CS_STPER];
unsigned total_bw;
dma_addr_t irq_phys;
struct he_irq *irq_base, *irq_head, *irq_tail;
volatile unsigned *irq_tailoffset;
int irq_peak;
struct tasklet_struct tasklet;
struct dma_pool *tpd_pool;
struct list_head outstanding_tpds;
dma_addr_t tpdrq_phys;
struct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head;
spinlock_t global_lock; /* 8.1.5 pci transaction ordering
error problem */
dma_addr_t rbrq_phys;
struct he_rbrq *rbrq_base, *rbrq_head;
int rbrq_peak;
struct he_buff **rbpl_virt;
unsigned long *rbpl_table;
unsigned long rbpl_hint;
struct dma_pool *rbpl_pool;
dma_addr_t rbpl_phys;
struct he_rbp *rbpl_base, *rbpl_tail;
struct list_head rbpl_outstanding;
int rbpl_peak;
dma_addr_t tbrq_phys;
struct he_tbrq *tbrq_base, *tbrq_head;
int tbrq_peak;
dma_addr_t hsp_phys;
struct he_hsp *hsp;
struct pci_dev *pci_dev;
struct atm_dev *atm_dev;
struct he_dev *next;
};
#define HE_MAXIOV 20
struct he_vcc
{
struct list_head buffers;
int pdu_len;
int rc_index;
wait_queue_head_t rx_waitq;
wait_queue_head_t tx_waitq;
};
#define HE_VCC(vcc) ((struct he_vcc *)(vcc->dev_data))
#define PCI_VENDOR_ID_FORE 0x1127
#define PCI_DEVICE_ID_FORE_HE 0x400
#define GEN_CNTL_0 0x40
#define INT_PROC_ENBL (1<<25)
#define SLAVE_ENDIAN_MODE (1<<16)
#define MRL_ENB (1<<5)
#define MRM_ENB (1<<4)
#define INIT_ENB (1<<2)
#define IGNORE_TIMEOUT (1<<1)
#define ENBL_64 (1<<0)
#define MIN_PCI_LATENCY 32 /* errata 8.1.3 */
#define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data)
#define he_is622(dev) ((dev)->media & 0x1)
#define he_isMM(dev) ((dev)->media & 0x20)
#define HE_REGMAP_SIZE 0x100000
#define RESET_CNTL 0x80000
#define BOARD_RST_STATUS (1<<6)
#define HOST_CNTL 0x80004
#define PCI_BUS_SIZE64 (1<<27)
#define DESC_RD_STATIC_64 (1<<26)
#define DATA_RD_STATIC_64 (1<<25)
#define DATA_WR_STATIC_64 (1<<24)
#define ID_CS (1<<12)
#define ID_WREN (1<<11)
#define ID_DOUT (1<<10)
#define ID_DOFFSET 10
#define ID_DIN (1<<9)
#define ID_CLOCK (1<<8)
#define QUICK_RD_RETRY (1<<7)
#define QUICK_WR_RETRY (1<<6)
#define OUTFF_ENB (1<<5)
#define CMDFF_ENB (1<<4)
#define PERR_INT_ENB (1<<2)
#define IGNORE_INTR (1<<0)
#define LB_SWAP 0x80008
#define SWAP_RNUM_MAX(x) (x<<27)
#define DATA_WR_SWAP (1<<20)
#define DESC_RD_SWAP (1<<19)
#define DATA_RD_SWAP (1<<18)
#define INTR_SWAP (1<<17)
#define DESC_WR_SWAP (1<<16)
#define SDRAM_INIT (1<<15)
#define BIG_ENDIAN_HOST (1<<14)
#define XFER_SIZE (1<<7)
#define LB_MEM_ADDR 0x8000c
#define LB_MEM_DATA 0x80010
#define LB_MEM_ACCESS 0x80014
#define LB_MEM_HNDSHK (1<<30)
#define LM_MEM_WRITE (0x7)
#define LM_MEM_READ (0x3)
#define SDRAM_CTL 0x80018
#define LB_64_ENB (1<<3)
#define LB_TWR (1<<2)
#define LB_TRP (1<<1)
#define LB_TRAS (1<<0)
#define INT_FIFO 0x8001c
#define INT_MASK_D (1<<15)
#define INT_MASK_C (1<<14)
#define INT_MASK_B (1<<13)
#define INT_MASK_A (1<<12)
#define INT_CLEAR_D (1<<11)
#define INT_CLEAR_C (1<<10)
#define INT_CLEAR_B (1<<9)
#define INT_CLEAR_A (1<<8)
#define ABORT_ADDR 0x80020
#define IRQ0_BASE 0x80080
#define IRQ_BASE(x) (x<<12)
#define IRQ_MASK ((CONFIG_IRQ_SIZE<<2)-1) /* was 0x3ff */
#define IRQ_TAIL(x) (((unsigned long)(x)) & IRQ_MASK)
#define IRQ0_HEAD 0x80084
#define IRQ_SIZE(x) (x<<22)
#define IRQ_THRESH(x) (x<<12)
#define IRQ_HEAD(x) (x<<2)
/* #define IRQ_PENDING (1) conflict with linux/irq.h */
#define IRQ0_CNTL 0x80088
#define IRQ_ADDRSEL(x) (x<<2)
#define IRQ_INT_A (0<<2)
#define IRQ_INT_B (1<<2)
#define IRQ_INT_C (2<<2)
#define IRQ_INT_D (3<<2)
#define IRQ_TYPE_ADDR 0x1
#define IRQ_TYPE_LINE 0x0
#define IRQ0_DATA 0x8008c
#define IRQ1_BASE 0x80090
#define IRQ1_HEAD 0x80094
#define IRQ1_CNTL 0x80098
#define IRQ1_DATA 0x8009c
#define IRQ2_BASE 0x800a0
#define IRQ2_HEAD 0x800a4
#define IRQ2_CNTL 0x800a8
#define IRQ2_DATA 0x800ac
#define IRQ3_BASE 0x800b0
#define IRQ3_HEAD 0x800b4
#define IRQ3_CNTL 0x800b8
#define IRQ3_DATA 0x800bc
#define GRP_10_MAP 0x800c0
#define GRP_32_MAP 0x800c4
#define GRP_54_MAP 0x800c8
#define GRP_76_MAP 0x800cc
#define G0_RBPS_S 0x80400
#define G0_RBPS_T 0x80404
#define RBP_TAIL(x) ((x)<<3)
#define RBP_MASK(x) ((x)|0x1fff)
#define G0_RBPS_QI 0x80408
#define RBP_QSIZE(x) ((x)<<14)
#define RBP_INT_ENB (1<<13)
#define RBP_THRESH(x) (x)
#define G0_RBPS_BS 0x8040c
#define G0_RBPL_S 0x80410
#define G0_RBPL_T 0x80414
#define G0_RBPL_QI 0x80418
#define G0_RBPL_BS 0x8041c
#define G1_RBPS_S 0x80420
#define G1_RBPS_T 0x80424
#define G1_RBPS_QI 0x80428
#define G1_RBPS_BS 0x8042c
#define G1_RBPL_S 0x80430
#define G1_RBPL_T 0x80434
#define G1_RBPL_QI 0x80438
#define G1_RBPL_BS 0x8043c
#define G2_RBPS_S 0x80440
#define G2_RBPS_T 0x80444
#define G2_RBPS_QI 0x80448
#define G2_RBPS_BS 0x8044c
#define G2_RBPL_S 0x80450
#define G2_RBPL_T 0x80454
#define G2_RBPL_QI 0x80458
#define G2_RBPL_BS 0x8045c
#define G3_RBPS_S 0x80460
#define G3_RBPS_T 0x80464
#define G3_RBPS_QI 0x80468
#define G3_RBPS_BS 0x8046c
#define G3_RBPL_S 0x80470
#define G3_RBPL_T 0x80474
#define G3_RBPL_QI 0x80478
#define G3_RBPL_BS 0x8047c
#define G4_RBPS_S 0x80480
#define G4_RBPS_T 0x80484
#define G4_RBPS_QI 0x80488
#define G4_RBPS_BS 0x8048c
#define G4_RBPL_S 0x80490
#define G4_RBPL_T 0x80494
#define G4_RBPL_QI 0x80498
#define G4_RBPL_BS 0x8049c
#define G5_RBPS_S 0x804a0
#define G5_RBPS_T 0x804a4
#define G5_RBPS_QI 0x804a8
#define G5_RBPS_BS 0x804ac
#define G5_RBPL_S 0x804b0
#define G5_RBPL_T 0x804b4
#define G5_RBPL_QI 0x804b8
#define G5_RBPL_BS 0x804bc
#define G6_RBPS_S 0x804c0
#define G6_RBPS_T 0x804c4
#define G6_RBPS_QI 0x804c8
#define G6_RBPS_BS 0x804cc
#define G6_RBPL_S 0x804d0
#define G6_RBPL_T 0x804d4
#define G6_RBPL_QI 0x804d8
#define G6_RBPL_BS 0x804dc
#define G7_RBPS_S 0x804e0
#define G7_RBPS_T 0x804e4
#define G7_RBPS_QI 0x804e8
#define G7_RBPS_BS 0x804ec
#define G7_RBPL_S 0x804f0
#define G7_RBPL_T 0x804f4
#define G7_RBPL_QI 0x804f8
#define G7_RBPL_BS 0x804fc
#define G0_RBRQ_ST 0x80500
#define G0_RBRQ_H 0x80504
#define G0_RBRQ_Q 0x80508
#define RBRQ_THRESH(x) ((x)<<13)
#define RBRQ_SIZE(x) (x)
#define G0_RBRQ_I 0x8050c
#define RBRQ_TIME(x) ((x)<<8)
#define RBRQ_COUNT(x) (x)
/* fill in 1 ... 7 later */
#define G0_TBRQ_B_T 0x80600
#define G0_TBRQ_H 0x80604
#define G0_TBRQ_S 0x80608
#define G0_TBRQ_THRESH 0x8060c
#define TBRQ_THRESH(x) (x)
/* fill in 1 ... 7 later */
#define RH_CONFIG 0x805c0
#define PHY_INT_ENB (1<<10)
#define OAM_GID(x) (x<<7)
#define PTMR_PRE(x) (x)
#define G0_INMQ_S 0x80580
#define G0_INMQ_L 0x80584
#define G1_INMQ_S 0x80588
#define G1_INMQ_L 0x8058c
#define G2_INMQ_S 0x80590
#define G2_INMQ_L 0x80594
#define G3_INMQ_S 0x80598
#define G3_INMQ_L 0x8059c
#define G4_INMQ_S 0x805a0
#define G4_INMQ_L 0x805a4
#define G5_INMQ_S 0x805a8
#define G5_INMQ_L 0x805ac
#define G6_INMQ_S 0x805b0
#define G6_INMQ_L 0x805b4
#define G7_INMQ_S 0x805b8
#define G7_INMQ_L 0x805bc
#define TPDRQ_B_H 0x80680
#define TPDRQ_T 0x80684
#define TPDRQ_S 0x80688
#define UBUFF_BA 0x8068c
#define RLBF0_H 0x806c0
#define RLBF0_T 0x806c4
#define RLBF1_H 0x806c8
#define RLBF1_T 0x806cc
#define RLBC_H 0x806d0
#define RLBC_T 0x806d4
#define RLBC_H2 0x806d8
#define TLBF_H 0x806e0
#define TLBF_T 0x806e4
#define RLBF0_C 0x806e8
#define RLBF1_C 0x806ec
#define RXTHRSH 0x806f0
#define LITHRSH 0x806f4
#define LBARB 0x80700
#define SLICE_X(x) (x<<28)
#define ARB_RNUM_MAX(x) (x<<23)
#define TH_PRTY(x) (x<<21)
#define RH_PRTY(x) (x<<19)
#define TL_PRTY(x) (x<<17)
#define RL_PRTY(x) (x<<15)
#define BUS_MULTI(x) (x<<8)
#define NET_PREF(x) (x)
#define SDRAMCON 0x80704
#define BANK_ON (1<<14)
#define WIDE_DATA (1<<13)
#define TWR_WAIT (1<<12)
#define TRP_WAIT (1<<11)
#define TRAS_WAIT (1<<10)
#define REF_RATE(x) (x)
#define LBSTAT 0x80708
#define RCC_STAT 0x8070c
#define RCC_BUSY (1)
#define TCMCONFIG 0x80740
#define TM_DESL2 (1<<10)
#define TM_BANK_WAIT(x) (x<<6)
#define TM_ADD_BANK4(x) (x<<4)
#define TM_PAR_CHECK(x) (x<<3)
#define TM_RW_WAIT(x) (x<<2)
#define TM_SRAM_TYPE(x) (x)
#define TSRB_BA 0x80744
#define TSRC_BA 0x80748
#define TMABR_BA 0x8074c
#define TPD_BA 0x80750
#define TSRD_BA 0x80758
#define TX_CONFIG 0x80760
#define DRF_THRESH(x) (x<<22)
#define TX_UT_MODE(x) (x<<21)
#define TX_VCI_MASK(x) (x<<17)
#define LBFREE_CNT(x) (x)
#define TXAAL5_PROTO 0x80764
#define CPCS_UU(x) (x<<8)
#define CPI(x) (x)
#define RCMCONFIG 0x80780
#define RM_DESL2(x) (x<<10)
#define RM_BANK_WAIT(x) (x<<6)
#define RM_ADD_BANK(x) (x<<4)
#define RM_PAR_CHECK(x) (x<<3)
#define RM_RW_WAIT(x) (x<<2)
#define RM_SRAM_TYPE(x) (x)
#define RCMRSRB_BA 0x80784
#define RCMLBM_BA 0x80788
#define RCMABR_BA 0x8078c
#define RC_CONFIG 0x807c0
#define UT_RD_DELAY(x) (x<<11)
#define WRAP_MODE(x) (x<<10)
#define RC_UT_MODE(x) (x<<9)
#define RX_ENABLE (1<<8)
#define RX_VALVP(x) (x<<4)
#define RX_VALVC(x) (x)
#define MCC 0x807c4
#define OEC 0x807c8
#define DCC 0x807cc
#define CEC 0x807d0
#define HSP_BA 0x807f0
#define LB_CONFIG 0x807f4
#define LB_SIZE(x) (x)
#define CON_DAT 0x807f8
#define CON_CTL 0x807fc
#define CON_CTL_MBOX (2<<30)
#define CON_CTL_TCM (1<<30)
#define CON_CTL_RCM (0<<30)
#define CON_CTL_WRITE (1<<29)
#define CON_CTL_READ (0<<29)
#define CON_CTL_BUSY (1<<28)
#define CON_BYTE_DISABLE_3 (1<<22) /* 24..31 */
#define CON_BYTE_DISABLE_2 (1<<21) /* 16..23 */
#define CON_BYTE_DISABLE_1 (1<<20) /* 8..15 */
#define CON_BYTE_DISABLE_0 (1<<19) /* 0..7 */
#define CON_CTL_ADDR(x) (x)
#define FRAMER 0x80800 /* to 0x80bfc */
/* 3.3 network controller (internal) mailbox registers */
#define CS_STPER0 0x0
/* ... */
#define CS_STPER31 0x01f
#define CS_STTIM0 0x020
/* ... */
#define CS_STTIM31 0x03f
#define CS_TGRLD0 0x040
/* ... */
#define CS_TGRLD15 0x04f
#define CS_ERTHR0 0x050
#define CS_ERTHR1 0x051
#define CS_ERTHR2 0x052
#define CS_ERTHR3 0x053
#define CS_ERTHR4 0x054
#define CS_ERCTL0 0x055
#define TX_ENABLE (1<<28)
#define ER_ENABLE (1<<27)
#define CS_ERCTL1 0x056
#define CS_ERCTL2 0x057
#define CS_ERSTAT0 0x058
#define CS_ERSTAT1 0x059
#define CS_RTCCT 0x060
#define CS_RTFWC 0x061
#define CS_RTFWR 0x062
#define CS_RTFTC 0x063
#define CS_RTATR 0x064
#define CS_TFBSET 0x070
#define CS_TFBADD 0x071
#define CS_TFBSUB 0x072
#define CS_WCRMAX 0x073
#define CS_WCRMIN 0x074
#define CS_WCRINC 0x075
#define CS_WCRDEC 0x076
#define CS_WCRCEIL 0x077
#define CS_BWDCNT 0x078
#define CS_OTPPER 0x080
#define CS_OTWPER 0x081
#define CS_OTTLIM 0x082
#define CS_OTTCNT 0x083
#define CS_HGRRT0 0x090
/* ... */
#define CS_HGRRT7 0x097
#define CS_ORPTRS 0x0a0
#define RXCON_CLOSE 0x100
#define RCM_MEM_SIZE 0x10000 /* 1M of 32-bit registers */
#define TCM_MEM_SIZE 0x20000 /* 2M of 32-bit registers */
/* 2.5 transmit connection memory registers */
#define TSR0_CONN_STATE(x) ((x>>28) & 0x7)
#define TSR0_USE_WMIN (1<<23)
#define TSR0_GROUP(x) ((x & 0x7)<<18)
#define TSR0_ABR (2<<16)
#define TSR0_UBR (1<<16)
#define TSR0_CBR (0<<16)
#define TSR0_PROT (1<<15)
#define TSR0_AAL0_SDU (2<<12)
#define TSR0_AAL0 (1<<12)
#define TSR0_AAL5 (0<<12)
#define TSR0_HALT_ER (1<<11)
#define TSR0_MARK_CI (1<<10)
#define TSR0_MARK_ER (1<<9)
#define TSR0_UPDATE_GER (1<<8)
#define TSR0_RC_INDEX(x) (x & 0x1F)
#define TSR1_PCR(x) ((x & 0x7FFF)<<16)
#define TSR1_MCR(x) (x & 0x7FFF)
#define TSR2_ACR(x) ((x & 0x7FFF)<<16)
#define TSR3_NRM_CNT(x) ((x & 0xFF)<<24)
#define TSR3_CRM_CNT(x) (x & 0xFFFF)
#define TSR4_FLUSH_CONN (1<<31)
#define TSR4_SESSION_ENDED (1<<30)
#define TSR4_CRC10 (1<<28)
#define TSR4_NULL_CRC10 (1<<27)
#define TSR4_PROT (1<<26)
#define TSR4_AAL0_SDU (2<<23)
#define TSR4_AAL0 (1<<23)
#define TSR4_AAL5 (0<<23)
#define TSR9_OPEN_CONN (1<<20)
#define TSR11_ICR(x) ((x & 0x7FFF)<<16)
#define TSR11_TRM(x) ((x & 0x7)<<13)
#define TSR11_NRM(x) ((x & 0x7)<<10)
#define TSR11_ADTF(x) (x & 0x3FF)
#define TSR13_RDF(x) ((x & 0xF)<<23)
#define TSR13_RIF(x) ((x & 0xF)<<19)
#define TSR13_CDF(x) ((x & 0x7)<<16)
#define TSR13_CRM(x) (x & 0xFFFF)
#define TSR14_DELETE (1<<31)
#define TSR14_ABR_CLOSE (1<<16)
/* 2.7.1 per connection receieve state registers */
#define RSR0_START_PDU (1<<10)
#define RSR0_OPEN_CONN (1<<6)
#define RSR0_CLOSE_CONN (0<<6)
#define RSR0_PPD_ENABLE (1<<5)
#define RSR0_EPD_ENABLE (1<<4)
#define RSR0_TCP_CKSUM (1<<3)
#define RSR0_AAL5 (0)
#define RSR0_AAL0 (1)
#define RSR0_AAL0_SDU (2)
#define RSR0_RAWCELL (3)
#define RSR0_RAWCELL_CRC10 (4)
#define RSR1_AQI_ENABLE (1<<20)
#define RSR1_RBPL_ONLY (1<<19)
#define RSR1_GROUP(x) ((x)<<16)
#define RSR4_AQI_ENABLE (1<<30)
#define RSR4_GROUP(x) ((x)<<27)
#define RSR4_RBPL_ONLY (1<<26)
/* 2.1.4 transmit packet descriptor */
#define TPD_USERCELL 0x0
#define TPD_SEGMENT_OAMF5 0x4
#define TPD_END2END_OAMF5 0x5
#define TPD_RMCELL 0x6
#define TPD_CELLTYPE(x) (x<<3)
#define TPD_EOS (1<<2)
#define TPD_CLP (1<<1)
#define TPD_INT (1<<0)
#define TPD_LST (1<<31)
/* table 4.3 serial eeprom information */
#define PROD_ID 0x08 /* char[] */
#define PROD_ID_LEN 30
#define HW_REV 0x26 /* char[] */
#define M_SN 0x3a /* integer */
#define MEDIA 0x3e /* integer */
#define HE155MM 0x26
#define HE622MM 0x27
#define HE155SM 0x46
#define HE622SM 0x47
#define MAC_ADDR 0x42 /* char[] */
#define CS_LOW 0x0
#define CS_HIGH ID_CS /* HOST_CNTL_ID_PROM_SEL */
#define CLK_LOW 0x0
#define CLK_HIGH ID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */
#define SI_HIGH ID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */
#define EEPROM_DELAY 400 /* microseconds */
#endif /* _HE_H_ */

376
drivers/atm/idt77105.c
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@ -1,376 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* drivers/atm/idt77105.c - IDT77105 (PHY) driver */
/* Written 1999 by Greg Banks, NEC Australia <gnb@linuxfan.com>. Based on suni.c */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/atmdev.h>
#include <linux/sonet.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/capability.h>
#include <linux/atm_idt77105.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <asm/param.h>
#include <linux/uaccess.h>
#include "idt77105.h"
#undef GENERAL_DEBUG
#ifdef GENERAL_DEBUG
#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
#else
#define DPRINTK(format,args...)
#endif
struct idt77105_priv {
struct idt77105_stats stats; /* link diagnostics */
struct atm_dev *dev; /* device back-pointer */
struct idt77105_priv *next;
int loop_mode;
unsigned char old_mcr; /* storage of MCR reg while signal lost */
};
static DEFINE_SPINLOCK(idt77105_priv_lock);
#define PRIV(dev) ((struct idt77105_priv *) dev->phy_data)
#define PUT(val,reg) dev->ops->phy_put(dev,val,IDT77105_##reg)
#define GET(reg) dev->ops->phy_get(dev,IDT77105_##reg)
static void idt77105_stats_timer_func(struct timer_list *);
static void idt77105_restart_timer_func(struct timer_list *);
static DEFINE_TIMER(stats_timer, idt77105_stats_timer_func);
static DEFINE_TIMER(restart_timer, idt77105_restart_timer_func);
static int start_timer = 1;
static struct idt77105_priv *idt77105_all = NULL;
/*
* Retrieve the value of one of the IDT77105's counters.
* `counter' is one of the IDT77105_CTRSEL_* constants.
*/
static u16 get_counter(struct atm_dev *dev, int counter)
{
u16 val;
/* write the counter bit into PHY register 6 */
PUT(counter, CTRSEL);
/* read the low 8 bits from register 4 */
val = GET(CTRLO);
/* read the high 8 bits from register 5 */
val |= GET(CTRHI)<<8;
return val;
}
/*
* Timer function called every second to gather statistics
* from the 77105. This is done because the h/w registers
* will overflow if not read at least once per second. The
* kernel's stats are much higher precision. Also, having
* a separate copy of the stats allows implementation of
* an ioctl which gathers the stats *without* zero'ing them.
*/
static void idt77105_stats_timer_func(struct timer_list *unused)
{
struct idt77105_priv *walk;
struct atm_dev *dev;
struct idt77105_stats *stats;
DPRINTK("IDT77105 gathering statistics\n");
for (walk = idt77105_all; walk; walk = walk->next) {
dev = walk->dev;
stats = &walk->stats;
stats->symbol_errors += get_counter(dev, IDT77105_CTRSEL_SEC);
stats->tx_cells += get_counter(dev, IDT77105_CTRSEL_TCC);
stats->rx_cells += get_counter(dev, IDT77105_CTRSEL_RCC);
stats->rx_hec_errors += get_counter(dev, IDT77105_CTRSEL_RHEC);
}
if (!start_timer) mod_timer(&stats_timer,jiffies+IDT77105_STATS_TIMER_PERIOD);
}
/*
* A separate timer func which handles restarting PHY chips which
* have had the cable re-inserted after being pulled out. This is
* done by polling the Good Signal Bit in the Interrupt Status
* register every 5 seconds. The other technique (checking Good
* Signal Bit in the interrupt handler) cannot be used because PHY
* interrupts need to be disabled when the cable is pulled out
* to avoid lots of spurious cell error interrupts.
*/
static void idt77105_restart_timer_func(struct timer_list *unused)
{
struct idt77105_priv *walk;
struct atm_dev *dev;
unsigned char istat;
DPRINTK("IDT77105 checking for cable re-insertion\n");
for (walk = idt77105_all; walk; walk = walk->next) {
dev = walk->dev;
if (dev->signal != ATM_PHY_SIG_LOST)
continue;
istat = GET(ISTAT); /* side effect: clears all interrupt status bits */
if (istat & IDT77105_ISTAT_GOODSIG) {
/* Found signal again */
atm_dev_signal_change(dev, ATM_PHY_SIG_FOUND);
printk(KERN_NOTICE "%s(itf %d): signal detected again\n",
dev->type,dev->number);
/* flush the receive FIFO */
PUT( GET(DIAG) | IDT77105_DIAG_RFLUSH, DIAG);
/* re-enable interrupts */
PUT( walk->old_mcr ,MCR);
}
}
if (!start_timer) mod_timer(&restart_timer,jiffies+IDT77105_RESTART_TIMER_PERIOD);
}
static int fetch_stats(struct atm_dev *dev,struct idt77105_stats __user *arg,int zero)
{
unsigned long flags;
struct idt77105_stats stats;
spin_lock_irqsave(&idt77105_priv_lock, flags);
memcpy(&stats, &PRIV(dev)->stats, sizeof(struct idt77105_stats));
if (zero)
memset(&PRIV(dev)->stats, 0, sizeof(struct idt77105_stats));
spin_unlock_irqrestore(&idt77105_priv_lock, flags);
if (arg == NULL)
return 0;
return copy_to_user(arg, &stats,
sizeof(struct idt77105_stats)) ? -EFAULT : 0;
}
static int set_loopback(struct atm_dev *dev,int mode)
{
int diag;
diag = GET(DIAG) & ~IDT77105_DIAG_LCMASK;
switch (mode) {
case ATM_LM_NONE:
break;
case ATM_LM_LOC_ATM:
diag |= IDT77105_DIAG_LC_PHY_LOOPBACK;
break;
case ATM_LM_RMT_ATM:
diag |= IDT77105_DIAG_LC_LINE_LOOPBACK;
break;
default:
return -EINVAL;
}
PUT(diag,DIAG);
printk(KERN_NOTICE "%s(%d) Loopback mode is: %s\n", dev->type,
dev->number,
(mode == ATM_LM_NONE ? "NONE" :
(mode == ATM_LM_LOC_ATM ? "DIAG (local)" :
(mode == IDT77105_DIAG_LC_LINE_LOOPBACK ? "LOOP (remote)" :
"unknown")))
);
PRIV(dev)->loop_mode = mode;
return 0;
}
static int idt77105_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
{
printk(KERN_NOTICE "%s(%d) idt77105_ioctl() called\n",dev->type,dev->number);
switch (cmd) {
case IDT77105_GETSTATZ:
if (!capable(CAP_NET_ADMIN)) return -EPERM;
fallthrough;
case IDT77105_GETSTAT:
return fetch_stats(dev, arg, cmd == IDT77105_GETSTATZ);
case ATM_SETLOOP:
return set_loopback(dev,(int)(unsigned long) arg);
case ATM_GETLOOP:
return put_user(PRIV(dev)->loop_mode,(int __user *)arg) ?
-EFAULT : 0;
case ATM_QUERYLOOP:
return put_user(ATM_LM_LOC_ATM | ATM_LM_RMT_ATM,
(int __user *) arg) ? -EFAULT : 0;
default:
return -ENOIOCTLCMD;
}
}
static void idt77105_int(struct atm_dev *dev)
{
unsigned char istat;
istat = GET(ISTAT); /* side effect: clears all interrupt status bits */
DPRINTK("IDT77105 generated an interrupt, istat=%02x\n", (unsigned)istat);
if (istat & IDT77105_ISTAT_RSCC) {
/* Rx Signal Condition Change - line went up or down */
if (istat & IDT77105_ISTAT_GOODSIG) { /* signal detected again */
/* This should not happen (restart timer does it) but JIC */
atm_dev_signal_change(dev, ATM_PHY_SIG_FOUND);
} else { /* signal lost */
/*
* Disable interrupts and stop all transmission and
* reception - the restart timer will restore these.
*/
PRIV(dev)->old_mcr = GET(MCR);
PUT(
(PRIV(dev)->old_mcr|
IDT77105_MCR_DREC|
IDT77105_MCR_DRIC|
IDT77105_MCR_HALTTX
) & ~IDT77105_MCR_EIP, MCR);
atm_dev_signal_change(dev, ATM_PHY_SIG_LOST);
printk(KERN_NOTICE "%s(itf %d): signal lost\n",
dev->type,dev->number);
}
}
if (istat & IDT77105_ISTAT_RFO) {
/* Rx FIFO Overrun -- perform a FIFO flush */
PUT( GET(DIAG) | IDT77105_DIAG_RFLUSH, DIAG);
printk(KERN_NOTICE "%s(itf %d): receive FIFO overrun\n",
dev->type,dev->number);
}
#ifdef GENERAL_DEBUG
if (istat & (IDT77105_ISTAT_HECERR | IDT77105_ISTAT_SCR |
IDT77105_ISTAT_RSE)) {
/* normally don't care - just report in stats */
printk(KERN_NOTICE "%s(itf %d): received cell with error\n",
dev->type,dev->number);
}
#endif
}
static int idt77105_start(struct atm_dev *dev)
{
unsigned long flags;
if (!(dev->phy_data = kmalloc_obj(struct idt77105_priv)))
return -ENOMEM;
PRIV(dev)->dev = dev;
spin_lock_irqsave(&idt77105_priv_lock, flags);
PRIV(dev)->next = idt77105_all;
idt77105_all = PRIV(dev);
spin_unlock_irqrestore(&idt77105_priv_lock, flags);
memset(&PRIV(dev)->stats,0,sizeof(struct idt77105_stats));
/* initialise dev->signal from Good Signal Bit */
atm_dev_signal_change(dev,
GET(ISTAT) & IDT77105_ISTAT_GOODSIG ?
ATM_PHY_SIG_FOUND : ATM_PHY_SIG_LOST);
if (dev->signal == ATM_PHY_SIG_LOST)
printk(KERN_WARNING "%s(itf %d): no signal\n",dev->type,
dev->number);
/* initialise loop mode from hardware */
switch ( GET(DIAG) & IDT77105_DIAG_LCMASK ) {
case IDT77105_DIAG_LC_NORMAL:
PRIV(dev)->loop_mode = ATM_LM_NONE;
break;
case IDT77105_DIAG_LC_PHY_LOOPBACK:
PRIV(dev)->loop_mode = ATM_LM_LOC_ATM;
break;
case IDT77105_DIAG_LC_LINE_LOOPBACK:
PRIV(dev)->loop_mode = ATM_LM_RMT_ATM;
break;
}
/* enable interrupts, e.g. on loss of signal */
PRIV(dev)->old_mcr = GET(MCR);
if (dev->signal == ATM_PHY_SIG_FOUND) {
PRIV(dev)->old_mcr |= IDT77105_MCR_EIP;
PUT(PRIV(dev)->old_mcr, MCR);
}
idt77105_stats_timer_func(0); /* clear 77105 counters */
(void) fetch_stats(dev,NULL,1); /* clear kernel counters */
spin_lock_irqsave(&idt77105_priv_lock, flags);
if (start_timer) {
start_timer = 0;
stats_timer.expires = jiffies+IDT77105_STATS_TIMER_PERIOD;
add_timer(&stats_timer);
restart_timer.expires = jiffies+IDT77105_RESTART_TIMER_PERIOD;
add_timer(&restart_timer);
}
spin_unlock_irqrestore(&idt77105_priv_lock, flags);
return 0;
}
static int idt77105_stop(struct atm_dev *dev)
{
struct idt77105_priv *walk, *prev;
DPRINTK("%s(itf %d): stopping IDT77105\n",dev->type,dev->number);
/* disable interrupts */
PUT( GET(MCR) & ~IDT77105_MCR_EIP, MCR );
/* detach private struct from atm_dev & free */
for (prev = NULL, walk = idt77105_all ;
walk != NULL;
prev = walk, walk = walk->next) {
if (walk->dev == dev) {
if (prev != NULL)
prev->next = walk->next;
else
idt77105_all = walk->next;
dev->phy = NULL;
dev->phy_data = NULL;
kfree(walk);
break;
}
}
return 0;
}
static const struct atmphy_ops idt77105_ops = {
.start = idt77105_start,
.ioctl = idt77105_ioctl,
.interrupt = idt77105_int,
.stop = idt77105_stop,
};
int idt77105_init(struct atm_dev *dev)
{
dev->phy = &idt77105_ops;
return 0;
}
EXPORT_SYMBOL(idt77105_init);
static void __exit idt77105_exit(void)
{
/* turn off timers */
timer_delete_sync(&stats_timer);
timer_delete_sync(&restart_timer);
}
module_exit(idt77105_exit);
MODULE_DESCRIPTION("IDT77105 PHY driver");
MODULE_LICENSE("GPL");

92
drivers/atm/idt77105.h
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/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/idt77105.h - IDT77105 (PHY) declarations */
/* Written 1999 by Greg Banks, NEC Australia <gnb@linuxfan.com>. Based on suni.h */
#ifndef DRIVER_ATM_IDT77105_H
#define DRIVER_ATM_IDT77105_H
#include <linux/atmdev.h>
#include <linux/atmioc.h>
/* IDT77105 registers */
#define IDT77105_MCR 0x0 /* Master Control Register */
#define IDT77105_ISTAT 0x1 /* Interrupt Status */
#define IDT77105_DIAG 0x2 /* Diagnostic Control */
#define IDT77105_LEDHEC 0x3 /* LED Driver & HEC Status/Control */
#define IDT77105_CTRLO 0x4 /* Low Byte Counter Register */
#define IDT77105_CTRHI 0x5 /* High Byte Counter Register */
#define IDT77105_CTRSEL 0x6 /* Counter Register Read Select */
/* IDT77105 register values */
/* MCR */
#define IDT77105_MCR_UPLO 0x80 /* R/W, User Prog'le Output Latch */
#define IDT77105_MCR_DREC 0x40 /* R/W, Discard Receive Error Cells */
#define IDT77105_MCR_ECEIO 0x20 /* R/W, Enable Cell Error Interrupts
* Only */
#define IDT77105_MCR_TDPC 0x10 /* R/W, Transmit Data Parity Check */
#define IDT77105_MCR_DRIC 0x08 /* R/W, Discard Received Idle Cells */
#define IDT77105_MCR_HALTTX 0x04 /* R/W, Halt Tx */
#define IDT77105_MCR_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */
#define IDT77105_MCR_EIP 0x01 /* R/W, Enable Interrupt Pin */
/* ISTAT */
#define IDT77105_ISTAT_GOODSIG 0x40 /* R, Good Signal Bit */
#define IDT77105_ISTAT_HECERR 0x20 /* sticky, HEC Error*/
#define IDT77105_ISTAT_SCR 0x10 /* sticky, Short Cell Received */
#define IDT77105_ISTAT_TPE 0x08 /* sticky, Transmit Parity Error */
#define IDT77105_ISTAT_RSCC 0x04 /* sticky, Rx Signal Condition Change */
#define IDT77105_ISTAT_RSE 0x02 /* sticky, Rx Symbol Error */
#define IDT77105_ISTAT_RFO 0x01 /* sticky, Rx FIFO Overrun */
/* DIAG */
#define IDT77105_DIAG_FTD 0x80 /* R/W, Force TxClav deassert */
#define IDT77105_DIAG_ROS 0x40 /* R/W, RxClav operation select */
#define IDT77105_DIAG_MPCS 0x20 /* R/W, Multi-PHY config'n select */
#define IDT77105_DIAG_RFLUSH 0x10 /* R/W, clear receive FIFO */
#define IDT77105_DIAG_ITPE 0x08 /* R/W, Insert Tx payload error */
#define IDT77105_DIAG_ITHE 0x04 /* R/W, Insert Tx HEC error */
#define IDT77105_DIAG_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */
#define IDT77105_DIAG_LCMASK 0x03 /* R/W, Loopback Control */
#define IDT77105_DIAG_LC_NORMAL 0x00 /* Receive from network */
#define IDT77105_DIAG_LC_PHY_LOOPBACK 0x02
#define IDT77105_DIAG_LC_LINE_LOOPBACK 0x03
/* LEDHEC */
#define IDT77105_LEDHEC_DRHC 0x40 /* R/W, Disable Rx HEC check */
#define IDT77105_LEDHEC_DTHC 0x20 /* R/W, Disable Tx HEC calculation */
#define IDT77105_LEDHEC_RPWMASK 0x18 /* R/W, RxRef pulse width select */
#define IDT77105_LEDHEC_TFS 0x04 /* R, Tx FIFO Status (1=empty) */
#define IDT77105_LEDHEC_TLS 0x02 /* R, Tx LED Status (1=lit) */
#define IDT77105_LEDHEC_RLS 0x01 /* R, Rx LED Status (1=lit) */
#define IDT77105_LEDHEC_RPW_1 0x00 /* RxRef active for 1 RxClk cycle */
#define IDT77105_LEDHEC_RPW_2 0x08 /* RxRef active for 2 RxClk cycle */
#define IDT77105_LEDHEC_RPW_4 0x10 /* RxRef active for 4 RxClk cycle */
#define IDT77105_LEDHEC_RPW_8 0x18 /* RxRef active for 8 RxClk cycle */
/* CTRSEL */
#define IDT77105_CTRSEL_SEC 0x08 /* W, Symbol Error Counter */
#define IDT77105_CTRSEL_TCC 0x04 /* W, Tx Cell Counter */
#define IDT77105_CTRSEL_RCC 0x02 /* W, Rx Cell Counter */
#define IDT77105_CTRSEL_RHEC 0x01 /* W, Rx HEC Error Counter */
#ifdef __KERNEL__
int idt77105_init(struct atm_dev *dev);
#endif
/*
* Tunable parameters
*/
/* Time between samples of the hardware cell counters. Should be <= 1 sec */
#define IDT77105_STATS_TIMER_PERIOD (HZ)
/* Time between checks to see if the signal has been found again */
#define IDT77105_RESTART_TIMER_PERIOD (5 * HZ)
#endif

3797
drivers/atm/idt77252.c
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drivers/atm/idt77252.h
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/*******************************************************************
*
* Copyright (c) 2000 ATecoM GmbH
*
* The author may be reached at ecd@atecom.com.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*******************************************************************/
#ifndef _IDT77252_H
#define _IDT77252_H 1
#include <linux/ptrace.h>
#include <linux/skbuff.h>
#include <linux/workqueue.h>
#include <linux/mutex.h>
/*****************************************************************************/
/* */
/* Makros */
/* */
/*****************************************************************************/
#define VPCI2VC(card, vpi, vci) \
(((vpi) << card->vcibits) | ((vci) & card->vcimask))
/*****************************************************************************/
/* */
/* DEBUGGING definitions */
/* */
/*****************************************************************************/
#define DBG_RAW_CELL 0x00000400
#define DBG_TINY 0x00000200
#define DBG_GENERAL 0x00000100
#define DBG_XGENERAL 0x00000080
#define DBG_INIT 0x00000040
#define DBG_DEINIT 0x00000020
#define DBG_INTERRUPT 0x00000010
#define DBG_OPEN_CONN 0x00000008
#define DBG_CLOSE_CONN 0x00000004
#define DBG_RX_DATA 0x00000002
#define DBG_TX_DATA 0x00000001
#ifdef CONFIG_ATM_IDT77252_DEBUG
#define CPRINTK(args...) do { if (debug & DBG_CLOSE_CONN) printk(args); } while(0)
#define OPRINTK(args...) do { if (debug & DBG_OPEN_CONN) printk(args); } while(0)
#define IPRINTK(args...) do { if (debug & DBG_INIT) printk(args); } while(0)
#define INTPRINTK(args...) do { if (debug & DBG_INTERRUPT) printk(args); } while(0)
#define DIPRINTK(args...) do { if (debug & DBG_DEINIT) printk(args); } while(0)
#define TXPRINTK(args...) do { if (debug & DBG_TX_DATA) printk(args); } while(0)
#define RXPRINTK(args...) do { if (debug & DBG_RX_DATA) printk(args); } while(0)
#define XPRINTK(args...) do { if (debug & DBG_XGENERAL) printk(args); } while(0)
#define DPRINTK(args...) do { if (debug & DBG_GENERAL) printk(args); } while(0)
#define NPRINTK(args...) do { if (debug & DBG_TINY) printk(args); } while(0)
#define RPRINTK(args...) do { if (debug & DBG_RAW_CELL) printk(args); } while(0)
#else
#define CPRINTK(args...) do { } while(0)
#define OPRINTK(args...) do { } while(0)
#define IPRINTK(args...) do { } while(0)
#define INTPRINTK(args...) do { } while(0)
#define DIPRINTK(args...) do { } while(0)
#define TXPRINTK(args...) do { } while(0)
#define RXPRINTK(args...) do { } while(0)
#define XPRINTK(args...) do { } while(0)
#define DPRINTK(args...) do { } while(0)
#define NPRINTK(args...) do { } while(0)
#define RPRINTK(args...) do { } while(0)
#endif
#define SCHED_UBR0 0
#define SCHED_UBR 1
#define SCHED_VBR 2
#define SCHED_ABR 3
#define SCHED_CBR 4
#define SCQFULL_TIMEOUT HZ
/*****************************************************************************/
/* */
/* Free Buffer Queue Layout */
/* */
/*****************************************************************************/
#define SAR_FB_SIZE_0 (2048 - 256)
#define SAR_FB_SIZE_1 (4096 - 256)
#define SAR_FB_SIZE_2 (8192 - 256)
#define SAR_FB_SIZE_3 (16384 - 256)
#define SAR_FBQ0_LOW 4
#define SAR_FBQ0_HIGH 8
#define SAR_FBQ1_LOW 2
#define SAR_FBQ1_HIGH 4
#define SAR_FBQ2_LOW 1
#define SAR_FBQ2_HIGH 2
#define SAR_FBQ3_LOW 1
#define SAR_FBQ3_HIGH 2
#if 0
#define SAR_TST_RESERVED 44 /* Num TST reserved for UBR/ABR/VBR */
#else
#define SAR_TST_RESERVED 0 /* Num TST reserved for UBR/ABR/VBR */
#endif
#define TCT_CBR 0x00000000
#define TCT_UBR 0x00000000
#define TCT_VBR 0x40000000
#define TCT_ABR 0x80000000
#define TCT_TYPE 0xc0000000
#define TCT_RR 0x20000000
#define TCT_LMCR 0x08000000
#define TCT_SCD_MASK 0x0007ffff
#define TCT_TSIF 0x00004000
#define TCT_HALT 0x80000000
#define TCT_IDLE 0x40000000
#define TCT_FLAG_UBR 0x80000000
/*****************************************************************************/
/* */
/* Structure describing an IDT77252 */
/* */
/*****************************************************************************/
struct scqe
{
u32 word_1;
u32 word_2;
u32 word_3;
u32 word_4;
};
#define SCQ_ENTRIES 64
#define SCQ_SIZE (SCQ_ENTRIES * sizeof(struct scqe))
#define SCQ_MASK (SCQ_SIZE - 1)
struct scq_info
{
struct scqe *base;
struct scqe *next;
struct scqe *last;
dma_addr_t paddr;
spinlock_t lock;
atomic_t used;
unsigned long trans_start;
unsigned long scd;
spinlock_t skblock;
struct sk_buff_head transmit;
struct sk_buff_head pending;
};
struct rx_pool {
struct sk_buff_head queue;
unsigned int len;
};
struct aal1 {
unsigned int total;
unsigned int count;
struct sk_buff *data;
unsigned char sequence;
};
struct vc_map;
struct rate_estimator {
struct timer_list timer;
unsigned int interval;
unsigned int ewma_log;
u64 cells;
u64 last_cells;
long avcps;
u32 cps;
u32 maxcps;
struct vc_map *vc;
};
struct vc_map {
unsigned int index;
unsigned long flags;
#define VCF_TX 0
#define VCF_RX 1
#define VCF_IDLE 2
#define VCF_RSV 3
unsigned int class;
u8 init_er;
u8 lacr;
u8 max_er;
unsigned int ntste;
spinlock_t lock;
struct atm_vcc *tx_vcc;
struct atm_vcc *rx_vcc;
struct idt77252_dev *card;
struct scq_info *scq; /* To keep track of the SCQ */
struct rate_estimator *estimator;
int scd_index;
union {
struct rx_pool rx_pool;
struct aal1 aal1;
} rcv;
};
/*****************************************************************************/
/* */
/* RCTE - Receive Connection Table Entry */
/* */
/*****************************************************************************/
struct rct_entry
{
u32 word_1;
u32 buffer_handle;
u32 dma_address;
u32 aal5_crc32;
};
/*****************************************************************************/
/* */
/* RSQ - Receive Status Queue */
/* */
/*****************************************************************************/
#define SAR_RSQE_VALID 0x80000000
#define SAR_RSQE_IDLE 0x40000000
#define SAR_RSQE_BUF_MASK 0x00030000
#define SAR_RSQE_BUF_ASGN 0x00008000
#define SAR_RSQE_NZGFC 0x00004000
#define SAR_RSQE_EPDU 0x00002000
#define SAR_RSQE_BUF_CONT 0x00001000
#define SAR_RSQE_EFCIE 0x00000800
#define SAR_RSQE_CLP 0x00000400
#define SAR_RSQE_CRC 0x00000200
#define SAR_RSQE_CELLCNT 0x000001FF
#define RSQSIZE 8192
#define RSQ_NUM_ENTRIES (RSQSIZE / 16)
#define RSQ_ALIGNMENT 8192
struct rsq_entry {
u32 word_1;
u32 word_2;
u32 word_3;
u32 word_4;
};
struct rsq_info {
struct rsq_entry *base;
struct rsq_entry *next;
struct rsq_entry *last;
dma_addr_t paddr;
};
/*****************************************************************************/
/* */
/* TSQ - Transmit Status Queue */
/* */
/*****************************************************************************/
#define SAR_TSQE_INVALID 0x80000000
#define SAR_TSQE_TIMESTAMP 0x00FFFFFF
#define SAR_TSQE_TYPE 0x60000000
#define SAR_TSQE_TYPE_TIMER 0x00000000
#define SAR_TSQE_TYPE_TSR 0x20000000
#define SAR_TSQE_TYPE_IDLE 0x40000000
#define SAR_TSQE_TYPE_TBD_COMP 0x60000000
#define SAR_TSQE_TAG(stat) (((stat) >> 24) & 0x1f)
#define TSQSIZE 8192
#define TSQ_NUM_ENTRIES 1024
#define TSQ_ALIGNMENT 8192
struct tsq_entry
{
u32 word_1;
u32 word_2;
};
struct tsq_info
{
struct tsq_entry *base;
struct tsq_entry *next;
struct tsq_entry *last;
dma_addr_t paddr;
};
struct tst_info
{
struct vc_map *vc;
u32 tste;
};
#define TSTE_MASK 0x601fffff
#define TSTE_OPC_MASK 0x60000000
#define TSTE_OPC_NULL 0x00000000
#define TSTE_OPC_CBR 0x20000000
#define TSTE_OPC_VAR 0x40000000
#define TSTE_OPC_JMP 0x60000000
#define TSTE_PUSH_IDLE 0x01000000
#define TSTE_PUSH_ACTIVE 0x02000000
#define TST_SWITCH_DONE 0
#define TST_SWITCH_PENDING 1
#define TST_SWITCH_WAIT 2
#define FBQ_SHIFT 9
#define FBQ_SIZE (1 << FBQ_SHIFT)
#define FBQ_MASK (FBQ_SIZE - 1)
struct sb_pool
{
unsigned int index;
struct sk_buff *skb[FBQ_SIZE];
};
#define POOL_HANDLE(queue, index) (((queue + 1) << 16) | (index))
#define POOL_QUEUE(handle) (((handle) >> 16) - 1)
#define POOL_INDEX(handle) ((handle) & 0xffff)
struct idt77252_dev
{
struct tsq_info tsq; /* Transmit Status Queue */
struct rsq_info rsq; /* Receive Status Queue */
struct pci_dev *pcidev; /* PCI handle (desriptor) */
struct atm_dev *atmdev; /* ATM device desriptor */
void __iomem *membase; /* SAR's memory base address */
unsigned long srambase; /* SAR's sram base address */
void __iomem *fbq[4]; /* FBQ fill addresses */
struct mutex mutex;
spinlock_t cmd_lock; /* for r/w utility/sram */
unsigned long softstat;
unsigned long flags; /* see blow */
struct work_struct tqueue;
unsigned long tct_base; /* TCT base address in SRAM */
unsigned long rct_base; /* RCT base address in SRAM */
unsigned long rt_base; /* Rate Table base in SRAM */
unsigned long scd_base; /* SCD base address in SRAM */
unsigned long tst[2]; /* TST base address in SRAM */
unsigned long abrst_base; /* ABRST base address in SRAM */
unsigned long fifo_base; /* RX FIFO base in SRAM */
unsigned long irqstat[16];
unsigned int sramsize; /* SAR's sram size */
unsigned int tct_size; /* total TCT entries */
unsigned int rct_size; /* total RCT entries */
unsigned int scd_size; /* length of SCD */
unsigned int tst_size; /* total TST entries */
unsigned int tst_free; /* free TSTEs in TST */
unsigned int abrst_size; /* size of ABRST in words */
unsigned int fifo_size; /* size of RX FIFO in words */
unsigned int vpibits; /* Bits used for VPI index */
unsigned int vcibits; /* Bits used for VCI index */
unsigned int vcimask; /* Mask for VCI index */
unsigned int utopia_pcr; /* Utopia Itf's Cell Rate */
unsigned int link_pcr; /* PHY's Peek Cell Rate */
struct vc_map **vcs; /* Open Connections */
struct vc_map **scd2vc; /* SCD to Connection map */
struct tst_info *soft_tst; /* TST to Connection map */
unsigned int tst_index; /* Current TST in use */
struct timer_list tst_timer;
spinlock_t tst_lock;
unsigned long tst_state;
struct sb_pool sbpool[4]; /* Pool of RX skbuffs */
struct sk_buff *raw_cell_head; /* Pointer to raw cell queue */
u32 *raw_cell_hnd; /* Pointer to RCQ handle */
dma_addr_t raw_cell_paddr;
int index; /* SAR's ID */
int revision; /* chip revision */
char name[16]; /* Device name */
struct idt77252_dev *next;
};
/* definition for flag field above */
#define IDT77252_BIT_INIT 1
#define IDT77252_BIT_INTERRUPT 2
#define ATM_CELL_PAYLOAD 48
#define FREEBUF_ALIGNMENT 16
/*****************************************************************************/
/* */
/* Makros */
/* */
/*****************************************************************************/
#define ALIGN_ADDRESS(addr, alignment) \
((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))
/*****************************************************************************/
/* */
/* ABR SAR Network operation Register */
/* */
/*****************************************************************************/
#define SAR_REG_DR0 (card->membase + 0x00)
#define SAR_REG_DR1 (card->membase + 0x04)
#define SAR_REG_DR2 (card->membase + 0x08)
#define SAR_REG_DR3 (card->membase + 0x0C)
#define SAR_REG_CMD (card->membase + 0x10)
#define SAR_REG_CFG (card->membase + 0x14)
#define SAR_REG_STAT (card->membase + 0x18)
#define SAR_REG_RSQB (card->membase + 0x1C)
#define SAR_REG_RSQT (card->membase + 0x20)
#define SAR_REG_RSQH (card->membase + 0x24)
#define SAR_REG_CDC (card->membase + 0x28)
#define SAR_REG_VPEC (card->membase + 0x2C)
#define SAR_REG_ICC (card->membase + 0x30)
#define SAR_REG_RAWCT (card->membase + 0x34)
#define SAR_REG_TMR (card->membase + 0x38)
#define SAR_REG_TSTB (card->membase + 0x3C)
#define SAR_REG_TSQB (card->membase + 0x40)
#define SAR_REG_TSQT (card->membase + 0x44)
#define SAR_REG_TSQH (card->membase + 0x48)
#define SAR_REG_GP (card->membase + 0x4C)
#define SAR_REG_VPM (card->membase + 0x50)
#define SAR_REG_RXFD (card->membase + 0x54)
#define SAR_REG_RXFT (card->membase + 0x58)
#define SAR_REG_RXFH (card->membase + 0x5C)
#define SAR_REG_RAWHND (card->membase + 0x60)
#define SAR_REG_RXSTAT (card->membase + 0x64)
#define SAR_REG_ABRSTD (card->membase + 0x68)
#define SAR_REG_ABRRQ (card->membase + 0x6C)
#define SAR_REG_VBRRQ (card->membase + 0x70)
#define SAR_REG_RTBL (card->membase + 0x74)
#define SAR_REG_MDFCT (card->membase + 0x78)
#define SAR_REG_TXSTAT (card->membase + 0x7C)
#define SAR_REG_TCMDQ (card->membase + 0x80)
#define SAR_REG_IRCP (card->membase + 0x84)
#define SAR_REG_FBQP0 (card->membase + 0x88)
#define SAR_REG_FBQP1 (card->membase + 0x8C)
#define SAR_REG_FBQP2 (card->membase + 0x90)
#define SAR_REG_FBQP3 (card->membase + 0x94)
#define SAR_REG_FBQS0 (card->membase + 0x98)
#define SAR_REG_FBQS1 (card->membase + 0x9C)
#define SAR_REG_FBQS2 (card->membase + 0xA0)
#define SAR_REG_FBQS3 (card->membase + 0xA4)
#define SAR_REG_FBQWP0 (card->membase + 0xA8)
#define SAR_REG_FBQWP1 (card->membase + 0xAC)
#define SAR_REG_FBQWP2 (card->membase + 0xB0)
#define SAR_REG_FBQWP3 (card->membase + 0xB4)
#define SAR_REG_NOW (card->membase + 0xB8)
/*****************************************************************************/
/* */
/* Commands */
/* */
/*****************************************************************************/
#define SAR_CMD_NO_OPERATION 0x00000000
#define SAR_CMD_OPENCLOSE_CONNECTION 0x20000000
#define SAR_CMD_WRITE_SRAM 0x40000000
#define SAR_CMD_READ_SRAM 0x50000000
#define SAR_CMD_READ_UTILITY 0x80000000
#define SAR_CMD_WRITE_UTILITY 0x90000000
#define SAR_CMD_OPEN_CONNECTION (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000)
#define SAR_CMD_CLOSE_CONNECTION SAR_CMD_OPENCLOSE_CONNECTION
/*****************************************************************************/
/* */
/* Configuration Register bits */
/* */
/*****************************************************************************/
#define SAR_CFG_SWRST 0x80000000 /* Software reset */
#define SAR_CFG_LOOP 0x40000000 /* Internal Loopback */
#define SAR_CFG_RXPTH 0x20000000 /* Receive Path Enable */
#define SAR_CFG_IDLE_CLP 0x10000000 /* SAR set CLP Bits of Null Cells */
#define SAR_CFG_TX_FIFO_SIZE_1 0x04000000 /* TX FIFO Size = 1 cell */
#define SAR_CFG_TX_FIFO_SIZE_2 0x08000000 /* TX FIFO Size = 2 cells */
#define SAR_CFG_TX_FIFO_SIZE_4 0x0C000000 /* TX FIFO Size = 4 cells */
#define SAR_CFG_TX_FIFO_SIZE_9 0x00000000 /* TX FIFO Size = 9 cells (full) */
#define SAR_CFG_NO_IDLE 0x02000000 /* SAR sends no Null Cells */
#define SAR_CFG_RSVD1 0x01000000 /* Reserved */
#define SAR_CFG_RXSTQ_SIZE_2k 0x00000000 /* RX Stat Queue Size = 2048 byte */
#define SAR_CFG_RXSTQ_SIZE_4k 0x00400000 /* RX Stat Queue Size = 4096 byte */
#define SAR_CFG_RXSTQ_SIZE_8k 0x00800000 /* RX Stat Queue Size = 8192 byte */
#define SAR_CFG_RXSTQ_SIZE_R 0x00C00000 /* RX Stat Queue Size = reserved */
#define SAR_CFG_ICAPT 0x00200000 /* accept Invalid Cells */
#define SAR_CFG_IGGFC 0x00100000 /* Ignore GFC */
#define SAR_CFG_VPVCS_0 0x00000000 /* VPI/VCI Select bit range */
#define SAR_CFG_VPVCS_1 0x00040000 /* VPI/VCI Select bit range */
#define SAR_CFG_VPVCS_2 0x00080000 /* VPI/VCI Select bit range */
#define SAR_CFG_VPVCS_8 0x000C0000 /* VPI/VCI Select bit range */
#define SAR_CFG_CNTBL_1k 0x00000000 /* Connection Table Size */
#define SAR_CFG_CNTBL_4k 0x00010000 /* Connection Table Size */
#define SAR_CFG_CNTBL_16k 0x00020000 /* Connection Table Size */
#define SAR_CFG_CNTBL_512 0x00030000 /* Connection Table Size */
#define SAR_CFG_VPECA 0x00008000 /* VPI/VCI Error Cell Accept */
#define SAR_CFG_RXINT_NOINT 0x00000000 /* No Interrupt on PDU received */
#define SAR_CFG_RXINT_NODELAY 0x00001000 /* Interrupt without delay to host*/
#define SAR_CFG_RXINT_256US 0x00002000 /* Interrupt with delay 256 usec */
#define SAR_CFG_RXINT_505US 0x00003000 /* Interrupt with delay 505 usec */
#define SAR_CFG_RXINT_742US 0x00004000 /* Interrupt with delay 742 usec */
#define SAR_CFG_RAWIE 0x00000800 /* Raw Cell Queue Interrupt Enable*/
#define SAR_CFG_RQFIE 0x00000400 /* RSQ Almost Full Int Enable */
#define SAR_CFG_RSVD2 0x00000200 /* Reserved */
#define SAR_CFG_CACHE 0x00000100 /* DMA on Cache Line Boundary */
#define SAR_CFG_TMOIE 0x00000080 /* Timer Roll Over Int Enable */
#define SAR_CFG_FBIE 0x00000040 /* Free Buffer Queue Int Enable */
#define SAR_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
#define SAR_CFG_TXINT 0x00000010 /* Transmit status Int Enable */
#define SAR_CFG_TXUIE 0x00000008 /* Transmit underrun Int Enable */
#define SAR_CFG_UMODE 0x00000004 /* Utopia Mode Select */
#define SAR_CFG_TXSFI 0x00000002 /* Transmit status Full Int Enable*/
#define SAR_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
#define SAR_CFG_TX_FIFO_SIZE_MASK 0x0C000000 /* TX FIFO Size Mask */
#define SAR_CFG_RXSTQSIZE_MASK 0x00C00000
#define SAR_CFG_CNTBL_MASK 0x00030000
#define SAR_CFG_RXINT_MASK 0x00007000
/*****************************************************************************/
/* */
/* Status Register bits */
/* */
/*****************************************************************************/
#define SAR_STAT_FRAC_3 0xF0000000 /* Fraction of Free Buffer Queue 3 */
#define SAR_STAT_FRAC_2 0x0F000000 /* Fraction of Free Buffer Queue 2 */
#define SAR_STAT_FRAC_1 0x00F00000 /* Fraction of Free Buffer Queue 1 */
#define SAR_STAT_FRAC_0 0x000F0000 /* Fraction of Free Buffer Queue 0 */
#define SAR_STAT_TSIF 0x00008000 /* Transmit Status Indicator */
#define SAR_STAT_TXICP 0x00004000 /* Transmit Status Indicator */
#define SAR_STAT_RSVD1 0x00002000 /* Reserved */
#define SAR_STAT_TSQF 0x00001000 /* Transmit Status Queue full */
#define SAR_STAT_TMROF 0x00000800 /* Timer overflow */
#define SAR_STAT_PHYI 0x00000400 /* PHY device Interrupt flag */
#define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Command Busy Flag */
#define SAR_STAT_FBQ3A 0x00000100 /* Free Buffer Queue 3 Attention */
#define SAR_STAT_FBQ2A 0x00000080 /* Free Buffer Queue 2 Attention */
#define SAR_STAT_RSQF 0x00000040 /* Receive Status Queue full */
#define SAR_STAT_EPDU 0x00000020 /* End Of PDU Flag */
#define SAR_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
#define SAR_STAT_FBQ1A 0x00000008 /* Free Buffer Queue 1 Attention */
#define SAR_STAT_FBQ0A 0x00000004 /* Free Buffer Queue 0 Attention */
#define SAR_STAT_RSQAF 0x00000002 /* Receive Status Queue almost full*/
#define SAR_STAT_RSVD2 0x00000001 /* Reserved */
/*****************************************************************************/
/* */
/* General Purpose Register bits */
/* */
/*****************************************************************************/
#define SAR_GP_TXNCC_MASK 0xff000000 /* Transmit Negative Credit Count */
#define SAR_GP_EEDI 0x00010000 /* EEPROM Data In */
#define SAR_GP_BIGE 0x00008000 /* Big Endian Operation */
#define SAR_GP_RM_NORMAL 0x00000000 /* Normal handling of RM cells */
#define SAR_GP_RM_TO_RCQ 0x00002000 /* put RM cells into Raw Cell Queue */
#define SAR_GP_RM_RSVD 0x00004000 /* Reserved */
#define SAR_GP_RM_INHIBIT 0x00006000 /* Inhibit update of Connection tab */
#define SAR_GP_PHY_RESET 0x00000008 /* PHY Reset */
#define SAR_GP_EESCLK 0x00000004 /* EEPROM SCLK */
#define SAR_GP_EECS 0x00000002 /* EEPROM Chip Select */
#define SAR_GP_EEDO 0x00000001 /* EEPROM Data Out */
/*****************************************************************************/
/* */
/* SAR local SRAM layout for 128k work SRAM */
/* */
/*****************************************************************************/
#define SAR_SRAM_SCD_SIZE 12
#define SAR_SRAM_TCT_SIZE 8
#define SAR_SRAM_RCT_SIZE 4
#define SAR_SRAM_TCT_128_BASE 0x00000
#define SAR_SRAM_TCT_128_TOP 0x01fff
#define SAR_SRAM_RCT_128_BASE 0x02000
#define SAR_SRAM_RCT_128_TOP 0x02fff
#define SAR_SRAM_FB0_128_BASE 0x03000
#define SAR_SRAM_FB0_128_TOP 0x033ff
#define SAR_SRAM_FB1_128_BASE 0x03400
#define SAR_SRAM_FB1_128_TOP 0x037ff
#define SAR_SRAM_FB2_128_BASE 0x03800
#define SAR_SRAM_FB2_128_TOP 0x03bff
#define SAR_SRAM_FB3_128_BASE 0x03c00
#define SAR_SRAM_FB3_128_TOP 0x03fff
#define SAR_SRAM_SCD_128_BASE 0x04000
#define SAR_SRAM_SCD_128_TOP 0x07fff
#define SAR_SRAM_TST1_128_BASE 0x08000
#define SAR_SRAM_TST1_128_TOP 0x0bfff
#define SAR_SRAM_TST2_128_BASE 0x0c000
#define SAR_SRAM_TST2_128_TOP 0x0ffff
#define SAR_SRAM_ABRSTD_128_BASE 0x10000
#define SAR_SRAM_ABRSTD_128_TOP 0x13fff
#define SAR_SRAM_RT_128_BASE 0x14000
#define SAR_SRAM_RT_128_TOP 0x15fff
#define SAR_SRAM_FIFO_128_BASE 0x18000
#define SAR_SRAM_FIFO_128_TOP 0x1ffff
/*****************************************************************************/
/* */
/* SAR local SRAM layout for 32k work SRAM */
/* */
/*****************************************************************************/
#define SAR_SRAM_TCT_32_BASE 0x00000
#define SAR_SRAM_TCT_32_TOP 0x00fff
#define SAR_SRAM_RCT_32_BASE 0x01000
#define SAR_SRAM_RCT_32_TOP 0x017ff
#define SAR_SRAM_FB0_32_BASE 0x01800
#define SAR_SRAM_FB0_32_TOP 0x01bff
#define SAR_SRAM_FB1_32_BASE 0x01c00
#define SAR_SRAM_FB1_32_TOP 0x01fff
#define SAR_SRAM_FB2_32_BASE 0x02000
#define SAR_SRAM_FB2_32_TOP 0x023ff
#define SAR_SRAM_FB3_32_BASE 0x02400
#define SAR_SRAM_FB3_32_TOP 0x027ff
#define SAR_SRAM_SCD_32_BASE 0x02800
#define SAR_SRAM_SCD_32_TOP 0x03fff
#define SAR_SRAM_TST1_32_BASE 0x04000
#define SAR_SRAM_TST1_32_TOP 0x04fff
#define SAR_SRAM_TST2_32_BASE 0x05000
#define SAR_SRAM_TST2_32_TOP 0x05fff
#define SAR_SRAM_ABRSTD_32_BASE 0x06000
#define SAR_SRAM_ABRSTD_32_TOP 0x067ff
#define SAR_SRAM_RT_32_BASE 0x06800
#define SAR_SRAM_RT_32_TOP 0x06fff
#define SAR_SRAM_FIFO_32_BASE 0x07000
#define SAR_SRAM_FIFO_32_TOP 0x07fff
/*****************************************************************************/
/* */
/* TSR - Transmit Status Request */
/* */
/*****************************************************************************/
#define SAR_TSR_TYPE_TSR 0x80000000
#define SAR_TSR_TYPE_TBD 0x00000000
#define SAR_TSR_TSIF 0x20000000
#define SAR_TSR_TAG_MASK 0x01F00000
/*****************************************************************************/
/* */
/* TBD - Transmit Buffer Descriptor */
/* */
/*****************************************************************************/
#define SAR_TBD_EPDU 0x40000000
#define SAR_TBD_TSIF 0x20000000
#define SAR_TBD_OAM 0x10000000
#define SAR_TBD_AAL0 0x00000000
#define SAR_TBD_AAL34 0x04000000
#define SAR_TBD_AAL5 0x08000000
#define SAR_TBD_GTSI 0x02000000
#define SAR_TBD_TAG_MASK 0x01F00000
#define SAR_TBD_VPI_MASK 0x0FF00000
#define SAR_TBD_VCI_MASK 0x000FFFF0
#define SAR_TBD_VC_MASK (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK)
#define SAR_TBD_VPI_SHIFT 20
#define SAR_TBD_VCI_SHIFT 4
/*****************************************************************************/
/* */
/* RXFD - Receive FIFO Descriptor */
/* */
/*****************************************************************************/
#define SAR_RXFD_SIZE_MASK 0x0F000000
#define SAR_RXFD_SIZE_512 0x00000000 /* 512 words */
#define SAR_RXFD_SIZE_1K 0x01000000 /* 1k words */
#define SAR_RXFD_SIZE_2K 0x02000000 /* 2k words */
#define SAR_RXFD_SIZE_4K 0x03000000 /* 4k words */
#define SAR_RXFD_SIZE_8K 0x04000000 /* 8k words */
#define SAR_RXFD_SIZE_16K 0x05000000 /* 16k words */
#define SAR_RXFD_SIZE_32K 0x06000000 /* 32k words */
#define SAR_RXFD_SIZE_64K 0x07000000 /* 64k words */
#define SAR_RXFD_SIZE_128K 0x08000000 /* 128k words */
#define SAR_RXFD_SIZE_256K 0x09000000 /* 256k words */
#define SAR_RXFD_ADDR_MASK 0x001ffc00
/*****************************************************************************/
/* */
/* ABRSTD - ABR + VBR Schedule Tables */
/* */
/*****************************************************************************/
#define SAR_ABRSTD_SIZE_MASK 0x07000000
#define SAR_ABRSTD_SIZE_512 0x00000000 /* 512 words */
#define SAR_ABRSTD_SIZE_1K 0x01000000 /* 1k words */
#define SAR_ABRSTD_SIZE_2K 0x02000000 /* 2k words */
#define SAR_ABRSTD_SIZE_4K 0x03000000 /* 4k words */
#define SAR_ABRSTD_SIZE_8K 0x04000000 /* 8k words */
#define SAR_ABRSTD_SIZE_16K 0x05000000 /* 16k words */
#define SAR_ABRSTD_ADDR_MASK 0x001ffc00
/*****************************************************************************/
/* */
/* RCTE - Receive Connection Table Entry */
/* */
/*****************************************************************************/
#define SAR_RCTE_IL_MASK 0xE0000000 /* inactivity limit */
#define SAR_RCTE_IC_MASK 0x1C000000 /* inactivity count */
#define SAR_RCTE_RSVD 0x02000000 /* reserved */
#define SAR_RCTE_LCD 0x01000000 /* last cell data */
#define SAR_RCTE_CI_VC 0x00800000 /* EFCI in previous cell of VC */
#define SAR_RCTE_FBP_01 0x00000000 /* 1. cell->FBQ0, others->FBQ1 */
#define SAR_RCTE_FBP_1 0x00200000 /* use FBQ 1 for all cells */
#define SAR_RCTE_FBP_2 0x00400000 /* use FBQ 2 for all cells */
#define SAR_RCTE_FBP_3 0x00600000 /* use FBQ 3 for all cells */
#define SAR_RCTE_NZ_GFC 0x00100000 /* non zero GFC in all cell of VC */
#define SAR_RCTE_CONNECTOPEN 0x00080000 /* VC is open */
#define SAR_RCTE_AAL_MASK 0x00070000 /* mask for AAL type field s.b. */
#define SAR_RCTE_RAWCELLINTEN 0x00008000 /* raw cell interrupt enable */
#define SAR_RCTE_RXCONCELLADDR 0x00004000 /* RX constant cell address */
#define SAR_RCTE_BUFFSTAT_MASK 0x00003000 /* buffer status */
#define SAR_RCTE_EFCI 0x00000800 /* EFCI Congestion flag */
#define SAR_RCTE_CLP 0x00000400 /* Cell Loss Priority flag */
#define SAR_RCTE_CRC 0x00000200 /* Received CRC Error */
#define SAR_RCTE_CELLCNT_MASK 0x000001FF /* cell Count */
#define SAR_RCTE_AAL0 0x00000000 /* AAL types for ALL field */
#define SAR_RCTE_AAL34 0x00010000
#define SAR_RCTE_AAL5 0x00020000
#define SAR_RCTE_RCQ 0x00030000
#define SAR_RCTE_OAM 0x00040000
#define TCMDQ_START 0x01000000
#define TCMDQ_LACR 0x02000000
#define TCMDQ_START_LACR 0x03000000
#define TCMDQ_INIT_ER 0x04000000
#define TCMDQ_HALT 0x05000000
struct idt77252_skb_prv {
struct scqe tbd; /* Transmit Buffer Descriptor */
dma_addr_t paddr; /* DMA handle */
u32 pool; /* sb_pool handle */
} __packed;
#define IDT77252_PRV_TBD(skb) \
(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)
#define IDT77252_PRV_PADDR(skb) \
(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)
#define IDT77252_PRV_POOL(skb) \
(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)
/*****************************************************************************/
/* */
/* PCI related items */
/* */
/*****************************************************************************/
#ifndef PCI_VENDOR_ID_IDT
#define PCI_VENDOR_ID_IDT 0x111D
#endif /* PCI_VENDOR_ID_IDT */
#ifndef PCI_DEVICE_ID_IDT_IDT77252
#define PCI_DEVICE_ID_IDT_IDT77252 0x0003
#endif /* PCI_DEVICE_ID_IDT_IDT772052 */
#endif /* !(_IDT77252_H) */

781
drivers/atm/idt77252_tables.h
View File

@ -1,781 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Do not edit, automatically generated by `./genrtbl'.
*
* Cell Line Rate: 353207.55 (155520000 bps)
*/
static unsigned int log_to_rate[] =
{
/* 000 */ 0x8d022e27, /* cps = 10.02, nrm = 3, interval = 35264.00 */
/* 001 */ 0x8d362e11, /* cps = 10.42, nrm = 3, interval = 33856.00 */
/* 002 */ 0x8d6e2bf8, /* cps = 10.86, nrm = 3, interval = 32512.00 */
/* 003 */ 0x8da82bcf, /* cps = 11.31, nrm = 3, interval = 31200.00 */
/* 004 */ 0x8de42ba8, /* cps = 11.78, nrm = 3, interval = 29952.00 */
/* 005 */ 0x8e242b82, /* cps = 12.28, nrm = 3, interval = 28736.00 */
/* 006 */ 0x8e662b5e, /* cps = 12.80, nrm = 3, interval = 27584.00 */
/* 007 */ 0x8eaa2b3c, /* cps = 13.33, nrm = 3, interval = 26496.00 */
/* 008 */ 0x8ef22b1a, /* cps = 13.89, nrm = 3, interval = 25408.00 */
/* 009 */ 0x8f3e2afa, /* cps = 14.48, nrm = 3, interval = 24384.00 */
/* 010 */ 0x8f8a2adc, /* cps = 15.08, nrm = 3, interval = 23424.00 */
/* 011 */ 0x8fdc2abe, /* cps = 15.72, nrm = 3, interval = 22464.00 */
/* 012 */ 0x90182aa2, /* cps = 16.38, nrm = 3, interval = 21568.00 */
/* 013 */ 0x90422a87, /* cps = 17.03, nrm = 3, interval = 20704.00 */
/* 014 */ 0x90702a6d, /* cps = 17.75, nrm = 3, interval = 19872.00 */
/* 015 */ 0x90a02a54, /* cps = 18.50, nrm = 3, interval = 19072.00 */
/* 016 */ 0x90d22a3c, /* cps = 19.28, nrm = 3, interval = 18304.00 */
/* 017 */ 0x91062a25, /* cps = 20.09, nrm = 3, interval = 17568.00 */
/* 018 */ 0x913c2a0f, /* cps = 20.94, nrm = 3, interval = 16864.00 */
/* 019 */ 0x917427f3, /* cps = 21.81, nrm = 3, interval = 16176.00 */
/* 020 */ 0x91b027ca, /* cps = 22.75, nrm = 3, interval = 15520.00 */
/* 021 */ 0x91ec27a3, /* cps = 23.69, nrm = 3, interval = 14896.00 */
/* 022 */ 0x922c277e, /* cps = 24.69, nrm = 3, interval = 14304.00 */
/* 023 */ 0x926e275a, /* cps = 25.72, nrm = 3, interval = 13728.00 */
/* 024 */ 0x92b42737, /* cps = 26.81, nrm = 3, interval = 13168.00 */
/* 025 */ 0x92fc2716, /* cps = 27.94, nrm = 3, interval = 12640.00 */
/* 026 */ 0x934626f6, /* cps = 29.09, nrm = 3, interval = 12128.00 */
/* 027 */ 0x939426d8, /* cps = 30.31, nrm = 3, interval = 11648.00 */
/* 028 */ 0x93e426bb, /* cps = 31.56, nrm = 3, interval = 11184.00 */
/* 029 */ 0x941e269e, /* cps = 32.94, nrm = 3, interval = 10720.00 */
/* 030 */ 0x944a2683, /* cps = 34.31, nrm = 3, interval = 10288.00 */
/* 031 */ 0x9476266a, /* cps = 35.69, nrm = 3, interval = 9888.00 */
/* 032 */ 0x94a62651, /* cps = 37.19, nrm = 3, interval = 9488.00 */
/* 033 */ 0x94d82639, /* cps = 38.75, nrm = 3, interval = 9104.00 */
/* 034 */ 0x950c6622, /* cps = 40.38, nrm = 4, interval = 8736.00 */
/* 035 */ 0x9544660c, /* cps = 42.12, nrm = 4, interval = 8384.00 */
/* 036 */ 0x957c63ee, /* cps = 43.88, nrm = 4, interval = 8048.00 */
/* 037 */ 0x95b663c6, /* cps = 45.69, nrm = 4, interval = 7728.00 */
/* 038 */ 0x95f4639f, /* cps = 47.62, nrm = 4, interval = 7416.00 */
/* 039 */ 0x96346379, /* cps = 49.62, nrm = 4, interval = 7112.00 */
/* 040 */ 0x96766356, /* cps = 51.69, nrm = 4, interval = 6832.00 */
/* 041 */ 0x96bc6333, /* cps = 53.88, nrm = 4, interval = 6552.00 */
/* 042 */ 0x97046312, /* cps = 56.12, nrm = 4, interval = 6288.00 */
/* 043 */ 0x974e62f3, /* cps = 58.44, nrm = 4, interval = 6040.00 */
/* 044 */ 0x979e62d4, /* cps = 60.94, nrm = 4, interval = 5792.00 */
/* 045 */ 0x97f062b7, /* cps = 63.50, nrm = 4, interval = 5560.00 */
/* 046 */ 0x9822629b, /* cps = 66.12, nrm = 4, interval = 5336.00 */
/* 047 */ 0x984e6280, /* cps = 68.88, nrm = 4, interval = 5120.00 */
/* 048 */ 0x987e6266, /* cps = 71.88, nrm = 4, interval = 4912.00 */
/* 049 */ 0x98ac624e, /* cps = 74.75, nrm = 4, interval = 4720.00 */
/* 050 */ 0x98e06236, /* cps = 78.00, nrm = 4, interval = 4528.00 */
/* 051 */ 0x9914a21f, /* cps = 81.25, nrm = 8, interval = 4344.00 */
/* 052 */ 0x994aa209, /* cps = 84.62, nrm = 8, interval = 4168.00 */
/* 053 */ 0x99829fe9, /* cps = 88.12, nrm = 8, interval = 4004.00 */
/* 054 */ 0x99be9fc1, /* cps = 91.88, nrm = 8, interval = 3844.00 */
/* 055 */ 0x99fc9f9a, /* cps = 95.75, nrm = 8, interval = 3688.00 */
/* 056 */ 0x9a3c9f75, /* cps = 99.75, nrm = 8, interval = 3540.00 */
/* 057 */ 0x9a809f51, /* cps = 104.00, nrm = 8, interval = 3396.00 */
/* 058 */ 0x9ac49f2f, /* cps = 108.25, nrm = 8, interval = 3260.00 */
/* 059 */ 0x9b0e9f0e, /* cps = 112.88, nrm = 8, interval = 3128.00 */
/* 060 */ 0x9b589eef, /* cps = 117.50, nrm = 8, interval = 3004.00 */
/* 061 */ 0x9ba69ed1, /* cps = 122.38, nrm = 8, interval = 2884.00 */
/* 062 */ 0x9bf89eb4, /* cps = 127.50, nrm = 8, interval = 2768.00 */
/* 063 */ 0x9c269e98, /* cps = 132.75, nrm = 8, interval = 2656.00 */
/* 064 */ 0x9c549e7d, /* cps = 138.50, nrm = 8, interval = 2548.00 */
/* 065 */ 0x9c849e63, /* cps = 144.50, nrm = 8, interval = 2444.00 */
/* 066 */ 0x9cb29e4b, /* cps = 150.25, nrm = 8, interval = 2348.00 */
/* 067 */ 0x9ce69e33, /* cps = 156.75, nrm = 8, interval = 2252.00 */
/* 068 */ 0x9d1cde1c, /* cps = 163.50, nrm = 16, interval = 2160.00 */
/* 069 */ 0x9d50de07, /* cps = 170.00, nrm = 16, interval = 2076.00 */
/* 070 */ 0x9d8adbe4, /* cps = 177.25, nrm = 16, interval = 1992.00 */
/* 071 */ 0x9dc4dbbc, /* cps = 184.50, nrm = 16, interval = 1912.00 */
/* 072 */ 0x9e02db96, /* cps = 192.25, nrm = 16, interval = 1836.00 */
/* 073 */ 0x9e42db71, /* cps = 200.25, nrm = 16, interval = 1762.00 */
/* 074 */ 0x9e86db4d, /* cps = 208.75, nrm = 16, interval = 1690.00 */
/* 075 */ 0x9ecedb2b, /* cps = 217.75, nrm = 16, interval = 1622.00 */
/* 076 */ 0x9f16db0a, /* cps = 226.75, nrm = 16, interval = 1556.00 */
/* 077 */ 0x9f62daeb, /* cps = 236.25, nrm = 16, interval = 1494.00 */
/* 078 */ 0x9fb2dacd, /* cps = 246.25, nrm = 16, interval = 1434.00 */
/* 079 */ 0xa002dab0, /* cps = 256.50, nrm = 16, interval = 1376.00 */
/* 080 */ 0xa02eda94, /* cps = 267.50, nrm = 16, interval = 1320.00 */
/* 081 */ 0xa05ada7a, /* cps = 278.50, nrm = 16, interval = 1268.00 */
/* 082 */ 0xa088da60, /* cps = 290.00, nrm = 16, interval = 1216.00 */
/* 083 */ 0xa0b8da48, /* cps = 302.00, nrm = 16, interval = 1168.00 */
/* 084 */ 0xa0ecda30, /* cps = 315.00, nrm = 16, interval = 1120.00 */
/* 085 */ 0xa1211a1a, /* cps = 328.00, nrm = 32, interval = 1076.00 */
/* 086 */ 0xa1591a04, /* cps = 342.00, nrm = 32, interval = 1032.00 */
/* 087 */ 0xa19117df, /* cps = 356.00, nrm = 32, interval = 991.00 */
/* 088 */ 0xa1cd17b7, /* cps = 371.00, nrm = 32, interval = 951.00 */
/* 089 */ 0xa20b1791, /* cps = 386.50, nrm = 32, interval = 913.00 */
/* 090 */ 0xa24d176c, /* cps = 403.00, nrm = 32, interval = 876.00 */
/* 091 */ 0xa28f1749, /* cps = 419.50, nrm = 32, interval = 841.00 */
/* 092 */ 0xa2d71727, /* cps = 437.50, nrm = 32, interval = 807.00 */
/* 093 */ 0xa31f1707, /* cps = 455.50, nrm = 32, interval = 775.00 */
/* 094 */ 0xa36d16e7, /* cps = 475.00, nrm = 32, interval = 743.00 */
/* 095 */ 0xa3bd16c9, /* cps = 495.00, nrm = 32, interval = 713.00 */
/* 096 */ 0xa40716ad, /* cps = 515.00, nrm = 32, interval = 685.00 */
/* 097 */ 0xa4331691, /* cps = 537.00, nrm = 32, interval = 657.00 */
/* 098 */ 0xa45f1677, /* cps = 559.00, nrm = 32, interval = 631.00 */
/* 099 */ 0xa48f165d, /* cps = 583.00, nrm = 32, interval = 605.00 */
/* 100 */ 0xa4bf1645, /* cps = 607.00, nrm = 32, interval = 581.00 */
/* 101 */ 0xa4f1162e, /* cps = 632.00, nrm = 32, interval = 558.00 */
/* 102 */ 0xa5291617, /* cps = 660.00, nrm = 32, interval = 535.00 */
/* 103 */ 0xa55f1602, /* cps = 687.00, nrm = 32, interval = 514.00 */
/* 104 */ 0xa59913da, /* cps = 716.00, nrm = 32, interval = 493.00 */
/* 105 */ 0xa5d513b2, /* cps = 746.00, nrm = 32, interval = 473.00 */
/* 106 */ 0xa613138c, /* cps = 777.00, nrm = 32, interval = 454.00 */
/* 107 */ 0xa6551368, /* cps = 810.00, nrm = 32, interval = 436.00 */
/* 108 */ 0xa6971345, /* cps = 843.00, nrm = 32, interval = 418.50 */
/* 109 */ 0xa6df1323, /* cps = 879.00, nrm = 32, interval = 401.50 */
/* 110 */ 0xa7291303, /* cps = 916.00, nrm = 32, interval = 385.50 */
/* 111 */ 0xa77512e4, /* cps = 954.00, nrm = 32, interval = 370.00 */
/* 112 */ 0xa7c512c6, /* cps = 994.00, nrm = 32, interval = 355.00 */
/* 113 */ 0xa80d12a9, /* cps = 1036.00, nrm = 32, interval = 340.50 */
/* 114 */ 0xa839128e, /* cps = 1080.00, nrm = 32, interval = 327.00 */
/* 115 */ 0xa8651274, /* cps = 1124.00, nrm = 32, interval = 314.00 */
/* 116 */ 0xa895125a, /* cps = 1172.00, nrm = 32, interval = 301.00 */
/* 117 */ 0xa8c71242, /* cps = 1222.00, nrm = 32, interval = 289.00 */
/* 118 */ 0xa8f9122b, /* cps = 1272.00, nrm = 32, interval = 277.50 */
/* 119 */ 0xa92f1214, /* cps = 1326.00, nrm = 32, interval = 266.00 */
/* 120 */ 0xa9670ffe, /* cps = 1382.00, nrm = 32, interval = 255.50 */
/* 121 */ 0xa9a10fd5, /* cps = 1440.00, nrm = 32, interval = 245.25 */
/* 122 */ 0xa9db0fae, /* cps = 1498.00, nrm = 32, interval = 235.50 */
/* 123 */ 0xaa1b0f88, /* cps = 1562.00, nrm = 32, interval = 226.00 */
/* 124 */ 0xaa5d0f63, /* cps = 1628.00, nrm = 32, interval = 216.75 */
/* 125 */ 0xaaa10f41, /* cps = 1696.00, nrm = 32, interval = 208.25 */
/* 126 */ 0xaae90f1f, /* cps = 1768.00, nrm = 32, interval = 199.75 */
/* 127 */ 0xab330eff, /* cps = 1842.00, nrm = 32, interval = 191.75 */
/* 128 */ 0xab7f0ee0, /* cps = 1918.00, nrm = 32, interval = 184.00 */
/* 129 */ 0xabd10ec2, /* cps = 2000.00, nrm = 32, interval = 176.50 */
/* 130 */ 0xac110ea6, /* cps = 2080.00, nrm = 32, interval = 169.50 */
/* 131 */ 0xac3d0e8b, /* cps = 2168.00, nrm = 32, interval = 162.75 */
/* 132 */ 0xac6d0e70, /* cps = 2264.00, nrm = 32, interval = 156.00 */
/* 133 */ 0xac9b0e57, /* cps = 2356.00, nrm = 32, interval = 149.75 */
/* 134 */ 0xaccd0e3f, /* cps = 2456.00, nrm = 32, interval = 143.75 */
/* 135 */ 0xacff0e28, /* cps = 2556.00, nrm = 32, interval = 138.00 */
/* 136 */ 0xad350e12, /* cps = 2664.00, nrm = 32, interval = 132.50 */
/* 137 */ 0xad6d0bf9, /* cps = 2776.00, nrm = 32, interval = 127.12 */
/* 138 */ 0xada70bd0, /* cps = 2892.00, nrm = 32, interval = 122.00 */
/* 139 */ 0xade30ba9, /* cps = 3012.00, nrm = 32, interval = 117.12 */
/* 140 */ 0xae230b83, /* cps = 3140.00, nrm = 32, interval = 112.38 */
/* 141 */ 0xae650b5f, /* cps = 3272.00, nrm = 32, interval = 107.88 */
/* 142 */ 0xaeab0b3c, /* cps = 3412.00, nrm = 32, interval = 103.50 */
/* 143 */ 0xaef10b1b, /* cps = 3552.00, nrm = 32, interval = 99.38 */
/* 144 */ 0xaf3b0afb, /* cps = 3700.00, nrm = 32, interval = 95.38 */
/* 145 */ 0xaf8b0adc, /* cps = 3860.00, nrm = 32, interval = 91.50 */
/* 146 */ 0xafd90abf, /* cps = 4016.00, nrm = 32, interval = 87.88 */
/* 147 */ 0xb0170aa3, /* cps = 4184.00, nrm = 32, interval = 84.38 */
/* 148 */ 0xb0430a87, /* cps = 4360.00, nrm = 32, interval = 80.88 */
/* 149 */ 0xb0710a6d, /* cps = 4544.00, nrm = 32, interval = 77.62 */
/* 150 */ 0xb0a10a54, /* cps = 4736.00, nrm = 32, interval = 74.50 */
/* 151 */ 0xb0d30a3c, /* cps = 4936.00, nrm = 32, interval = 71.50 */
/* 152 */ 0xb1070a25, /* cps = 5144.00, nrm = 32, interval = 68.62 */
/* 153 */ 0xb13d0a0f, /* cps = 5360.00, nrm = 32, interval = 65.88 */
/* 154 */ 0xb17507f4, /* cps = 5584.00, nrm = 32, interval = 63.25 */
/* 155 */ 0xb1af07cb, /* cps = 5816.00, nrm = 32, interval = 60.69 */
/* 156 */ 0xb1eb07a4, /* cps = 6056.00, nrm = 32, interval = 58.25 */
/* 157 */ 0xb22b077f, /* cps = 6312.00, nrm = 32, interval = 55.94 */
/* 158 */ 0xb26d075b, /* cps = 6576.00, nrm = 32, interval = 53.69 */
/* 159 */ 0xb2b30738, /* cps = 6856.00, nrm = 32, interval = 51.50 */
/* 160 */ 0xb2fb0717, /* cps = 7144.00, nrm = 32, interval = 49.44 */
/* 161 */ 0xb34506f7, /* cps = 7440.00, nrm = 32, interval = 47.44 */
/* 162 */ 0xb39306d9, /* cps = 7752.00, nrm = 32, interval = 45.56 */
/* 163 */ 0xb3e506bb, /* cps = 8080.00, nrm = 32, interval = 43.69 */
/* 164 */ 0xb41d069f, /* cps = 8416.00, nrm = 32, interval = 41.94 */
/* 165 */ 0xb4490684, /* cps = 8768.00, nrm = 32, interval = 40.25 */
/* 166 */ 0xb477066a, /* cps = 9136.00, nrm = 32, interval = 38.62 */
/* 167 */ 0xb4a70651, /* cps = 9520.00, nrm = 32, interval = 37.06 */
/* 168 */ 0xb4d90639, /* cps = 9920.00, nrm = 32, interval = 35.56 */
/* 169 */ 0xb50d0622, /* cps = 10336.00, nrm = 32, interval = 34.12 */
/* 170 */ 0xb545060c, /* cps = 10784.00, nrm = 32, interval = 32.75 */
/* 171 */ 0xb57b03ef, /* cps = 11216.00, nrm = 32, interval = 31.47 */
/* 172 */ 0xb5b503c7, /* cps = 11680.00, nrm = 32, interval = 30.22 */
/* 173 */ 0xb5f303a0, /* cps = 12176.00, nrm = 32, interval = 29.00 */
/* 174 */ 0xb633037a, /* cps = 12688.00, nrm = 32, interval = 27.81 */
/* 175 */ 0xb6750357, /* cps = 13216.00, nrm = 32, interval = 26.72 */
/* 176 */ 0xb6bb0334, /* cps = 13776.00, nrm = 32, interval = 25.62 */
/* 177 */ 0xb7030313, /* cps = 14352.00, nrm = 32, interval = 24.59 */
/* 178 */ 0xb74f02f3, /* cps = 14960.00, nrm = 32, interval = 23.59 */
/* 179 */ 0xb79d02d5, /* cps = 15584.00, nrm = 32, interval = 22.66 */
/* 180 */ 0xb7ed02b8, /* cps = 16224.00, nrm = 32, interval = 21.75 */
/* 181 */ 0xb821029c, /* cps = 16896.00, nrm = 32, interval = 20.88 */
/* 182 */ 0xb84f0281, /* cps = 17632.00, nrm = 32, interval = 20.03 */
/* 183 */ 0xb87d0267, /* cps = 18368.00, nrm = 32, interval = 19.22 */
/* 184 */ 0xb8ad024e, /* cps = 19136.00, nrm = 32, interval = 18.44 */
/* 185 */ 0xb8dd0237, /* cps = 19904.00, nrm = 32, interval = 17.72 */
/* 186 */ 0xb9130220, /* cps = 20768.00, nrm = 32, interval = 17.00 */
/* 187 */ 0xb949020a, /* cps = 21632.00, nrm = 32, interval = 16.31 */
/* 188 */ 0xb98301f5, /* cps = 22560.00, nrm = 32, interval = 15.66 */
/* 189 */ 0xb9bd01e1, /* cps = 23488.00, nrm = 32, interval = 15.03 */
/* 190 */ 0xb9fd01cd, /* cps = 24512.00, nrm = 32, interval = 14.41 */
/* 191 */ 0xba3b01bb, /* cps = 25504.00, nrm = 32, interval = 13.84 */
/* 192 */ 0xba7f01a9, /* cps = 26592.00, nrm = 32, interval = 13.28 */
/* 193 */ 0xbac30198, /* cps = 27680.00, nrm = 32, interval = 12.75 */
/* 194 */ 0xbb0f0187, /* cps = 28896.00, nrm = 32, interval = 12.22 */
/* 195 */ 0xbb570178, /* cps = 30048.00, nrm = 32, interval = 11.75 */
/* 196 */ 0xbbab0168, /* cps = 31392.00, nrm = 32, interval = 11.25 */
/* 197 */ 0xbbf9015a, /* cps = 32640.00, nrm = 32, interval = 10.81 */
/* 198 */ 0xbc27014c, /* cps = 33984.00, nrm = 32, interval = 10.38 */
/* 199 */ 0xbc53013f, /* cps = 35392.00, nrm = 32, interval = 9.97 */
/* 200 */ 0xbc830132, /* cps = 36928.00, nrm = 32, interval = 9.56 */
/* 201 */ 0xbcb50125, /* cps = 38528.00, nrm = 32, interval = 9.16 */
/* 202 */ 0xbce5011a, /* cps = 40064.00, nrm = 32, interval = 8.81 */
/* 203 */ 0xbd1d010e, /* cps = 41856.00, nrm = 32, interval = 8.44 */
/* 204 */ 0xbd530103, /* cps = 43584.00, nrm = 32, interval = 8.09 */
/* 205 */ 0xbd8b00f9, /* cps = 45376.00, nrm = 32, interval = 7.78 */
/* 206 */ 0xbdc500ef, /* cps = 47232.00, nrm = 32, interval = 7.47 */
/* 207 */ 0xbe0700e5, /* cps = 49344.00, nrm = 32, interval = 7.16 */
/* 208 */ 0xbe4500dc, /* cps = 51328.00, nrm = 32, interval = 6.88 */
/* 209 */ 0xbe8900d3, /* cps = 53504.00, nrm = 32, interval = 6.59 */
/* 210 */ 0xbecb00cb, /* cps = 55616.00, nrm = 32, interval = 6.34 */
/* 211 */ 0xbf1d00c2, /* cps = 58240.00, nrm = 32, interval = 6.06 */
/* 212 */ 0xbf6100bb, /* cps = 60416.00, nrm = 32, interval = 5.84 */
/* 213 */ 0xbfb500b3, /* cps = 63104.00, nrm = 32, interval = 5.59 */
/* 214 */ 0xc00300ac, /* cps = 65664.00, nrm = 32, interval = 5.38 */
/* 215 */ 0xc02f00a5, /* cps = 68480.00, nrm = 32, interval = 5.16 */
/* 216 */ 0xc05d009e, /* cps = 71424.00, nrm = 32, interval = 4.94 */
/* 217 */ 0xc0890098, /* cps = 74240.00, nrm = 32, interval = 4.75 */
/* 218 */ 0xc0b90092, /* cps = 77312.00, nrm = 32, interval = 4.56 */
/* 219 */ 0xc0ed008c, /* cps = 80640.00, nrm = 32, interval = 4.38 */
/* 220 */ 0xc1250086, /* cps = 84224.00, nrm = 32, interval = 4.19 */
/* 221 */ 0xc1590081, /* cps = 87552.00, nrm = 32, interval = 4.03 */
/* 222 */ 0xc191007c, /* cps = 91136.00, nrm = 32, interval = 3.88 */
/* 223 */ 0xc1cd0077, /* cps = 94976.00, nrm = 32, interval = 3.72 */
/* 224 */ 0xc20d0072, /* cps = 99072.00, nrm = 32, interval = 3.56 */
/* 225 */ 0xc255006d, /* cps = 103680.00, nrm = 32, interval = 3.41 */
/* 226 */ 0xc2910069, /* cps = 107520.00, nrm = 32, interval = 3.28 */
/* 227 */ 0xc2d50065, /* cps = 111872.00, nrm = 32, interval = 3.16 */
/* 228 */ 0xc32f0060, /* cps = 117632.00, nrm = 32, interval = 3.00 */
/* 229 */ 0xc36b005d, /* cps = 121472.00, nrm = 32, interval = 2.91 */
/* 230 */ 0xc3c10059, /* cps = 126976.00, nrm = 32, interval = 2.78 */
/* 231 */ 0xc40f0055, /* cps = 132864.00, nrm = 32, interval = 2.66 */
/* 232 */ 0xc4350052, /* cps = 137728.00, nrm = 32, interval = 2.56 */
/* 233 */ 0xc46d004e, /* cps = 144896.00, nrm = 32, interval = 2.44 */
/* 234 */ 0xc499004b, /* cps = 150528.00, nrm = 32, interval = 2.34 */
/* 235 */ 0xc4cb0048, /* cps = 156928.00, nrm = 32, interval = 2.25 */
/* 236 */ 0xc4ff0045, /* cps = 163584.00, nrm = 32, interval = 2.16 */
/* 237 */ 0xc5250043, /* cps = 168448.00, nrm = 32, interval = 2.09 */
/* 238 */ 0xc5630040, /* cps = 176384.00, nrm = 32, interval = 2.00 */
/* 239 */ 0xc5a7003d, /* cps = 185088.00, nrm = 32, interval = 1.91 */
/* 240 */ 0xc5d9003b, /* cps = 191488.00, nrm = 32, interval = 1.84 */
/* 241 */ 0xc6290038, /* cps = 201728.00, nrm = 32, interval = 1.75 */
/* 242 */ 0xc6630036, /* cps = 209152.00, nrm = 32, interval = 1.69 */
/* 243 */ 0xc6a30034, /* cps = 217344.00, nrm = 32, interval = 1.62 */
/* 244 */ 0xc6e70032, /* cps = 226048.00, nrm = 32, interval = 1.56 */
/* 245 */ 0xc72f0030, /* cps = 235264.00, nrm = 32, interval = 1.50 */
/* 246 */ 0xc77f002e, /* cps = 245504.00, nrm = 32, interval = 1.44 */
/* 247 */ 0xc7d7002c, /* cps = 256768.00, nrm = 32, interval = 1.38 */
/* 248 */ 0xc81b002a, /* cps = 268800.00, nrm = 32, interval = 1.31 */
/* 249 */ 0xc84f0028, /* cps = 282112.00, nrm = 32, interval = 1.25 */
/* 250 */ 0xc86d0027, /* cps = 289792.00, nrm = 32, interval = 1.22 */
/* 251 */ 0xc8a90025, /* cps = 305152.00, nrm = 32, interval = 1.16 */
/* 252 */ 0xc8cb0024, /* cps = 313856.00, nrm = 32, interval = 1.12 */
/* 253 */ 0xc9130022, /* cps = 332288.00, nrm = 32, interval = 1.06 */
/* 254 */ 0xc9390021, /* cps = 342016.00, nrm = 32, interval = 1.03 */
/* 255 */ 0xc9630020, /* cps = 352768.00, nrm = 32, interval = 1.00 */
};
static unsigned char rate_to_log[] =
{
/* 1.00 => 0 */ 0x00, /* => 10.02 */
/* 1.06 => 0 */ 0x00, /* => 10.02 */
/* 1.12 => 0 */ 0x00, /* => 10.02 */
/* 1.19 => 0 */ 0x00, /* => 10.02 */
/* 1.25 => 0 */ 0x00, /* => 10.02 */
/* 1.31 => 0 */ 0x00, /* => 10.02 */
/* 1.38 => 0 */ 0x00, /* => 10.02 */
/* 1.44 => 0 */ 0x00, /* => 10.02 */
/* 1.50 => 0 */ 0x00, /* => 10.02 */
/* 1.56 => 0 */ 0x00, /* => 10.02 */
/* 1.62 => 0 */ 0x00, /* => 10.02 */
/* 1.69 => 0 */ 0x00, /* => 10.02 */
/* 1.75 => 0 */ 0x00, /* => 10.02 */
/* 1.81 => 0 */ 0x00, /* => 10.02 */
/* 1.88 => 0 */ 0x00, /* => 10.02 */
/* 1.94 => 0 */ 0x00, /* => 10.02 */
/* 2.00 => 0 */ 0x00, /* => 10.02 */
/* 2.12 => 0 */ 0x00, /* => 10.02 */
/* 2.25 => 0 */ 0x00, /* => 10.02 */
/* 2.38 => 0 */ 0x00, /* => 10.02 */
/* 2.50 => 0 */ 0x00, /* => 10.02 */
/* 2.62 => 0 */ 0x00, /* => 10.02 */
/* 2.75 => 0 */ 0x00, /* => 10.02 */
/* 2.88 => 0 */ 0x00, /* => 10.02 */
/* 3.00 => 0 */ 0x00, /* => 10.02 */
/* 3.12 => 0 */ 0x00, /* => 10.02 */
/* 3.25 => 0 */ 0x00, /* => 10.02 */
/* 3.38 => 0 */ 0x00, /* => 10.02 */
/* 3.50 => 0 */ 0x00, /* => 10.02 */
/* 3.62 => 0 */ 0x00, /* => 10.02 */
/* 3.75 => 0 */ 0x00, /* => 10.02 */
/* 3.88 => 0 */ 0x00, /* => 10.02 */
/* 4.00 => 0 */ 0x00, /* => 10.02 */
/* 4.25 => 0 */ 0x00, /* => 10.02 */
/* 4.50 => 0 */ 0x00, /* => 10.02 */
/* 4.75 => 0 */ 0x00, /* => 10.02 */
/* 5.00 => 0 */ 0x00, /* => 10.02 */
/* 5.25 => 0 */ 0x00, /* => 10.02 */
/* 5.50 => 0 */ 0x00, /* => 10.02 */
/* 5.75 => 0 */ 0x00, /* => 10.02 */
/* 6.00 => 0 */ 0x00, /* => 10.02 */
/* 6.25 => 0 */ 0x00, /* => 10.02 */
/* 6.50 => 0 */ 0x00, /* => 10.02 */
/* 6.75 => 0 */ 0x00, /* => 10.02 */
/* 7.00 => 0 */ 0x00, /* => 10.02 */
/* 7.25 => 0 */ 0x00, /* => 10.02 */
/* 7.50 => 0 */ 0x00, /* => 10.02 */
/* 7.75 => 0 */ 0x00, /* => 10.02 */
/* 8.00 => 0 */ 0x00, /* => 10.02 */
/* 8.50 => 0 */ 0x00, /* => 10.02 */
/* 9.00 => 0 */ 0x00, /* => 10.02 */
/* 9.50 => 0 */ 0x00, /* => 10.02 */
/* 10.00 => 0 */ 0x00, /* => 10.02 */
/* 10.50 => 1 */ 0x01, /* => 10.42 */
/* 11.00 => 2 */ 0x02, /* => 10.86 */
/* 11.50 => 3 */ 0x03, /* => 11.31 */
/* 12.00 => 4 */ 0x04, /* => 11.78 */
/* 12.50 => 5 */ 0x05, /* => 12.28 */
/* 13.00 => 6 */ 0x06, /* => 12.80 */
/* 13.50 => 7 */ 0x07, /* => 13.33 */
/* 14.00 => 8 */ 0x08, /* => 13.89 */
/* 14.50 => 9 */ 0x09, /* => 14.48 */
/* 15.00 => 9 */ 0x09, /* => 14.48 */
/* 15.50 => 10 */ 0x0a, /* => 15.08 */
/* 16.00 => 11 */ 0x0b, /* => 15.72 */
/* 17.00 => 12 */ 0x0c, /* => 16.38 */
/* 18.00 => 14 */ 0x0e, /* => 17.75 */
/* 19.00 => 15 */ 0x0f, /* => 18.50 */
/* 20.00 => 16 */ 0x10, /* => 19.28 */
/* 21.00 => 18 */ 0x12, /* => 20.94 */
/* 22.00 => 19 */ 0x13, /* => 21.81 */
/* 23.00 => 20 */ 0x14, /* => 22.75 */
/* 24.00 => 21 */ 0x15, /* => 23.69 */
/* 25.00 => 22 */ 0x16, /* => 24.69 */
/* 26.00 => 23 */ 0x17, /* => 25.72 */
/* 27.00 => 24 */ 0x18, /* => 26.81 */
/* 28.00 => 25 */ 0x19, /* => 27.94 */
/* 29.00 => 25 */ 0x19, /* => 27.94 */
/* 30.00 => 26 */ 0x1a, /* => 29.09 */
/* 31.00 => 27 */ 0x1b, /* => 30.31 */
/* 32.00 => 28 */ 0x1c, /* => 31.56 */
/* 34.00 => 29 */ 0x1d, /* => 32.94 */
/* 36.00 => 31 */ 0x1f, /* => 35.69 */
/* 38.00 => 32 */ 0x20, /* => 37.19 */
/* 40.00 => 33 */ 0x21, /* => 38.75 */
/* 42.00 => 34 */ 0x22, /* => 40.38 */
/* 44.00 => 36 */ 0x24, /* => 43.88 */
/* 46.00 => 37 */ 0x25, /* => 45.69 */
/* 48.00 => 38 */ 0x26, /* => 47.62 */
/* 50.00 => 39 */ 0x27, /* => 49.62 */
/* 52.00 => 40 */ 0x28, /* => 51.69 */
/* 54.00 => 41 */ 0x29, /* => 53.88 */
/* 56.00 => 41 */ 0x29, /* => 53.88 */
/* 58.00 => 42 */ 0x2a, /* => 56.12 */
/* 60.00 => 43 */ 0x2b, /* => 58.44 */
/* 62.00 => 44 */ 0x2c, /* => 60.94 */
/* 64.00 => 45 */ 0x2d, /* => 63.50 */
/* 68.00 => 46 */ 0x2e, /* => 66.12 */
/* 72.00 => 48 */ 0x30, /* => 71.88 */
/* 76.00 => 49 */ 0x31, /* => 74.75 */
/* 80.00 => 50 */ 0x32, /* => 78.00 */
/* 84.00 => 51 */ 0x33, /* => 81.25 */
/* 88.00 => 52 */ 0x34, /* => 84.62 */
/* 92.00 => 54 */ 0x36, /* => 91.88 */
/* 96.00 => 55 */ 0x37, /* => 95.75 */
/* 100.00 => 56 */ 0x38, /* => 99.75 */
/* 104.00 => 56 */ 0x38, /* => 99.75 */
/* 108.00 => 57 */ 0x39, /* => 104.00 */
/* 112.00 => 58 */ 0x3a, /* => 108.25 */
/* 116.00 => 59 */ 0x3b, /* => 112.88 */
/* 120.00 => 60 */ 0x3c, /* => 117.50 */
/* 124.00 => 61 */ 0x3d, /* => 122.38 */
/* 128.00 => 62 */ 0x3e, /* => 127.50 */
/* 136.00 => 63 */ 0x3f, /* => 132.75 */
/* 144.00 => 64 */ 0x40, /* => 138.50 */
/* 152.00 => 66 */ 0x42, /* => 150.25 */
/* 160.00 => 67 */ 0x43, /* => 156.75 */
/* 168.00 => 68 */ 0x44, /* => 163.50 */
/* 176.00 => 69 */ 0x45, /* => 170.00 */
/* 184.00 => 70 */ 0x46, /* => 177.25 */
/* 192.00 => 71 */ 0x47, /* => 184.50 */
/* 200.00 => 72 */ 0x48, /* => 192.25 */
/* 208.00 => 73 */ 0x49, /* => 200.25 */
/* 216.00 => 74 */ 0x4a, /* => 208.75 */
/* 224.00 => 75 */ 0x4b, /* => 217.75 */
/* 232.00 => 76 */ 0x4c, /* => 226.75 */
/* 240.00 => 77 */ 0x4d, /* => 236.25 */
/* 248.00 => 78 */ 0x4e, /* => 246.25 */
/* 256.00 => 78 */ 0x4e, /* => 246.25 */
/* 272.00 => 80 */ 0x50, /* => 267.50 */
/* 288.00 => 81 */ 0x51, /* => 278.50 */
/* 304.00 => 83 */ 0x53, /* => 302.00 */
/* 320.00 => 84 */ 0x54, /* => 315.00 */
/* 336.00 => 85 */ 0x55, /* => 328.00 */
/* 352.00 => 86 */ 0x56, /* => 342.00 */
/* 368.00 => 87 */ 0x57, /* => 356.00 */
/* 384.00 => 88 */ 0x58, /* => 371.00 */
/* 400.00 => 89 */ 0x59, /* => 386.50 */
/* 416.00 => 90 */ 0x5a, /* => 403.00 */
/* 432.00 => 91 */ 0x5b, /* => 419.50 */
/* 448.00 => 92 */ 0x5c, /* => 437.50 */
/* 464.00 => 93 */ 0x5d, /* => 455.50 */
/* 480.00 => 94 */ 0x5e, /* => 475.00 */
/* 496.00 => 95 */ 0x5f, /* => 495.00 */
/* 512.00 => 95 */ 0x5f, /* => 495.00 */
/* 544.00 => 97 */ 0x61, /* => 537.00 */
/* 576.00 => 98 */ 0x62, /* => 559.00 */
/* 608.00 => 100 */ 0x64, /* => 607.00 */
/* 640.00 => 101 */ 0x65, /* => 632.00 */
/* 672.00 => 102 */ 0x66, /* => 660.00 */
/* 704.00 => 103 */ 0x67, /* => 687.00 */
/* 736.00 => 104 */ 0x68, /* => 716.00 */
/* 768.00 => 105 */ 0x69, /* => 746.00 */
/* 800.00 => 106 */ 0x6a, /* => 777.00 */
/* 832.00 => 107 */ 0x6b, /* => 810.00 */
/* 864.00 => 108 */ 0x6c, /* => 843.00 */
/* 896.00 => 109 */ 0x6d, /* => 879.00 */
/* 928.00 => 110 */ 0x6e, /* => 916.00 */
/* 960.00 => 111 */ 0x6f, /* => 954.00 */
/* 992.00 => 111 */ 0x6f, /* => 954.00 */
/* 1024.00 => 112 */ 0x70, /* => 994.00 */
/* 1088.00 => 114 */ 0x72, /* => 1080.00 */
/* 1152.00 => 115 */ 0x73, /* => 1124.00 */
/* 1216.00 => 116 */ 0x74, /* => 1172.00 */
/* 1280.00 => 118 */ 0x76, /* => 1272.00 */
/* 1344.00 => 119 */ 0x77, /* => 1326.00 */
/* 1408.00 => 120 */ 0x78, /* => 1382.00 */
/* 1472.00 => 121 */ 0x79, /* => 1440.00 */
/* 1536.00 => 122 */ 0x7a, /* => 1498.00 */
/* 1600.00 => 123 */ 0x7b, /* => 1562.00 */
/* 1664.00 => 124 */ 0x7c, /* => 1628.00 */
/* 1728.00 => 125 */ 0x7d, /* => 1696.00 */
/* 1792.00 => 126 */ 0x7e, /* => 1768.00 */
/* 1856.00 => 127 */ 0x7f, /* => 1842.00 */
/* 1920.00 => 128 */ 0x80, /* => 1918.00 */
/* 1984.00 => 128 */ 0x80, /* => 1918.00 */
/* 2048.00 => 129 */ 0x81, /* => 2000.00 */
/* 2176.00 => 131 */ 0x83, /* => 2168.00 */
/* 2304.00 => 132 */ 0x84, /* => 2264.00 */
/* 2432.00 => 133 */ 0x85, /* => 2356.00 */
/* 2560.00 => 135 */ 0x87, /* => 2556.00 */
/* 2688.00 => 136 */ 0x88, /* => 2664.00 */
/* 2816.00 => 137 */ 0x89, /* => 2776.00 */
/* 2944.00 => 138 */ 0x8a, /* => 2892.00 */
/* 3072.00 => 139 */ 0x8b, /* => 3012.00 */
/* 3200.00 => 140 */ 0x8c, /* => 3140.00 */
/* 3328.00 => 141 */ 0x8d, /* => 3272.00 */
/* 3456.00 => 142 */ 0x8e, /* => 3412.00 */
/* 3584.00 => 143 */ 0x8f, /* => 3552.00 */
/* 3712.00 => 144 */ 0x90, /* => 3700.00 */
/* 3840.00 => 144 */ 0x90, /* => 3700.00 */
/* 3968.00 => 145 */ 0x91, /* => 3860.00 */
/* 4096.00 => 146 */ 0x92, /* => 4016.00 */
/* 4352.00 => 147 */ 0x93, /* => 4184.00 */
/* 4608.00 => 149 */ 0x95, /* => 4544.00 */
/* 4864.00 => 150 */ 0x96, /* => 4736.00 */
/* 5120.00 => 151 */ 0x97, /* => 4936.00 */
/* 5376.00 => 153 */ 0x99, /* => 5360.00 */
/* 5632.00 => 154 */ 0x9a, /* => 5584.00 */
/* 5888.00 => 155 */ 0x9b, /* => 5816.00 */
/* 6144.00 => 156 */ 0x9c, /* => 6056.00 */
/* 6400.00 => 157 */ 0x9d, /* => 6312.00 */
/* 6656.00 => 158 */ 0x9e, /* => 6576.00 */
/* 6912.00 => 159 */ 0x9f, /* => 6856.00 */
/* 7168.00 => 160 */ 0xa0, /* => 7144.00 */
/* 7424.00 => 160 */ 0xa0, /* => 7144.00 */
/* 7680.00 => 161 */ 0xa1, /* => 7440.00 */
/* 7936.00 => 162 */ 0xa2, /* => 7752.00 */
/* 8192.00 => 163 */ 0xa3, /* => 8080.00 */
/* 8704.00 => 164 */ 0xa4, /* => 8416.00 */
/* 9216.00 => 166 */ 0xa6, /* => 9136.00 */
/* 9728.00 => 167 */ 0xa7, /* => 9520.00 */
/* 10240.00 => 168 */ 0xa8, /* => 9920.00 */
/* 10752.00 => 169 */ 0xa9, /* => 10336.00 */
/* 11264.00 => 171 */ 0xab, /* => 11216.00 */
/* 11776.00 => 172 */ 0xac, /* => 11680.00 */
/* 12288.00 => 173 */ 0xad, /* => 12176.00 */
/* 12800.00 => 174 */ 0xae, /* => 12688.00 */
/* 13312.00 => 175 */ 0xaf, /* => 13216.00 */
/* 13824.00 => 176 */ 0xb0, /* => 13776.00 */
/* 14336.00 => 176 */ 0xb0, /* => 13776.00 */
/* 14848.00 => 177 */ 0xb1, /* => 14352.00 */
/* 15360.00 => 178 */ 0xb2, /* => 14960.00 */
/* 15872.00 => 179 */ 0xb3, /* => 15584.00 */
/* 16384.00 => 180 */ 0xb4, /* => 16224.00 */
/* 17408.00 => 181 */ 0xb5, /* => 16896.00 */
/* 18432.00 => 183 */ 0xb7, /* => 18368.00 */
/* 19456.00 => 184 */ 0xb8, /* => 19136.00 */
/* 20480.00 => 185 */ 0xb9, /* => 19904.00 */
/* 21504.00 => 186 */ 0xba, /* => 20768.00 */
/* 22528.00 => 187 */ 0xbb, /* => 21632.00 */
/* 23552.00 => 189 */ 0xbd, /* => 23488.00 */
/* 24576.00 => 190 */ 0xbe, /* => 24512.00 */
/* 25600.00 => 191 */ 0xbf, /* => 25504.00 */
/* 26624.00 => 192 */ 0xc0, /* => 26592.00 */
/* 27648.00 => 192 */ 0xc0, /* => 26592.00 */
/* 28672.00 => 193 */ 0xc1, /* => 27680.00 */
/* 29696.00 => 194 */ 0xc2, /* => 28896.00 */
/* 30720.00 => 195 */ 0xc3, /* => 30048.00 */
/* 31744.00 => 196 */ 0xc4, /* => 31392.00 */
/* 32768.00 => 197 */ 0xc5, /* => 32640.00 */
/* 34816.00 => 198 */ 0xc6, /* => 33984.00 */
/* 36864.00 => 199 */ 0xc7, /* => 35392.00 */
/* 38912.00 => 201 */ 0xc9, /* => 38528.00 */
/* 40960.00 => 202 */ 0xca, /* => 40064.00 */
/* 43008.00 => 203 */ 0xcb, /* => 41856.00 */
/* 45056.00 => 204 */ 0xcc, /* => 43584.00 */
/* 47104.00 => 205 */ 0xcd, /* => 45376.00 */
/* 49152.00 => 206 */ 0xce, /* => 47232.00 */
/* 51200.00 => 207 */ 0xcf, /* => 49344.00 */
/* 53248.00 => 208 */ 0xd0, /* => 51328.00 */
/* 55296.00 => 209 */ 0xd1, /* => 53504.00 */
/* 57344.00 => 210 */ 0xd2, /* => 55616.00 */
/* 59392.00 => 211 */ 0xd3, /* => 58240.00 */
/* 61440.00 => 212 */ 0xd4, /* => 60416.00 */
/* 63488.00 => 213 */ 0xd5, /* => 63104.00 */
/* 65536.00 => 213 */ 0xd5, /* => 63104.00 */
/* 69632.00 => 215 */ 0xd7, /* => 68480.00 */
/* 73728.00 => 216 */ 0xd8, /* => 71424.00 */
/* 77824.00 => 218 */ 0xda, /* => 77312.00 */
/* 81920.00 => 219 */ 0xdb, /* => 80640.00 */
/* 86016.00 => 220 */ 0xdc, /* => 84224.00 */
/* 90112.00 => 221 */ 0xdd, /* => 87552.00 */
/* 94208.00 => 222 */ 0xde, /* => 91136.00 */
/* 98304.00 => 223 */ 0xdf, /* => 94976.00 */
/* 102400.00 => 224 */ 0xe0, /* => 99072.00 */
/* 106496.00 => 225 */ 0xe1, /* => 103680.00 */
/* 110592.00 => 226 */ 0xe2, /* => 107520.00 */
/* 114688.00 => 227 */ 0xe3, /* => 111872.00 */
/* 118784.00 => 228 */ 0xe4, /* => 117632.00 */
/* 122880.00 => 229 */ 0xe5, /* => 121472.00 */
/* 126976.00 => 229 */ 0xe5, /* => 121472.00 */
/* 131072.00 => 230 */ 0xe6, /* => 126976.00 */
/* 139264.00 => 232 */ 0xe8, /* => 137728.00 */
/* 147456.00 => 233 */ 0xe9, /* => 144896.00 */
/* 155648.00 => 234 */ 0xea, /* => 150528.00 */
/* 163840.00 => 236 */ 0xec, /* => 163584.00 */
/* 172032.00 => 237 */ 0xed, /* => 168448.00 */
/* 180224.00 => 238 */ 0xee, /* => 176384.00 */
/* 188416.00 => 239 */ 0xef, /* => 185088.00 */
/* 196608.00 => 240 */ 0xf0, /* => 191488.00 */
/* 204800.00 => 241 */ 0xf1, /* => 201728.00 */
/* 212992.00 => 242 */ 0xf2, /* => 209152.00 */
/* 221184.00 => 243 */ 0xf3, /* => 217344.00 */
/* 229376.00 => 244 */ 0xf4, /* => 226048.00 */
/* 237568.00 => 245 */ 0xf5, /* => 235264.00 */
/* 245760.00 => 246 */ 0xf6, /* => 245504.00 */
/* 253952.00 => 246 */ 0xf6, /* => 245504.00 */
/* 262144.00 => 247 */ 0xf7, /* => 256768.00 */
/* 278528.00 => 248 */ 0xf8, /* => 268800.00 */
/* 294912.00 => 250 */ 0xfa, /* => 289792.00 */
/* 311296.00 => 251 */ 0xfb, /* => 305152.00 */
/* 327680.00 => 252 */ 0xfc, /* => 313856.00 */
/* 344064.00 => 254 */ 0xfe, /* => 342016.00 */
/* 360448.00 => 255 */ 0xff, /* => 352768.00 */
/* 376832.00 => 255 */ 0xff, /* => 352768.00 */
/* 393216.00 => 255 */ 0xff, /* => 352768.00 */
/* 409600.00 => 255 */ 0xff, /* => 352768.00 */
/* 425984.00 => 255 */ 0xff, /* => 352768.00 */
/* 442368.00 => 255 */ 0xff, /* => 352768.00 */
/* 458752.00 => 255 */ 0xff, /* => 352768.00 */
/* 475136.00 => 255 */ 0xff, /* => 352768.00 */
/* 491520.00 => 255 */ 0xff, /* => 352768.00 */
/* 507904.00 => 255 */ 0xff, /* => 352768.00 */
/* 524288.00 => 255 */ 0xff, /* => 352768.00 */
/* 557056.00 => 255 */ 0xff, /* => 352768.00 */
/* 589824.00 => 255 */ 0xff, /* => 352768.00 */
/* 622592.00 => 255 */ 0xff, /* => 352768.00 */
/* 655360.00 => 255 */ 0xff, /* => 352768.00 */
/* 688128.00 => 255 */ 0xff, /* => 352768.00 */
/* 720896.00 => 255 */ 0xff, /* => 352768.00 */
/* 753664.00 => 255 */ 0xff, /* => 352768.00 */
/* 786432.00 => 255 */ 0xff, /* => 352768.00 */
/* 819200.00 => 255 */ 0xff, /* => 352768.00 */
/* 851968.00 => 255 */ 0xff, /* => 352768.00 */
/* 884736.00 => 255 */ 0xff, /* => 352768.00 */
/* 917504.00 => 255 */ 0xff, /* => 352768.00 */
/* 950272.00 => 255 */ 0xff, /* => 352768.00 */
/* 983040.00 => 255 */ 0xff, /* => 352768.00 */
/* 1015808.00 => 255 */ 0xff, /* => 352768.00 */
/* 1048576.00 => 255 */ 0xff, /* => 352768.00 */
/* 1114112.00 => 255 */ 0xff, /* => 352768.00 */
/* 1179648.00 => 255 */ 0xff, /* => 352768.00 */
/* 1245184.00 => 255 */ 0xff, /* => 352768.00 */
/* 1310720.00 => 255 */ 0xff, /* => 352768.00 */
/* 1376256.00 => 255 */ 0xff, /* => 352768.00 */
/* 1441792.00 => 255 */ 0xff, /* => 352768.00 */
/* 1507328.00 => 255 */ 0xff, /* => 352768.00 */
/* 1572864.00 => 255 */ 0xff, /* => 352768.00 */
/* 1638400.00 => 255 */ 0xff, /* => 352768.00 */
/* 1703936.00 => 255 */ 0xff, /* => 352768.00 */
/* 1769472.00 => 255 */ 0xff, /* => 352768.00 */
/* 1835008.00 => 255 */ 0xff, /* => 352768.00 */
/* 1900544.00 => 255 */ 0xff, /* => 352768.00 */
/* 1966080.00 => 255 */ 0xff, /* => 352768.00 */
/* 2031616.00 => 255 */ 0xff, /* => 352768.00 */
/* 2097152.00 => 255 */ 0xff, /* => 352768.00 */
/* 2228224.00 => 255 */ 0xff, /* => 352768.00 */
/* 2359296.00 => 255 */ 0xff, /* => 352768.00 */
/* 2490368.00 => 255 */ 0xff, /* => 352768.00 */
/* 2621440.00 => 255 */ 0xff, /* => 352768.00 */
/* 2752512.00 => 255 */ 0xff, /* => 352768.00 */
/* 2883584.00 => 255 */ 0xff, /* => 352768.00 */
/* 3014656.00 => 255 */ 0xff, /* => 352768.00 */
/* 3145728.00 => 255 */ 0xff, /* => 352768.00 */
/* 3276800.00 => 255 */ 0xff, /* => 352768.00 */
/* 3407872.00 => 255 */ 0xff, /* => 352768.00 */
/* 3538944.00 => 255 */ 0xff, /* => 352768.00 */
/* 3670016.00 => 255 */ 0xff, /* => 352768.00 */
/* 3801088.00 => 255 */ 0xff, /* => 352768.00 */
/* 3932160.00 => 255 */ 0xff, /* => 352768.00 */
/* 4063232.00 => 255 */ 0xff, /* => 352768.00 */
/* 4194304.00 => 255 */ 0xff, /* => 352768.00 */
/* 4456448.00 => 255 */ 0xff, /* => 352768.00 */
/* 4718592.00 => 255 */ 0xff, /* => 352768.00 */
/* 4980736.00 => 255 */ 0xff, /* => 352768.00 */
/* 5242880.00 => 255 */ 0xff, /* => 352768.00 */
/* 5505024.00 => 255 */ 0xff, /* => 352768.00 */
/* 5767168.00 => 255 */ 0xff, /* => 352768.00 */
/* 6029312.00 => 255 */ 0xff, /* => 352768.00 */
/* 6291456.00 => 255 */ 0xff, /* => 352768.00 */
/* 6553600.00 => 255 */ 0xff, /* => 352768.00 */
/* 6815744.00 => 255 */ 0xff, /* => 352768.00 */
/* 7077888.00 => 255 */ 0xff, /* => 352768.00 */
/* 7340032.00 => 255 */ 0xff, /* => 352768.00 */
/* 7602176.00 => 255 */ 0xff, /* => 352768.00 */
/* 7864320.00 => 255 */ 0xff, /* => 352768.00 */
/* 8126464.00 => 255 */ 0xff, /* => 352768.00 */
/* 8388608.00 => 255 */ 0xff, /* => 352768.00 */
/* 8912896.00 => 255 */ 0xff, /* => 352768.00 */
/* 9437184.00 => 255 */ 0xff, /* => 352768.00 */
/* 9961472.00 => 255 */ 0xff, /* => 352768.00 */
/* 10485760.00 => 255 */ 0xff, /* => 352768.00 */
/* 11010048.00 => 255 */ 0xff, /* => 352768.00 */
/* 11534336.00 => 255 */ 0xff, /* => 352768.00 */
/* 12058624.00 => 255 */ 0xff, /* => 352768.00 */
/* 12582912.00 => 255 */ 0xff, /* => 352768.00 */
/* 13107200.00 => 255 */ 0xff, /* => 352768.00 */
/* 13631488.00 => 255 */ 0xff, /* => 352768.00 */
/* 14155776.00 => 255 */ 0xff, /* => 352768.00 */
/* 14680064.00 => 255 */ 0xff, /* => 352768.00 */
/* 15204352.00 => 255 */ 0xff, /* => 352768.00 */
/* 15728640.00 => 255 */ 0xff, /* => 352768.00 */
/* 16252928.00 => 255 */ 0xff, /* => 352768.00 */
/* 16777216.00 => 255 */ 0xff, /* => 352768.00 */
/* 17825792.00 => 255 */ 0xff, /* => 352768.00 */
/* 18874368.00 => 255 */ 0xff, /* => 352768.00 */
/* 19922944.00 => 255 */ 0xff, /* => 352768.00 */
/* 20971520.00 => 255 */ 0xff, /* => 352768.00 */
/* 22020096.00 => 255 */ 0xff, /* => 352768.00 */
/* 23068672.00 => 255 */ 0xff, /* => 352768.00 */
/* 24117248.00 => 255 */ 0xff, /* => 352768.00 */
/* 25165824.00 => 255 */ 0xff, /* => 352768.00 */
/* 26214400.00 => 255 */ 0xff, /* => 352768.00 */
/* 27262976.00 => 255 */ 0xff, /* => 352768.00 */
/* 28311552.00 => 255 */ 0xff, /* => 352768.00 */
/* 29360128.00 => 255 */ 0xff, /* => 352768.00 */
/* 30408704.00 => 255 */ 0xff, /* => 352768.00 */
/* 31457280.00 => 255 */ 0xff, /* => 352768.00 */
/* 32505856.00 => 255 */ 0xff, /* => 352768.00 */
/* 33554432.00 => 255 */ 0xff, /* => 352768.00 */
/* 35651584.00 => 255 */ 0xff, /* => 352768.00 */
/* 37748736.00 => 255 */ 0xff, /* => 352768.00 */
/* 39845888.00 => 255 */ 0xff, /* => 352768.00 */
/* 41943040.00 => 255 */ 0xff, /* => 352768.00 */
/* 44040192.00 => 255 */ 0xff, /* => 352768.00 */
/* 46137344.00 => 255 */ 0xff, /* => 352768.00 */
/* 48234496.00 => 255 */ 0xff, /* => 352768.00 */
/* 50331648.00 => 255 */ 0xff, /* => 352768.00 */
/* 52428800.00 => 255 */ 0xff, /* => 352768.00 */
/* 54525952.00 => 255 */ 0xff, /* => 352768.00 */
/* 56623104.00 => 255 */ 0xff, /* => 352768.00 */
/* 58720256.00 => 255 */ 0xff, /* => 352768.00 */
/* 60817408.00 => 255 */ 0xff, /* => 352768.00 */
/* 62914560.00 => 255 */ 0xff, /* => 352768.00 */
/* 65011712.00 => 255 */ 0xff, /* => 352768.00 */
/* 67108864.00 => 255 */ 0xff, /* => 352768.00 */
/* 71303168.00 => 255 */ 0xff, /* => 352768.00 */
/* 75497472.00 => 255 */ 0xff, /* => 352768.00 */
/* 79691776.00 => 255 */ 0xff, /* => 352768.00 */
/* 83886080.00 => 255 */ 0xff, /* => 352768.00 */
/* 88080384.00 => 255 */ 0xff, /* => 352768.00 */
/* 92274688.00 => 255 */ 0xff, /* => 352768.00 */
/* 96468992.00 => 255 */ 0xff, /* => 352768.00 */
/* 100663296.00 => 255 */ 0xff, /* => 352768.00 */
/* 104857600.00 => 255 */ 0xff, /* => 352768.00 */
/* 109051904.00 => 255 */ 0xff, /* => 352768.00 */
/* 113246208.00 => 255 */ 0xff, /* => 352768.00 */
/* 117440512.00 => 255 */ 0xff, /* => 352768.00 */
/* 121634816.00 => 255 */ 0xff, /* => 352768.00 */
/* 125829120.00 => 255 */ 0xff, /* => 352768.00 */
/* 130023424.00 => 255 */ 0xff, /* => 352768.00 */
/* 134217728.00 => 255 */ 0xff, /* => 352768.00 */
/* 142606336.00 => 255 */ 0xff, /* => 352768.00 */
/* 150994944.00 => 255 */ 0xff, /* => 352768.00 */
/* 159383552.00 => 255 */ 0xff, /* => 352768.00 */
/* 167772160.00 => 255 */ 0xff, /* => 352768.00 */
/* 176160768.00 => 255 */ 0xff, /* => 352768.00 */
/* 184549376.00 => 255 */ 0xff, /* => 352768.00 */
/* 192937984.00 => 255 */ 0xff, /* => 352768.00 */
/* 201326592.00 => 255 */ 0xff, /* => 352768.00 */
/* 209715200.00 => 255 */ 0xff, /* => 352768.00 */
/* 218103808.00 => 255 */ 0xff, /* => 352768.00 */
/* 226492416.00 => 255 */ 0xff, /* => 352768.00 */
/* 234881024.00 => 255 */ 0xff, /* => 352768.00 */
/* 243269632.00 => 255 */ 0xff, /* => 352768.00 */
/* 251658240.00 => 255 */ 0xff, /* => 352768.00 */
/* 260046848.00 => 255 */ 0xff, /* => 352768.00 */
/* 268435456.00 => 255 */ 0xff, /* => 352768.00 */
/* 285212672.00 => 255 */ 0xff, /* => 352768.00 */
/* 301989888.00 => 255 */ 0xff, /* => 352768.00 */
/* 318767104.00 => 255 */ 0xff, /* => 352768.00 */
/* 335544320.00 => 255 */ 0xff, /* => 352768.00 */
/* 352321536.00 => 255 */ 0xff, /* => 352768.00 */
/* 369098752.00 => 255 */ 0xff, /* => 352768.00 */
/* 385875968.00 => 255 */ 0xff, /* => 352768.00 */
/* 402653184.00 => 255 */ 0xff, /* => 352768.00 */
/* 419430400.00 => 255 */ 0xff, /* => 352768.00 */
/* 436207616.00 => 255 */ 0xff, /* => 352768.00 */
/* 452984832.00 => 255 */ 0xff, /* => 352768.00 */
/* 469762048.00 => 255 */ 0xff, /* => 352768.00 */
/* 486539264.00 => 255 */ 0xff, /* => 352768.00 */
/* 503316480.00 => 255 */ 0xff, /* => 352768.00 */
/* 520093696.00 => 255 */ 0xff, /* => 352768.00 */
/* 536870912.00 => 255 */ 0xff, /* => 352768.00 */
/* 570425344.00 => 255 */ 0xff, /* => 352768.00 */
/* 603979776.00 => 255 */ 0xff, /* => 352768.00 */
/* 637534208.00 => 255 */ 0xff, /* => 352768.00 */
/* 671088640.00 => 255 */ 0xff, /* => 352768.00 */
/* 704643072.00 => 255 */ 0xff, /* => 352768.00 */
/* 738197504.00 => 255 */ 0xff, /* => 352768.00 */
/* 771751936.00 => 255 */ 0xff, /* => 352768.00 */
/* 805306368.00 => 255 */ 0xff, /* => 352768.00 */
/* 838860800.00 => 255 */ 0xff, /* => 352768.00 */
/* 872415232.00 => 255 */ 0xff, /* => 352768.00 */
/* 905969664.00 => 255 */ 0xff, /* => 352768.00 */
/* 939524096.00 => 255 */ 0xff, /* => 352768.00 */
/* 973078528.00 => 255 */ 0xff, /* => 352768.00 */
/* 1006632960.00 => 255 */ 0xff, /* => 352768.00 */
/* 1040187392.00 => 255 */ 0xff, /* => 352768.00 */
/* 1073741824.00 => 255 */ 0xff, /* => 352768.00 */
/* 1140850688.00 => 255 */ 0xff, /* => 352768.00 */
/* 1207959552.00 => 255 */ 0xff, /* => 352768.00 */
/* 1275068416.00 => 255 */ 0xff, /* => 352768.00 */
/* 1342177280.00 => 255 */ 0xff, /* => 352768.00 */
/* 1409286144.00 => 255 */ 0xff, /* => 352768.00 */
/* 1476395008.00 => 255 */ 0xff, /* => 352768.00 */
/* 1543503872.00 => 255 */ 0xff, /* => 352768.00 */
/* 1610612736.00 => 255 */ 0xff, /* => 352768.00 */
/* 1677721600.00 => 255 */ 0xff, /* => 352768.00 */
/* 1744830464.00 => 255 */ 0xff, /* => 352768.00 */
/* 1811939328.00 => 255 */ 0xff, /* => 352768.00 */
/* 1879048192.00 => 255 */ 0xff, /* => 352768.00 */
/* 1946157056.00 => 255 */ 0xff, /* => 352768.00 */
/* 2013265920.00 => 255 */ 0xff, /* => 352768.00 */
/* 2080374784.00 => 255 */ 0xff, /* => 352768.00 */
/* 2147483648.00 => 255 */ 0xff, /* => 352768.00 */
/* 2281701376.00 => 255 */ 0xff, /* => 352768.00 */
/* 2415919104.00 => 255 */ 0xff, /* => 352768.00 */
/* 2550136832.00 => 255 */ 0xff, /* => 352768.00 */
/* 2684354560.00 => 255 */ 0xff, /* => 352768.00 */
/* 2818572288.00 => 255 */ 0xff, /* => 352768.00 */
/* 2952790016.00 => 255 */ 0xff, /* => 352768.00 */
/* 3087007744.00 => 255 */ 0xff, /* => 352768.00 */
/* 3221225472.00 => 255 */ 0xff, /* => 352768.00 */
/* 3355443200.00 => 255 */ 0xff, /* => 352768.00 */
/* 3489660928.00 => 255 */ 0xff, /* => 352768.00 */
/* 3623878656.00 => 255 */ 0xff, /* => 352768.00 */
/* 3758096384.00 => 255 */ 0xff, /* => 352768.00 */
/* 3892314112.00 => 255 */ 0xff, /* => 352768.00 */
/* 4026531840.00 => 255 */ 0xff, /* => 352768.00 */
/* 4160749568.00 => 255 */ 0xff, /* => 352768.00 */
};

3283
drivers/atm/iphase.c
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1452
drivers/atm/iphase.h
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2603
drivers/atm/lanai.c
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266
drivers/atm/midway.h
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@ -1,266 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/midway.h - Efficient Networks Midway (SAR) description */
/* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
#ifndef DRIVERS_ATM_MIDWAY_H
#define DRIVERS_ATM_MIDWAY_H
#define NR_VCI 1024 /* number of VCIs */
#define NR_VCI_LD 10 /* log2(NR_VCI) */
#define NR_DMA_RX 512 /* RX DMA queue entries */
#define NR_DMA_TX 512 /* TX DMA queue entries */
#define NR_SERVICE NR_VCI /* service list size */
#define NR_CHAN 8 /* number of TX channels */
#define TS_CLOCK 25000000 /* traffic shaper clock (cell/sec) */
#define MAP_MAX_SIZE 0x00400000 /* memory window for max config */
#define EPROM_SIZE 0x00010000
#define MEM_VALID 0xffc00000 /* mask base address with this */
#define PHY_BASE 0x00020000 /* offset of PHY register are */
#define REG_BASE 0x00040000 /* offset of Midway register area */
#define RAM_BASE 0x00200000 /* offset of RAM area */
#define RAM_INCREMENT 0x00020000 /* probe for RAM every 128kB */
#define MID_VCI_BASE RAM_BASE
#define MID_DMA_RX_BASE (MID_VCI_BASE+NR_VCI*16)
#define MID_DMA_TX_BASE (MID_DMA_RX_BASE+NR_DMA_RX*8)
#define MID_SERVICE_BASE (MID_DMA_TX_BASE+NR_DMA_TX*8)
#define MID_FREE_BASE (MID_SERVICE_BASE+NR_SERVICE*4)
#define MAC_LEN 6 /* atm.h */
#define MID_MIN_BUF_SIZE (1024) /* 1 kB is minimum */
#define MID_MAX_BUF_SIZE (128*1024) /* 128 kB is maximum */
#define RX_DESCR_SIZE 1 /* RX PDU descr is 1 longword */
#define TX_DESCR_SIZE 2 /* TX PDU descr is 2 longwords */
#define AAL5_TRAILER (ATM_AAL5_TRAILER/4) /* AAL5 trailer is 2 longwords */
#define TX_GAP 8 /* TX buffer gap (words) */
/*
* Midway Reset/ID
*
* All values read-only. Writing to this register resets Midway chip.
*/
#define MID_RES_ID_MCON 0x00 /* Midway Reset/ID */
#define MID_ID 0xf0000000 /* Midway version */
#define MID_SHIFT 24
#define MID_MOTHER_ID 0x00000700 /* mother board id */
#define MID_MOTHER_SHIFT 8
#define MID_CON_TI 0x00000080 /* 0: normal ctrl; 1: SABRE */
#define MID_CON_SUNI 0x00000040 /* 0: UTOPIA; 1: SUNI */
#define MID_CON_V6 0x00000020 /* 0: non-pipel UTOPIA (required iff
!CON_SUNI; 1: UTOPIA */
#define DAUGHTER_ID 0x0000001f /* daughter board id */
/*
* Interrupt Status Acknowledge, Interrupt Status & Interrupt Enable
*/
#define MID_ISA 0x01 /* Interrupt Status Acknowledge */
#define MID_IS 0x02 /* Interrupt Status */
#define MID_IE 0x03 /* Interrupt Enable */
#define MID_TX_COMPLETE_7 0x00010000 /* channel N completed a PDU */
#define MID_TX_COMPLETE_6 0x00008000 /* transmission */
#define MID_TX_COMPLETE_5 0x00004000
#define MID_TX_COMPLETE_4 0x00002000
#define MID_TX_COMPLETE_3 0x00001000
#define MID_TX_COMPLETE_2 0x00000800
#define MID_TX_COMPLETE_1 0x00000400
#define MID_TX_COMPLETE_0 0x00000200
#define MID_TX_COMPLETE 0x0001fe00 /* any TX */
#define MID_TX_DMA_OVFL 0x00000100 /* DMA to adapter overflow */
#define MID_TX_IDENT_MISM 0x00000080 /* TX: ident mismatch => halted */
#define MID_DMA_LERR_ACK 0x00000040 /* LERR - SBus ? */
#define MID_DMA_ERR_ACK 0x00000020 /* DMA error */
#define MID_RX_DMA_COMPLETE 0x00000010 /* DMA to host done */
#define MID_TX_DMA_COMPLETE 0x00000008 /* DMA from host done */
#define MID_SERVICE 0x00000004 /* something in service list */
#define MID_SUNI_INT 0x00000002 /* interrupt from SUNI */
#define MID_STAT_OVFL 0x00000001 /* statistics overflow */
/*
* Master Control/Status
*/
#define MID_MC_S 0x04
#define MID_INT_SELECT 0x000001C0 /* Interrupt level (000: off) */
#define MID_INT_SEL_SHIFT 6
#define MID_TX_LOCK_MODE 0x00000020 /* 0: streaming; 1: TX ovfl->lock */
#define MID_DMA_ENABLE 0x00000010 /* R: 0: disable; 1: enable
W: 0: no change; 1: enable */
#define MID_TX_ENABLE 0x00000008 /* R: 0: TX disabled; 1: enabled
W: 0: no change; 1: enable */
#define MID_RX_ENABLE 0x00000004 /* like TX */
#define MID_WAIT_1MS 0x00000002 /* R: 0: timer not running; 1: running
W: 0: no change; 1: no interrupts
for 1 ms */
#define MID_WAIT_500US 0x00000001 /* like WAIT_1MS, but 0.5 ms */
/*
* Statistics
*
* Cleared when reading.
*/
#define MID_STAT 0x05
#define MID_VCI_TRASH 0xFFFF0000 /* trashed cells because of VCI mode */
#define MID_VCI_TRASH_SHIFT 16
#define MID_OVFL_TRASH 0x0000FFFF /* trashed cells because of overflow */
/*
* Address registers
*/
#define MID_SERV_WRITE 0x06 /* free pos in service area (R, 10 bits) */
#define MID_DMA_ADDR 0x07 /* virtual DMA address (R, 32 bits) */
#define MID_DMA_WR_RX 0x08 /* (RW, 9 bits) */
#define MID_DMA_RD_RX 0x09
#define MID_DMA_WR_TX 0x0A
#define MID_DMA_RD_TX 0x0B
/*
* Transmit Place Registers (0x10+4*channel)
*/
#define MID_TX_PLACE(c) (0x10+4*(c))
#define MID_SIZE 0x00003800 /* size, N*256 x 32 bit */
#define MID_SIZE_SHIFT 11
#define MID_LOCATION 0x000007FF /* location in adapter memory (word) */
#define MID_LOC_SKIP 8 /* 8 bits of location are always zero
(applies to all uses of location) */
/*
* Transmit ReadPtr Registers (0x11+4*channel)
*/
#define MID_TX_RDPTR(c) (0x11+4*(c))
#define MID_READ_PTR 0x00007FFF /* next word for PHY */
/*
* Transmit DescrStart Registers (0x12+4*channel)
*/
#define MID_TX_DESCRSTART(c) (0x12+4*(c))
#define MID_DESCR_START 0x00007FFF /* seg buffer being DMAed */
#define ENI155_MAGIC 0xa54b872d
struct midway_eprom {
unsigned char mac[MAC_LEN],inv_mac[MAC_LEN];
unsigned char pad[36];
u32 serial,inv_serial;
u32 magic,inv_magic;
};
/*
* VCI table entry
*/
#define MID_VCI_IN_SERVICE 0x00000001 /* set if VCI is currently in
service list */
#define MID_VCI_SIZE 0x00038000 /* reassembly buffer size,
2*<size> kB */
#define MID_VCI_SIZE_SHIFT 15
#define MID_VCI_LOCATION 0x1ffc0000 /* buffer location */
#define MID_VCI_LOCATION_SHIFT 18
#define MID_VCI_PTI_MODE 0x20000000 /* 0: trash, 1: preserve */
#define MID_VCI_MODE 0xc0000000
#define MID_VCI_MODE_SHIFT 30
#define MID_VCI_READ 0x00007fff
#define MID_VCI_READ_SHIFT 0
#define MID_VCI_DESCR 0x7fff0000
#define MID_VCI_DESCR_SHIFT 16
#define MID_VCI_COUNT 0x000007ff
#define MID_VCI_COUNT_SHIFT 0
#define MID_VCI_STATE 0x0000c000
#define MID_VCI_STATE_SHIFT 14
#define MID_VCI_WRITE 0x7fff0000
#define MID_VCI_WRITE_SHIFT 16
#define MID_MODE_TRASH 0
#define MID_MODE_RAW 1
#define MID_MODE_AAL5 2
/*
* Reassembly buffer descriptor
*/
#define MID_RED_COUNT 0x000007ff
#define MID_RED_CRC_ERR 0x00000800
#define MID_RED_T 0x00001000
#define MID_RED_CE 0x00010000
#define MID_RED_CLP 0x01000000
#define MID_RED_IDEN 0xfe000000
#define MID_RED_SHIFT 25
#define MID_RED_RX_ID 0x1b /* constant identifier */
/*
* Segmentation buffer descriptor
*/
#define MID_SEG_COUNT MID_RED_COUNT
#define MID_SEG_RATE 0x01f80000
#define MID_SEG_RATE_SHIFT 19
#define MID_SEG_PR 0x06000000
#define MID_SEG_PR_SHIFT 25
#define MID_SEG_AAL5 0x08000000
#define MID_SEG_ID 0xf0000000
#define MID_SEG_ID_SHIFT 28
#define MID_SEG_MAX_RATE 63
#define MID_SEG_CLP 0x00000001
#define MID_SEG_PTI 0x0000000e
#define MID_SEG_PTI_SHIFT 1
#define MID_SEG_VCI 0x00003ff0
#define MID_SEG_VCI_SHIFT 4
#define MID_SEG_TX_ID 0xb /* constant identifier */
/*
* DMA entry
*/
#define MID_DMA_COUNT 0xffff0000
#define MID_DMA_COUNT_SHIFT 16
#define MID_DMA_END 0x00000020
#define MID_DMA_TYPE 0x0000000f
#define MID_DT_JK 0x3
#define MID_DT_WORD 0x0
#define MID_DT_2W 0x7
#define MID_DT_4W 0x4
#define MID_DT_8W 0x5
#define MID_DT_16W 0x6
#define MID_DT_2WM 0xf
#define MID_DT_4WM 0xc
#define MID_DT_8WM 0xd
#define MID_DT_16WM 0xe
/* only for RX*/
#define MID_DMA_VCI 0x0000ffc0
#define MID_DMA_VCI_SHIFT 6
/* only for TX */
#define MID_DMA_CHAN 0x000001c0
#define MID_DMA_CHAN_SHIFT 6
#define MID_DT_BYTE 0x1
#define MID_DT_HWORD 0x2
#endif

2759
drivers/atm/nicstar.c
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drivers/atm/nicstar.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* nicstar.h
*
* Header file for the nicstar device driver.
*
* Author: Rui Prior (rprior@inescn.pt)
* PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
*
* (C) INESC 1998
*/
#ifndef _LINUX_NICSTAR_H_
#define _LINUX_NICSTAR_H_
/* Includes */
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/idr.h>
#include <linux/uio.h>
#include <linux/skbuff.h>
#include <linux/atmdev.h>
#include <linux/atm_nicstar.h>
/* Options */
#define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards
controlled by the device driver. Must
be <= 5 */
#undef RCQ_SUPPORT /* Do not define this for now */
#define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */
#define NS_TST_RESERVED 340 /* N. entries reserved for UBR/ABR/VBR */
#define NS_SMBUFSIZE 48 /* 48, 96, 240 or 2048 */
#define NS_LGBUFSIZE 16384 /* 2048, 4096, 8192 or 16384 */
#define NS_RSQSIZE 8192 /* 2048, 4096 or 8192 */
#define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
#define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384.
Define 4096 only if (all) your card(s)
have 32K x 32bit SRAM, in which case
setting this to 16384 will just waste a
lot of memory.
Setting this to 4096 for a card with
128K x 32bit SRAM will limit the maximum
VCI. */
/*#define NS_PCI_LATENCY 64*//* Must be a multiple of 32 */
/* Number of buffers initially allocated */
#define NUM_SB 32 /* Must be even */
#define NUM_LB 24 /* Must be even */
#define NUM_HB 8 /* Pre-allocated huge buffers */
#define NUM_IOVB 48 /* Iovec buffers */
/* Lower level for count of buffers */
#define MIN_SB 8 /* Must be even */
#define MIN_LB 8 /* Must be even */
#define MIN_HB 6
#define MIN_IOVB 8
/* Upper level for count of buffers */
#define MAX_SB 64 /* Must be even, <= 508 */
#define MAX_LB 48 /* Must be even, <= 508 */
#define MAX_HB 10
#define MAX_IOVB 80
/* These are the absolute maximum allowed for the ioctl() */
#define TOP_SB 256 /* Must be even, <= 508 */
#define TOP_LB 128 /* Must be even, <= 508 */
#define TOP_HB 64
#define TOP_IOVB 256
#define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */
#define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */
#undef ENABLE_TSQFIE
#define SCQFULL_TIMEOUT (5 * HZ)
#define NS_POLL_PERIOD (HZ)
#define PCR_TOLERANCE (1.0001)
/* ESI stuff */
#define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
#define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
/* #defines */
#define NS_IOREMAP_SIZE 4096
/*
* BUF_XX distinguish the Rx buffers depending on their (small/large) size.
* BUG_SM and BUG_LG are both used by the driver and the device.
* BUF_NONE is only used by the driver.
*/
#define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */
#define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */
#define BUF_NONE 0xffffffff /* Software only: */
#define NS_HBUFSIZE 65568 /* Size of max. AAL5 PDU */
#define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
(NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
#define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))
#define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
#define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
#define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
#define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
#define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
/* NICStAR structures located in host memory */
/*
* RSQ - Receive Status Queue
*
* Written by the NICStAR, read by the device driver.
*/
typedef struct ns_rsqe {
u32 word_1;
u32 buffer_handle;
u32 final_aal5_crc32;
u32 word_4;
} ns_rsqe;
#define ns_rsqe_vpi(ns_rsqep) \
((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
#define ns_rsqe_vci(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
#define NS_RSQE_VALID 0x80000000
#define NS_RSQE_NZGFC 0x00004000
#define NS_RSQE_EOPDU 0x00002000
#define NS_RSQE_BUFSIZE 0x00001000
#define NS_RSQE_CONGESTION 0x00000800
#define NS_RSQE_CLP 0x00000400
#define NS_RSQE_CRCERR 0x00000200
#define NS_RSQE_BUFSIZE_SM 0x00000000
#define NS_RSQE_BUFSIZE_LG 0x00001000
#define ns_rsqe_valid(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
#define ns_rsqe_nzgfc(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
#define ns_rsqe_eopdu(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
#define ns_rsqe_bufsize(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
#define ns_rsqe_congestion(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
#define ns_rsqe_clp(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
#define ns_rsqe_crcerr(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
#define ns_rsqe_cellcount(ns_rsqep) \
(le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
#define ns_rsqe_init(ns_rsqep) \
((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
#define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
#define NS_RSQ_ALIGNMENT NS_RSQSIZE
/*
* RCQ - Raw Cell Queue
*
* Written by the NICStAR, read by the device driver.
*/
typedef struct cell_payload {
u32 word[12];
} cell_payload;
typedef struct ns_rcqe {
u32 word_1;
u32 word_2;
u32 word_3;
u32 word_4;
cell_payload payload;
} ns_rcqe;
#define NS_RCQE_SIZE 64 /* bytes */
#define ns_rcqe_islast(ns_rcqep) \
(le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
#define ns_rcqe_cellheader(ns_rcqep) \
(le32_to_cpu((ns_rcqep)->word_1))
#define ns_rcqe_nextbufhandle(ns_rcqep) \
(le32_to_cpu((ns_rcqep)->word_2))
/*
* SCQ - Segmentation Channel Queue
*
* Written by the device driver, read by the NICStAR.
*/
typedef struct ns_scqe {
u32 word_1;
u32 word_2;
u32 word_3;
u32 word_4;
} ns_scqe;
/* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
or TSR (Transmit Status Requests) */
#define NS_SCQE_TYPE_TBD 0x00000000
#define NS_SCQE_TYPE_TSR 0x80000000
#define NS_TBD_EOPDU 0x40000000
#define NS_TBD_AAL0 0x00000000
#define NS_TBD_AAL34 0x04000000
#define NS_TBD_AAL5 0x08000000
#define NS_TBD_VPI_MASK 0x0FF00000
#define NS_TBD_VCI_MASK 0x000FFFF0
#define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)
#define NS_TBD_VPI_SHIFT 20
#define NS_TBD_VCI_SHIFT 4
#define ns_tbd_mkword_1(flags, m, n, buflen) \
(cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))
#define ns_tbd_mkword_1_novbr(flags, buflen) \
(cpu_to_le32((flags) | (buflen) | 0x00810000))
#define ns_tbd_mkword_3(control, pdulen) \
(cpu_to_le32((control) << 16 | (pdulen)))
#define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
(cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))
#define NS_TSR_INTENABLE 0x20000000
#define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */
#define ns_tsr_mkword_1(flags) \
(cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
#define ns_tsr_mkword_2(scdi, scqi) \
(cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
#define ns_scqe_is_tsr(ns_scqep) \
(le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
#define VBR_SCQ_NUM_ENTRIES 512
#define VBR_SCQSIZE 8192
#define CBR_SCQ_NUM_ENTRIES 64
#define CBR_SCQSIZE 1024
#define NS_SCQE_SIZE 16
/*
* TSQ - Transmit Status Queue
*
* Written by the NICStAR, read by the device driver.
*/
typedef struct ns_tsi {
u32 word_1;
u32 word_2;
} ns_tsi;
/* NOTE: The first word can be a status word copied from the TSR which
originated the TSI, or a timer overflow indicator. In this last
case, the value of the first word is all zeroes. */
#define NS_TSI_EMPTY 0x80000000
#define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
#define ns_tsi_isempty(ns_tsip) \
(le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
#define ns_tsi_gettimestamp(ns_tsip) \
(le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
#define ns_tsi_init(ns_tsip) \
((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
#define NS_TSQSIZE 8192
#define NS_TSQ_NUM_ENTRIES 1024
#define NS_TSQ_ALIGNMENT 8192
#define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
#define ns_tsi_tmrof(ns_tsip) \
(le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
#define ns_tsi_getscdindex(ns_tsip) \
((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
#define ns_tsi_getscqpos(ns_tsip) \
(le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
/* NICStAR structures located in local SRAM */
/*
* RCT - Receive Connection Table
*
* Written by both the NICStAR and the device driver.
*/
typedef struct ns_rcte {
u32 word_1;
u32 buffer_handle;
u32 dma_address;
u32 aal5_crc32;
} ns_rcte;
#define NS_RCTE_BSFB 0x00200000 /* Rev. D only */
#define NS_RCTE_NZGFC 0x00100000
#define NS_RCTE_CONNECTOPEN 0x00080000
#define NS_RCTE_AALMASK 0x00070000
#define NS_RCTE_AAL0 0x00000000
#define NS_RCTE_AAL34 0x00010000
#define NS_RCTE_AAL5 0x00020000
#define NS_RCTE_RCQ 0x00030000
#define NS_RCTE_RAWCELLINTEN 0x00008000
#define NS_RCTE_RXCONSTCELLADDR 0x00004000
#define NS_RCTE_BUFFVALID 0x00002000
#define NS_RCTE_FBDSIZE 0x00001000
#define NS_RCTE_EFCI 0x00000800
#define NS_RCTE_CLP 0x00000400
#define NS_RCTE_CRCERROR 0x00000200
#define NS_RCTE_CELLCOUNT_MASK 0x000001FF
#define NS_RCTE_FBDSIZE_SM 0x00000000
#define NS_RCTE_FBDSIZE_LG 0x00001000
#define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */
/* NOTE: We could make macros to contruct the first word of the RCTE,
but that doesn't seem to make much sense... */
/*
* FBD - Free Buffer Descriptor
*
* Written by the device driver using via the command register.
*/
typedef struct ns_fbd {
u32 buffer_handle;
u32 dma_address;
} ns_fbd;
/*
* TST - Transmit Schedule Table
*
* Written by the device driver.
*/
typedef u32 ns_tste;
#define NS_TST_OPCODE_MASK 0x60000000
#define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */
#define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */
#define NS_TST_OPCODE_VARIABLE 0x40000000
#define NS_TST_OPCODE_END 0x60000000 /* Jump */
#define ns_tste_make(opcode, sramad) (opcode | sramad)
/* NOTE:
- When the opcode is FIXED, sramad specifies the SRAM address of the
SCD for that fixed rate channel.
- When the opcode is END, sramad specifies the SRAM address of the
location of the next TST entry to read.
*/
/*
* SCD - Segmentation Channel Descriptor
*
* Written by both the device driver and the NICStAR
*/
typedef struct ns_scd {
u32 word_1;
u32 word_2;
u32 partial_aal5_crc;
u32 reserved;
ns_scqe cache_a;
ns_scqe cache_b;
} ns_scd;
#define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */
#define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */
#define NS_SCD_TAIL_MASK_VAR 0x00001FF0
#define NS_SCD_TAIL_MASK_FIX 0x000003F0
#define NS_SCD_HEAD_MASK_VAR 0x00001FF0
#define NS_SCD_HEAD_MASK_FIX 0x000003F0
#define NS_SCD_XMITFOREVER 0x02000000
/* NOTE: There are other fields in word 2 of the SCD, but as they should
not be needed in the device driver they are not defined here. */
/* NICStAR local SRAM memory map */
#define NS_RCT 0x00000
#define NS_RCT_32_END 0x03FFF
#define NS_RCT_128_END 0x0FFFF
#define NS_UNUSED_32 0x04000
#define NS_UNUSED_128 0x10000
#define NS_UNUSED_END 0x1BFFF
#define NS_TST_FRSCD 0x1C000
#define NS_TST_FRSCD_END 0x1E7DB
#define NS_VRSCD2 0x1E7DC
#define NS_VRSCD2_END 0x1E7E7
#define NS_VRSCD1 0x1E7E8
#define NS_VRSCD1_END 0x1E7F3
#define NS_VRSCD0 0x1E7F4
#define NS_VRSCD0_END 0x1E7FF
#define NS_RXFIFO 0x1E800
#define NS_RXFIFO_END 0x1F7FF
#define NS_SMFBQ 0x1F800
#define NS_SMFBQ_END 0x1FBFF
#define NS_LGFBQ 0x1FC00
#define NS_LGFBQ_END 0x1FFFF
/* NISCtAR operation registers */
/* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */
enum ns_regs {
DR0 = 0x00, /* Data Register 0 R/W */
DR1 = 0x04, /* Data Register 1 W */
DR2 = 0x08, /* Data Register 2 W */
DR3 = 0x0C, /* Data Register 3 W */
CMD = 0x10, /* Command W */
CFG = 0x14, /* Configuration R/W */
STAT = 0x18, /* Status R/W */
RSQB = 0x1C, /* Receive Status Queue Base W */
RSQT = 0x20, /* Receive Status Queue Tail R */
RSQH = 0x24, /* Receive Status Queue Head W */
CDC = 0x28, /* Cell Drop Counter R/clear */
VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */
ICC = 0x30, /* Invalid Cell Count R/clear */
RAWCT = 0x34, /* Raw Cell Tail R */
TMR = 0x38, /* Timer R */
TSTB = 0x3C, /* Transmit Schedule Table Base R/W */
TSQB = 0x40, /* Transmit Status Queue Base W */
TSQT = 0x44, /* Transmit Status Queue Tail R */
TSQH = 0x48, /* Transmit Status Queue Head W */
GP = 0x4C, /* General Purpose R/W */
VPM = 0x50 /* VPI/VCI Mask W */
};
/* NICStAR commands issued to the CMD register */
/* Top 4 bits are command opcode, lower 28 are parameters. */
#define NS_CMD_NO_OPERATION 0x00000000
/* params always 0 */
#define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
/* b19{1=open,0=close} b18-2{SRAM addr} */
#define NS_CMD_WRITE_SRAM 0x40000000
/* b18-2{SRAM addr} b1-0{burst size} */
#define NS_CMD_READ_SRAM 0x50000000
/* b18-2{SRAM addr} */
#define NS_CMD_WRITE_FREEBUFQ 0x60000000
/* b0{large buf indicator} */
#define NS_CMD_READ_UTILITY 0x80000000
/* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
#define NS_CMD_WRITE_UTILITY 0x90000000
/* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
#define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
#define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
/* NICStAR configuration bits */
#define NS_CFG_SWRST 0x80000000 /* Software Reset */
#define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */
#define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */
#define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */
#define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue
Interrupt Enable */
#define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */
#define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */
#define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */
#define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */
#define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */
#define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */
#define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt
Handling */
#define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */
#define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full
Interrupt Enable */
#define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */
#define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt
Enable */
#define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
#define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt
Enable */
#define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt
Enable */
#define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */
#define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full
Interrupt Enable */
#define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
#define NS_CFG_SMBUFSIZE_48 0x00000000
#define NS_CFG_SMBUFSIZE_96 0x08000000
#define NS_CFG_SMBUFSIZE_240 0x10000000
#define NS_CFG_SMBUFSIZE_2048 0x18000000
#define NS_CFG_LGBUFSIZE_2048 0x00000000
#define NS_CFG_LGBUFSIZE_4096 0x02000000
#define NS_CFG_LGBUFSIZE_8192 0x04000000
#define NS_CFG_LGBUFSIZE_16384 0x06000000
#define NS_CFG_RSQSIZE_2048 0x00000000
#define NS_CFG_RSQSIZE_4096 0x00400000
#define NS_CFG_RSQSIZE_8192 0x00800000
#define NS_CFG_VPIBITS_0 0x00000000
#define NS_CFG_VPIBITS_1 0x00040000
#define NS_CFG_VPIBITS_2 0x00080000
#define NS_CFG_VPIBITS_8 0x000C0000
#define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000
#define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000
#define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
#define NS_CFG_RXINT_NOINT 0x00000000
#define NS_CFG_RXINT_NODELAY 0x00001000
#define NS_CFG_RXINT_314US 0x00002000
#define NS_CFG_RXINT_624US 0x00003000
#define NS_CFG_RXINT_899US 0x00004000
/* NICStAR STATus bits */
#define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */
#define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */
#define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */
#define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */
#define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */
#define NS_STAT_TMROF 0x00000800 /* Timer Overflow */
#define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */
#define NS_STAT_CMDBZ 0x00000200 /* Command Busy */
#define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */
#define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */
#define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */
#define NS_STAT_EOPDU 0x00000020 /* End of PDU */
#define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
#define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */
#define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */
#define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */
#define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
#define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
/* #defines which depend on other #defines */
#define NS_TST0 NS_TST_FRSCD
#define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
#define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)
#define NS_FRSCD_SIZE 12 /* 12 dwords */
#define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
#if (NS_SMBUFSIZE == 48)
#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48
#elif (NS_SMBUFSIZE == 96)
#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96
#elif (NS_SMBUFSIZE == 240)
#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240
#elif (NS_SMBUFSIZE == 2048)
#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048
#else
#error NS_SMBUFSIZE is incorrect in nicstar.h
#endif /* NS_SMBUFSIZE */
#if (NS_LGBUFSIZE == 2048)
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
#elif (NS_LGBUFSIZE == 4096)
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
#elif (NS_LGBUFSIZE == 8192)
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
#elif (NS_LGBUFSIZE == 16384)
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
#else
#error NS_LGBUFSIZE is incorrect in nicstar.h
#endif /* NS_LGBUFSIZE */
#if (NS_RSQSIZE == 2048)
#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048
#elif (NS_RSQSIZE == 4096)
#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096
#elif (NS_RSQSIZE == 8192)
#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192
#else
#error NS_RSQSIZE is incorrect in nicstar.h
#endif /* NS_RSQSIZE */
#if (NS_VPIBITS == 0)
#define NS_CFG_VPIBITS NS_CFG_VPIBITS_0
#elif (NS_VPIBITS == 1)
#define NS_CFG_VPIBITS NS_CFG_VPIBITS_1
#elif (NS_VPIBITS == 2)
#define NS_CFG_VPIBITS NS_CFG_VPIBITS_2
#elif (NS_VPIBITS == 8)
#define NS_CFG_VPIBITS NS_CFG_VPIBITS_8
#else
#error NS_VPIBITS is incorrect in nicstar.h
#endif /* NS_VPIBITS */
#ifdef RCQ_SUPPORT
#define NS_CFG_RAWIE_OPT NS_CFG_RAWIE
#else
#define NS_CFG_RAWIE_OPT 0x00000000
#endif /* RCQ_SUPPORT */
#ifdef ENABLE_TSQFIE
#define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE
#else
#define NS_CFG_TSQFIE_OPT 0x00000000
#endif /* ENABLE_TSQFIE */
/* PCI stuff */
#ifndef PCI_VENDOR_ID_IDT
#define PCI_VENDOR_ID_IDT 0x111D
#endif /* PCI_VENDOR_ID_IDT */
#ifndef PCI_DEVICE_ID_IDT_IDT77201
#define PCI_DEVICE_ID_IDT_IDT77201 0x0001
#endif /* PCI_DEVICE_ID_IDT_IDT77201 */
/* Device driver structures */
struct ns_skb_prv {
u32 buf_type; /* BUF_SM/BUF_LG/BUF_NONE */
u32 dma;
int iovcnt;
};
#define NS_PRV_BUFTYPE(skb) \
(((struct ns_skb_prv *)(ATM_SKB(skb)+1))->buf_type)
#define NS_PRV_DMA(skb) \
(((struct ns_skb_prv *)(ATM_SKB(skb)+1))->dma)
#define NS_PRV_IOVCNT(skb) \
(((struct ns_skb_prv *)(ATM_SKB(skb)+1))->iovcnt)
typedef struct tsq_info {
void *org;
dma_addr_t dma;
ns_tsi *base;
ns_tsi *next;
ns_tsi *last;
} tsq_info;
typedef struct scq_info {
void *org;
dma_addr_t dma;
ns_scqe *base;
ns_scqe *last;
ns_scqe *next;
volatile ns_scqe *tail; /* Not related to the nicstar register */
unsigned num_entries;
struct sk_buff **skb; /* Pointer to an array of pointers
to the sk_buffs used for tx */
u32 scd; /* SRAM address of the corresponding
SCD */
int tbd_count; /* Only meaningful on variable rate */
wait_queue_head_t scqfull_waitq;
volatile char full; /* SCQ full indicator */
spinlock_t lock; /* SCQ spinlock */
} scq_info;
typedef struct rsq_info {
void *org;
dma_addr_t dma;
ns_rsqe *base;
ns_rsqe *next;
ns_rsqe *last;
} rsq_info;
typedef struct skb_pool {
volatile int count; /* number of buffers in the queue */
struct sk_buff_head queue;
} skb_pool;
/* NOTE: for small and large buffer pools, the count is not used, as the
actual value used for buffer management is the one read from the
card. */
typedef struct vc_map {
volatile unsigned int tx:1; /* TX vc? */
volatile unsigned int rx:1; /* RX vc? */
struct atm_vcc *tx_vcc, *rx_vcc;
struct sk_buff *rx_iov; /* RX iovector skb */
scq_info *scq; /* To keep track of the SCQ */
u32 cbr_scd; /* SRAM address of the corresponding
SCD. 0x00000000 for UBR/VBR/ABR */
int tbd_count;
} vc_map;
typedef struct ns_dev {
int index; /* Card ID to the device driver */
int sram_size; /* In k x 32bit words. 32 or 128 */
void __iomem *membase; /* Card's memory base address */
unsigned long max_pcr;
int rct_size; /* Number of entries */
int vpibits;
int vcibits;
struct pci_dev *pcidev;
struct idr idr;
struct atm_dev *atmdev;
tsq_info tsq;
rsq_info rsq;
scq_info *scq0, *scq1, *scq2; /* VBR SCQs */
skb_pool sbpool; /* Small buffers */
skb_pool lbpool; /* Large buffers */
skb_pool hbpool; /* Pre-allocated huge buffers */
skb_pool iovpool; /* iovector buffers */
volatile int efbie; /* Empty free buf. queue int. enabled */
volatile u32 tst_addr; /* SRAM address of the TST in use */
volatile int tst_free_entries;
vc_map vcmap[NS_MAX_RCTSIZE];
vc_map *tste2vc[NS_TST_NUM_ENTRIES];
vc_map *scd2vc[NS_FRSCD_NUM];
buf_nr sbnr;
buf_nr lbnr;
buf_nr hbnr;
buf_nr iovnr;
int sbfqc;
int lbfqc;
struct sk_buff *sm_handle;
u32 sm_addr;
struct sk_buff *lg_handle;
u32 lg_addr;
struct sk_buff *rcbuf; /* Current raw cell buffer */
struct ns_rcqe *rawcell;
u32 rawch; /* Raw cell queue head */
unsigned intcnt; /* Interrupt counter */
spinlock_t int_lock; /* Interrupt lock */
spinlock_t res_lock; /* Card resource lock */
} ns_dev;
/* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
CBR vc. If the entry is not allocated, it must be NULL.
There are two TSTs so the driver can modify them on the fly
without stopping the transmission.
scd2vc allows us to find out unused fixed rate SCDs, because
they must have a NULL pointer here. */
#endif /* _LINUX_NICSTAR_H_ */

244
drivers/atm/nicstarmac.c
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@ -1,244 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* this file included by nicstar.c
*/
/*
* nicstarmac.c
* Read this ForeRunner's MAC address from eprom/eeprom
*/
#include <linux/kernel.h>
typedef void __iomem *virt_addr_t;
#define CYCLE_DELAY 5
#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \
udelay((useconds));}
/*
* The following tables represent the timing diagrams found in
* the Data Sheet for the Xicor X25020 EEProm. The #defines below
* represent the bits in the NICStAR's General Purpose register
* that must be toggled for the corresponding actions on the EEProm
* to occur.
*/
/* Write Data To EEProm from SI line on rising edge of CLK */
/* Read Data From EEProm on falling edge of CLK */
#define CS_HIGH 0x0002 /* Chip select high */
#define CS_LOW 0x0000 /* Chip select low (active low) */
#define CLK_HIGH 0x0004 /* Clock high */
#define CLK_LOW 0x0000 /* Clock low */
#define SI_HIGH 0x0001 /* Serial input data high */
#define SI_LOW 0x0000 /* Serial input data low */
/* Read Status Register = 0000 0101b */
#if 0
static u_int32_t rdsrtab[] = {
CS_HIGH | CLK_HIGH,
CS_LOW | CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW | SI_HIGH,
CLK_HIGH | SI_HIGH, /* 1 */
CLK_LOW | SI_LOW,
CLK_HIGH, /* 0 */
CLK_LOW | SI_HIGH,
CLK_HIGH | SI_HIGH /* 1 */
};
#endif /* 0 */
/* Read from EEPROM = 0000 0011b */
static u_int32_t readtab[] = {
/*
CS_HIGH | CLK_HIGH,
*/
CS_LOW | CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW | SI_HIGH,
CLK_HIGH | SI_HIGH, /* 1 */
CLK_LOW | SI_HIGH,
CLK_HIGH | SI_HIGH /* 1 */
};
/* Clock to read from/write to the eeprom */
static u_int32_t clocktab[] = {
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW
};
#define NICSTAR_REG_WRITE(bs, reg, val) \
while ( readl(bs + STAT) & 0x0200 ) ; \
writel((val),(base)+(reg))
#define NICSTAR_REG_READ(bs, reg) \
readl((base)+(reg))
#define NICSTAR_REG_GENERAL_PURPOSE GP
/*
* This routine will clock the Read_Status_reg function into the X2520
* eeprom, then pull the result from bit 16 of the NicSTaR's General Purpose
* register.
*/
#if 0
u_int32_t nicstar_read_eprom_status(virt_addr_t base)
{
u_int32_t val;
u_int32_t rbyte;
int32_t i, j;
/* Send read instruction */
val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | rdsrtab[i]));
osp_MicroDelay(CYCLE_DELAY);
}
/* Done sending instruction - now pull data off of bit 16, MSB first */
/* Data clocked out of eeprom on falling edge of clock */
rbyte = 0;
for (i = 7, j = 0; i >= 0; i--) {
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++]));
rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
& 0x00010000) >> 16) << i);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++]));
osp_MicroDelay(CYCLE_DELAY);
}
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
osp_MicroDelay(CYCLE_DELAY);
return rbyte;
}
#endif /* 0 */
/*
* This routine will clock the Read_data function into the X2520
* eeprom, followed by the address to read from, through the NicSTaR's General
* Purpose register.
*/
static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset)
{
u_int32_t val = 0;
int i, j = 0;
u_int8_t tempread = 0;
val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
/* Send READ instruction */
for (i = 0; i < ARRAY_SIZE(readtab); i++) {
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | readtab[i]));
osp_MicroDelay(CYCLE_DELAY);
}
/* Next, we need to send the byte address to read from */
for (i = 7; i >= 0; i--) {
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++] | ((offset >> i) & 1)));
osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++] | ((offset >> i) & 1)));
osp_MicroDelay(CYCLE_DELAY);
}
j = 0;
/* Now, we can read data from the eeprom by clocking it in */
for (i = 7; i >= 0; i--) {
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++]));
osp_MicroDelay(CYCLE_DELAY);
tempread |=
(((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
& 0x00010000) >> 16) << i);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++]));
osp_MicroDelay(CYCLE_DELAY);
}
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
osp_MicroDelay(CYCLE_DELAY);
return tempread;
}
static void nicstar_init_eprom(virt_addr_t base)
{
u_int32_t val;
/*
* turn chip select off
*/
val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | CS_HIGH | CLK_HIGH));
osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | CS_HIGH | CLK_LOW));
osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | CS_HIGH | CLK_HIGH));
osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | CS_HIGH | CLK_LOW));
osp_MicroDelay(CYCLE_DELAY);
}
/*
* This routine will be the interface to the ReadPromByte function
* above.
*/
static void
nicstar_read_eprom(virt_addr_t base,
u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes)
{
u_int i;
for (i = 0; i < nbytes; i++) {
buffer[i] = read_eprom_byte(base, prom_offset);
++prom_offset;
osp_MicroDelay(CYCLE_DELAY);
}
}

61
drivers/atm/nicstarmac.copyright
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/* nicstar.c v0.22 Jawaid Bazyar (bazyar@hypermall.com)
* nicstar.c, M. Welsh (matt.welsh@cl.cam.ac.uk)
*
* Hacked October, 1997 by Jawaid Bazyar, Interlink Advertising Services Inc.
* http://www.hypermall.com/
* 10/1/97 - commented out CFG_PHYIE bit - we don't care when the PHY
* interrupts us (except possibly for removal/insertion of the cable?)
* 10/4/97 - began heavy inline documentation of the code. Corrected typos
* and spelling mistakes.
* 10/5/97 - added code to handle PHY interrupts, disable PHY on
* loss of link, and correctly re-enable PHY when link is
* re-established. (put back CFG_PHYIE)
*
* Modified to work with the IDT7721 nicstar -- AAL5 (tested) only.
*
* R. D. Rechenmacher <ron@fnal.gov>, Aug. 6, 1997
*
* Linux driver for the IDT77201 NICStAR PCI ATM controller.
* PHY component is expected to be 155 Mbps S/UNI-Lite or IDT 77155;
* see init_nicstar() for PHY initialization to change this. This driver
* expects the Linux ATM stack to support scatter-gather lists
* (skb->atm.iovcnt != 0) for Rx skb's passed to vcc->push.
*
* Implementing minimal-copy of received data:
* IDT always receives data into a small buffer, then large buffers
* as needed. This means that data must always be copied to create
* the linear buffer needed by most non-ATM protocol stacks (e.g. IP)
* Fix is simple: make large buffers large enough to hold entire
* SDU, and leave <small_buffer_data> bytes empty at the start. Then
* copy small buffer contents to head of large buffer.
* Trick is to avoid fragmenting Linux, due to need for a lot of large
* buffers. This is done by 2 things:
* 1) skb->destructor / skb->atm.recycle_buffer
* combined, allow nicstar_free_rx_skb to be called to
* recycle large data buffers
* 2) skb_clone of received buffers
* See nicstar_free_rx_skb and linearize_buffer for implementation
* details.
*
*
*
* Copyright (c) 1996 University of Cambridge Computer Laboratory
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* M. Welsh, 6 July 1996
*
*
*/

391
drivers/atm/suni.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/atm/suni.c - S/UNI PHY driver
*
* Supports the following:
* PMC PM5346 S/UNI LITE
* PMC PM5350 S/UNI 155 ULTRA
* PMC PM5355 S/UNI 622
*/
/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
#include <linux/module.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/atmdev.h>
#include <linux/sonet.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/capability.h>
#include <linux/slab.h>
#include <asm/param.h>
#include <linux/uaccess.h>
#include <linux/atomic.h>
#include "suni.h"
#if 0
#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
#else
#define DPRINTK(format,args...)
#endif
#define PRIV(dev) ((struct suni_priv *) dev->phy_data)
#define PUT(val,reg) dev->ops->phy_put(dev,val,SUNI_##reg)
#define GET(reg) dev->ops->phy_get(dev,SUNI_##reg)
#define REG_CHANGE(mask,shift,value,reg) \
PUT((GET(reg) & ~(mask)) | ((value) << (shift)),reg)
static struct timer_list poll_timer;
static struct suni_priv *sunis = NULL;
static DEFINE_SPINLOCK(sunis_lock);
#define ADD_LIMITED(s,v) \
atomic_add((v),&stats->s); \
if (atomic_read(&stats->s) < 0) atomic_set(&stats->s,INT_MAX);
static void suni_hz(struct timer_list *timer)
{
struct suni_priv *walk;
struct atm_dev *dev;
struct k_sonet_stats *stats;
for (walk = sunis; walk; walk = walk->next) {
dev = walk->dev;
stats = &walk->sonet_stats;
PUT(0,MRI); /* latch counters */
udelay(1);
ADD_LIMITED(section_bip,(GET(RSOP_SBL) & 0xff) |
((GET(RSOP_SBM) & 0xff) << 8));
ADD_LIMITED(line_bip,(GET(RLOP_LBL) & 0xff) |
((GET(RLOP_LB) & 0xff) << 8) |
((GET(RLOP_LBM) & 0xf) << 16));
ADD_LIMITED(path_bip,(GET(RPOP_PBL) & 0xff) |
((GET(RPOP_PBM) & 0xff) << 8));
ADD_LIMITED(line_febe,(GET(RLOP_LFL) & 0xff) |
((GET(RLOP_LF) & 0xff) << 8) |
((GET(RLOP_LFM) & 0xf) << 16));
ADD_LIMITED(path_febe,(GET(RPOP_PFL) & 0xff) |
((GET(RPOP_PFM) & 0xff) << 8));
ADD_LIMITED(corr_hcs,GET(RACP_CHEC) & 0xff);
ADD_LIMITED(uncorr_hcs,GET(RACP_UHEC) & 0xff);
ADD_LIMITED(rx_cells,(GET(RACP_RCCL) & 0xff) |
((GET(RACP_RCC) & 0xff) << 8) |
((GET(RACP_RCCM) & 7) << 16));
ADD_LIMITED(tx_cells,(GET(TACP_TCCL) & 0xff) |
((GET(TACP_TCC) & 0xff) << 8) |
((GET(TACP_TCCM) & 7) << 16));
}
if (timer) mod_timer(&poll_timer,jiffies+HZ);
}
#undef ADD_LIMITED
static int fetch_stats(struct atm_dev *dev,struct sonet_stats __user *arg,int zero)
{
struct sonet_stats tmp;
int error = 0;
sonet_copy_stats(&PRIV(dev)->sonet_stats,&tmp);
if (arg) error = copy_to_user(arg,&tmp,sizeof(tmp));
if (zero && !error) sonet_subtract_stats(&PRIV(dev)->sonet_stats,&tmp);
return error ? -EFAULT : 0;
}
#define HANDLE_FLAG(flag,reg,bit) \
if (todo & flag) { \
if (set) PUT(GET(reg) | bit,reg); \
else PUT(GET(reg) & ~bit,reg); \
todo &= ~flag; \
}
static int change_diag(struct atm_dev *dev,void __user *arg,int set)
{
int todo;
if (get_user(todo,(int __user *)arg)) return -EFAULT;
HANDLE_FLAG(SONET_INS_SBIP,TSOP_DIAG,SUNI_TSOP_DIAG_DBIP8);
HANDLE_FLAG(SONET_INS_LBIP,TLOP_DIAG,SUNI_TLOP_DIAG_DBIP);
HANDLE_FLAG(SONET_INS_PBIP,TPOP_CD,SUNI_TPOP_DIAG_DB3);
HANDLE_FLAG(SONET_INS_FRAME,RSOP_CIE,SUNI_RSOP_CIE_FOOF);
HANDLE_FLAG(SONET_INS_LAIS,TSOP_CTRL,SUNI_TSOP_CTRL_LAIS);
HANDLE_FLAG(SONET_INS_PAIS,TPOP_CD,SUNI_TPOP_DIAG_PAIS);
HANDLE_FLAG(SONET_INS_LOS,TSOP_DIAG,SUNI_TSOP_DIAG_DLOS);
HANDLE_FLAG(SONET_INS_HCS,TACP_CS,SUNI_TACP_CS_DHCS);
return put_user(todo,(int __user *)arg) ? -EFAULT : 0;
}
#undef HANDLE_FLAG
static int get_diag(struct atm_dev *dev,void __user *arg)
{
int set;
set = 0;
if (GET(TSOP_DIAG) & SUNI_TSOP_DIAG_DBIP8) set |= SONET_INS_SBIP;
if (GET(TLOP_DIAG) & SUNI_TLOP_DIAG_DBIP) set |= SONET_INS_LBIP;
if (GET(TPOP_CD) & SUNI_TPOP_DIAG_DB3) set |= SONET_INS_PBIP;
/* SONET_INS_FRAME is one-shot only */
if (GET(TSOP_CTRL) & SUNI_TSOP_CTRL_LAIS) set |= SONET_INS_LAIS;
if (GET(TPOP_CD) & SUNI_TPOP_DIAG_PAIS) set |= SONET_INS_PAIS;
if (GET(TSOP_DIAG) & SUNI_TSOP_DIAG_DLOS) set |= SONET_INS_LOS;
if (GET(TACP_CS) & SUNI_TACP_CS_DHCS) set |= SONET_INS_HCS;
return put_user(set,(int __user *)arg) ? -EFAULT : 0;
}
static int set_loopback(struct atm_dev *dev,int mode)
{
unsigned char control;
int reg, dle, lle;
if (PRIV(dev)->type == SUNI_MRI_TYPE_PM5355) {
reg = SUNI_MCM;
dle = SUNI_MCM_DLE;
lle = SUNI_MCM_LLE;
} else {
reg = SUNI_MCT;
dle = SUNI_MCT_DLE;
lle = SUNI_MCT_LLE;
}
control = dev->ops->phy_get(dev, reg) & ~(dle | lle);
switch (mode) {
case ATM_LM_NONE:
break;
case ATM_LM_LOC_PHY:
control |= dle;
break;
case ATM_LM_RMT_PHY:
control |= lle;
break;
default:
return -EINVAL;
}
dev->ops->phy_put(dev, control, reg);
PRIV(dev)->loop_mode = mode;
return 0;
}
/*
* SONET vs. SDH Configuration
*
* Z0INS (register 0x06): 0 for SONET, 1 for SDH
* ENSS (register 0x3D): 0 for SONET, 1 for SDH
* LEN16 (register 0x28): 0 for SONET, 1 for SDH (n/a for S/UNI 155 QUAD)
* LEN16 (register 0x50): 0 for SONET, 1 for SDH (n/a for S/UNI 155 QUAD)
* S[1:0] (register 0x46): 00 for SONET, 10 for SDH
*/
static int set_sonet(struct atm_dev *dev)
{
if (PRIV(dev)->type == SUNI_MRI_TYPE_PM5355) {
PUT(GET(RPOP_RC) & ~SUNI_RPOP_RC_ENSS, RPOP_RC);
PUT(GET(SSTB_CTRL) & ~SUNI_SSTB_CTRL_LEN16, SSTB_CTRL);
PUT(GET(SPTB_CTRL) & ~SUNI_SPTB_CTRL_LEN16, SPTB_CTRL);
}
REG_CHANGE(SUNI_TPOP_APM_S, SUNI_TPOP_APM_S_SHIFT,
SUNI_TPOP_S_SONET, TPOP_APM);
return 0;
}
static int set_sdh(struct atm_dev *dev)
{
if (PRIV(dev)->type == SUNI_MRI_TYPE_PM5355) {
PUT(GET(RPOP_RC) | SUNI_RPOP_RC_ENSS, RPOP_RC);
PUT(GET(SSTB_CTRL) | SUNI_SSTB_CTRL_LEN16, SSTB_CTRL);
PUT(GET(SPTB_CTRL) | SUNI_SPTB_CTRL_LEN16, SPTB_CTRL);
}
REG_CHANGE(SUNI_TPOP_APM_S, SUNI_TPOP_APM_S_SHIFT,
SUNI_TPOP_S_SDH, TPOP_APM);
return 0;
}
static int get_framing(struct atm_dev *dev, void __user *arg)
{
int framing;
unsigned char s;
s = (GET(TPOP_APM) & SUNI_TPOP_APM_S) >> SUNI_TPOP_APM_S_SHIFT;
if (s == SUNI_TPOP_S_SONET)
framing = SONET_FRAME_SONET;
else
framing = SONET_FRAME_SDH;
return put_user(framing, (int __user *) arg) ? -EFAULT : 0;
}
static int set_framing(struct atm_dev *dev, void __user *arg)
{
int mode;
if (get_user(mode, (int __user *) arg))
return -EFAULT;
if (mode == SONET_FRAME_SONET)
return set_sonet(dev);
else if (mode == SONET_FRAME_SDH)
return set_sdh(dev);
return -EINVAL;
}
static int suni_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
{
switch (cmd) {
case SONET_GETSTATZ:
case SONET_GETSTAT:
return fetch_stats(dev, arg, cmd == SONET_GETSTATZ);
case SONET_SETDIAG:
return change_diag(dev,arg,1);
case SONET_CLRDIAG:
return change_diag(dev,arg,0);
case SONET_GETDIAG:
return get_diag(dev,arg);
case SONET_SETFRAMING:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
return set_framing(dev, arg);
case SONET_GETFRAMING:
return get_framing(dev, arg);
case SONET_GETFRSENSE:
return -EINVAL;
case ATM_SETLOOP:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
return set_loopback(dev,(int)(unsigned long)arg);
case ATM_GETLOOP:
return put_user(PRIV(dev)->loop_mode,(int __user *)arg) ?
-EFAULT : 0;
case ATM_QUERYLOOP:
return put_user(ATM_LM_LOC_PHY | ATM_LM_RMT_PHY,
(int __user *) arg) ? -EFAULT : 0;
default:
return -ENOIOCTLCMD;
}
}
static void poll_los(struct atm_dev *dev)
{
atm_dev_signal_change(dev,
GET(RSOP_SIS) & SUNI_RSOP_SIS_LOSV ?
ATM_PHY_SIG_LOST : ATM_PHY_SIG_FOUND);
}
static void suni_int(struct atm_dev *dev)
{
poll_los(dev);
printk(KERN_NOTICE "%s(itf %d): signal %s\n",dev->type,dev->number,
dev->signal == ATM_PHY_SIG_LOST ? "lost" : "detected again");
}
static int suni_start(struct atm_dev *dev)
{
unsigned long flags;
int first;
spin_lock_irqsave(&sunis_lock,flags);
first = !sunis;
PRIV(dev)->next = sunis;
sunis = PRIV(dev);
spin_unlock_irqrestore(&sunis_lock,flags);
memset(&PRIV(dev)->sonet_stats,0,sizeof(struct k_sonet_stats));
PUT(GET(RSOP_CIE) | SUNI_RSOP_CIE_LOSE,RSOP_CIE);
/* interrupt on loss of signal */
poll_los(dev); /* ... and clear SUNI interrupts */
if (dev->signal == ATM_PHY_SIG_LOST)
printk(KERN_WARNING "%s(itf %d): no signal\n",dev->type,
dev->number);
PRIV(dev)->loop_mode = ATM_LM_NONE;
suni_hz(NULL); /* clear SUNI counters */
(void) fetch_stats(dev,NULL,1); /* clear kernel counters */
if (first) {
timer_setup(&poll_timer, suni_hz, 0);
poll_timer.expires = jiffies+HZ;
#if 0
printk(KERN_DEBUG "[u] p=0x%lx,n=0x%lx\n",(unsigned long) poll_timer.list.prev,
(unsigned long) poll_timer.list.next);
#endif
add_timer(&poll_timer);
}
return 0;
}
static int suni_stop(struct atm_dev *dev)
{
struct suni_priv **walk;
unsigned long flags;
/* let SAR driver worry about stopping interrupts */
spin_lock_irqsave(&sunis_lock,flags);
for (walk = &sunis; *walk != PRIV(dev);
walk = &PRIV((*walk)->dev)->next);
*walk = PRIV((*walk)->dev)->next;
if (!sunis) timer_delete_sync(&poll_timer);
spin_unlock_irqrestore(&sunis_lock,flags);
kfree(PRIV(dev));
return 0;
}
static const struct atmphy_ops suni_ops = {
.start = suni_start,
.ioctl = suni_ioctl,
.interrupt = suni_int,
.stop = suni_stop,
};
int suni_init(struct atm_dev *dev)
{
unsigned char mri;
if (!(dev->phy_data = kmalloc_obj(struct suni_priv)))
return -ENOMEM;
PRIV(dev)->dev = dev;
mri = GET(MRI); /* reset SUNI */
PRIV(dev)->type = (mri & SUNI_MRI_TYPE) >> SUNI_MRI_TYPE_SHIFT;
PUT(mri | SUNI_MRI_RESET,MRI);
PUT(mri,MRI);
PUT((GET(MT) & SUNI_MT_DS27_53),MT); /* disable all tests */
set_sonet(dev);
REG_CHANGE(SUNI_TACP_IUCHP_CLP,0,SUNI_TACP_IUCHP_CLP,
TACP_IUCHP); /* idle cells */
PUT(SUNI_IDLE_PATTERN,TACP_IUCPOP);
dev->phy = &suni_ops;
return 0;
}
EXPORT_SYMBOL(suni_init);
MODULE_DESCRIPTION("S/UNI PHY driver");
MODULE_LICENSE("GPL");

242
drivers/atm/suni.h
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@ -1,242 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* drivers/atm/suni.h - S/UNI PHY driver
*/
/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
#ifndef DRIVER_ATM_SUNI_H
#define DRIVER_ATM_SUNI_H
#include <linux/atmdev.h>
#include <linux/atmioc.h>
#include <linux/sonet.h>
/* SUNI registers */
#define SUNI_MRI 0x00 /* Master Reset and Identity / Load
Meter */
#define SUNI_MC 0x01 /* Master Configuration */
#define SUNI_MIS 0x02 /* Master Interrupt Status */
/* no 0x03 */
#define SUNI_MCM 0x04 /* Master Clock Monitor */
#define SUNI_MCT 0x05 /* Master Control */
#define SUNI_CSCS 0x06 /* Clock Synthesis Control and Status */
#define SUNI_CRCS 0x07 /* Clock Recovery Control and Status */
/* 0x08-0x0F reserved */
#define SUNI_RSOP_CIE 0x10 /* RSOP Control/Interrupt Enable */
#define SUNI_RSOP_SIS 0x11 /* RSOP Status/Interrupt Status */
#define SUNI_RSOP_SBL 0x12 /* RSOP Section BIP-8 LSB */
#define SUNI_RSOP_SBM 0x13 /* RSOP Section BIP-8 MSB */
#define SUNI_TSOP_CTRL 0x14 /* TSOP Control */
#define SUNI_TSOP_DIAG 0x15 /* TSOP Diagnostic */
/* 0x16-0x17 reserved */
#define SUNI_RLOP_CS 0x18 /* RLOP Control/Status */
#define SUNI_RLOP_IES 0x19 /* RLOP Interrupt Enable/Status */
#define SUNI_RLOP_LBL 0x1A /* RLOP Line BIP-8/24 LSB */
#define SUNI_RLOP_LB 0x1B /* RLOP Line BIP-8/24 */
#define SUNI_RLOP_LBM 0x1C /* RLOP Line BIP-8/24 MSB */
#define SUNI_RLOP_LFL 0x1D /* RLOP Line FEBE LSB */
#define SUNI_RLOP_LF 0x1E /* RLOP Line FEBE */
#define SUNI_RLOP_LFM 0x1F /* RLOP Line FEBE MSB */
#define SUNI_TLOP_CTRL 0x20 /* TLOP Control */
#define SUNI_TLOP_DIAG 0x21 /* TLOP Diagnostic */
/* 0x22-0x27 reserved */
#define SUNI_SSTB_CTRL 0x28
#define SUNI_RPOP_SC 0x30 /* RPOP Status/Control */
#define SUNI_RPOP_IS 0x31 /* RPOP Interrupt Status */
/* 0x32 reserved */
#define SUNI_RPOP_IE 0x33 /* RPOP Interrupt Enable */
/* 0x34-0x36 reserved */
#define SUNI_RPOP_PSL 0x37 /* RPOP Path Signal Label */
#define SUNI_RPOP_PBL 0x38 /* RPOP Path BIP-8 LSB */
#define SUNI_RPOP_PBM 0x39 /* RPOP Path BIP-8 MSB */
#define SUNI_RPOP_PFL 0x3A /* RPOP Path FEBE LSB */
#define SUNI_RPOP_PFM 0x3B /* RPOP Path FEBE MSB */
/* 0x3C reserved */
#define SUNI_RPOP_PBC 0x3D /* RPOP Path BIP-8 Configuration */
#define SUNI_RPOP_RC 0x3D /* RPOP Ring Control (PM5355) */
/* 0x3E-0x3F reserved */
#define SUNI_TPOP_CD 0x40 /* TPOP Control/Diagnostic */
#define SUNI_TPOP_PC 0x41 /* TPOP Pointer Control */
/* 0x42-0x44 reserved */
#define SUNI_TPOP_APL 0x45 /* TPOP Arbitrary Pointer LSB */
#define SUNI_TPOP_APM 0x46 /* TPOP Arbitrary Pointer MSB */
/* 0x47 reserved */
#define SUNI_TPOP_PSL 0x48 /* TPOP Path Signal Label */
#define SUNI_TPOP_PS 0x49 /* TPOP Path Status */
/* 0x4A-0x4F reserved */
#define SUNI_RACP_CS 0x50 /* RACP Control/Status */
#define SUNI_RACP_IES 0x51 /* RACP Interrupt Enable/Status */
#define SUNI_RACP_MHP 0x52 /* RACP Match Header Pattern */
#define SUNI_RACP_MHM 0x53 /* RACP Match Header Mask */
#define SUNI_RACP_CHEC 0x54 /* RACP Correctable HCS Error Count */
#define SUNI_RACP_UHEC 0x55 /* RACP Uncorrectable HCS Err Count */
#define SUNI_RACP_RCCL 0x56 /* RACP Receive Cell Counter LSB */
#define SUNI_RACP_RCC 0x57 /* RACP Receive Cell Counter */
#define SUNI_RACP_RCCM 0x58 /* RACP Receive Cell Counter MSB */
#define SUNI_RACP_CFG 0x59 /* RACP Configuration */
/* 0x5A-0x5F reserved */
#define SUNI_TACP_CS 0x60 /* TACP Control/Status */
#define SUNI_TACP_IUCHP 0x61 /* TACP Idle/Unassigned Cell Hdr Pat */
#define SUNI_TACP_IUCPOP 0x62 /* TACP Idle/Unassigned Cell Payload
Octet Pattern */
#define SUNI_TACP_FIFO 0x63 /* TACP FIFO Configuration */
#define SUNI_TACP_TCCL 0x64 /* TACP Transmit Cell Counter LSB */
#define SUNI_TACP_TCC 0x65 /* TACP Transmit Cell Counter */
#define SUNI_TACP_TCCM 0x66 /* TACP Transmit Cell Counter MSB */
#define SUNI_TACP_CFG 0x67 /* TACP Configuration */
#define SUNI_SPTB_CTRL 0x68 /* SPTB Control */
/* 0x69-0x7F reserved */
#define SUNI_MT 0x80 /* Master Test */
/* 0x81-0xFF reserved */
/* SUNI register values */
/* MRI is reg 0 */
#define SUNI_MRI_ID 0x0f /* R, SUNI revision number */
#define SUNI_MRI_ID_SHIFT 0
#define SUNI_MRI_TYPE 0x70 /* R, SUNI type (lite is 011) */
#define SUNI_MRI_TYPE_SHIFT 4
#define SUNI_MRI_TYPE_PM5346 0x3 /* S/UNI 155 LITE */
#define SUNI_MRI_TYPE_PM5347 0x4 /* S/UNI 155 PLUS */
#define SUNI_MRI_TYPE_PM5350 0x7 /* S/UNI 155 ULTRA */
#define SUNI_MRI_TYPE_PM5355 0x1 /* S/UNI 622 */
#define SUNI_MRI_RESET 0x80 /* RW, reset & power down chip
0: normal operation
1: reset & low power */
/* MCM is reg 0x4 */
#define SUNI_MCM_LLE 0x20 /* line loopback (PM5355) */
#define SUNI_MCM_DLE 0x10 /* diagnostic loopback (PM5355) */
/* MCT is reg 5 */
#define SUNI_MCT_LOOPT 0x01 /* RW, timing source, 0: from
TRCLK+/- */
#define SUNI_MCT_DLE 0x02 /* RW, diagnostic loopback */
#define SUNI_MCT_LLE 0x04 /* RW, line loopback */
#define SUNI_MCT_FIXPTR 0x20 /* RW, disable transmit payload pointer
adjustments
0: payload ptr controlled by TPOP
ptr control reg
1: payload pointer fixed at 522 */
#define SUNI_MCT_LCDV 0x40 /* R, loss of cell delineation */
#define SUNI_MCT_LCDE 0x80 /* RW, loss of cell delineation
interrupt (1: on) */
/* RSOP_CIE is reg 0x10 */
#define SUNI_RSOP_CIE_OOFE 0x01 /* RW, enable interrupt on frame alarm
state change */
#define SUNI_RSOP_CIE_LOFE 0x02 /* RW, enable interrupt on loss of
frame state change */
#define SUNI_RSOP_CIE_LOSE 0x04 /* RW, enable interrupt on loss of
signal state change */
#define SUNI_RSOP_CIE_BIPEE 0x08 /* RW, enable interrupt on section
BIP-8 error (B1) */
#define SUNI_RSOP_CIE_FOOF 0x20 /* W, force RSOP out of frame at next
boundary */
#define SUNI_RSOP_CIE_DDS 0x40 /* RW, disable scrambling */
/* RSOP_SIS is reg 0x11 */
#define SUNI_RSOP_SIS_OOFV 0x01 /* R, out of frame */
#define SUNI_RSOP_SIS_LOFV 0x02 /* R, loss of frame */
#define SUNI_RSOP_SIS_LOSV 0x04 /* R, loss of signal */
#define SUNI_RSOP_SIS_OOFI 0x08 /* R, out of frame interrupt */
#define SUNI_RSOP_SIS_LOFI 0x10 /* R, loss of frame interrupt */
#define SUNI_RSOP_SIS_LOSI 0x20 /* R, loss of signal interrupt */
#define SUNI_RSOP_SIS_BIPEI 0x40 /* R, section BIP-8 interrupt */
/* TSOP_CTRL is reg 0x14 */
#define SUNI_TSOP_CTRL_LAIS 0x01 /* insert alarm indication signal */
#define SUNI_TSOP_CTRL_DS 0x40 /* disable scrambling */
/* TSOP_DIAG is reg 0x15 */
#define SUNI_TSOP_DIAG_DFP 0x01 /* insert single bit error cont. */
#define SUNI_TSOP_DIAG_DBIP8 0x02 /* insert section BIP err (cont) */
#define SUNI_TSOP_DIAG_DLOS 0x04 /* set line to zero (loss of signal) */
/* TLOP_DIAG is reg 0x21 */
#define SUNI_TLOP_DIAG_DBIP 0x01 /* insert line BIP err (continuously) */
/* SSTB_CTRL is reg 0x28 */
#define SUNI_SSTB_CTRL_LEN16 0x01 /* path trace message length bit */
/* RPOP_RC is reg 0x3D (PM5355) */
#define SUNI_RPOP_RC_ENSS 0x40 /* enable size bit */
/* TPOP_DIAG is reg 0x40 */
#define SUNI_TPOP_DIAG_PAIS 0x01 /* insert STS path alarm ind (cont) */
#define SUNI_TPOP_DIAG_DB3 0x02 /* insert path BIP err (continuously) */
/* TPOP_APM is reg 0x46 */
#define SUNI_TPOP_APM_APTR 0x03 /* RW, arbitrary pointer, upper 2
bits */
#define SUNI_TPOP_APM_APTR_SHIFT 0
#define SUNI_TPOP_APM_S 0x0c /* RW, "unused" bits of payload
pointer */
#define SUNI_TPOP_APM_S_SHIFT 2
#define SUNI_TPOP_APM_NDF 0xf0 /* RW, NDF bits */
#define SUNI_TPOP_APM_NDF_SHIFT 4
#define SUNI_TPOP_S_SONET 0 /* set S bits to 00 */
#define SUNI_TPOP_S_SDH 2 /* set S bits to 10 */
/* RACP_IES is reg 0x51 */
#define SUNI_RACP_IES_FOVRI 0x02 /* R, FIFO overrun */
#define SUNI_RACP_IES_UHCSI 0x04 /* R, uncorrectable HCS error */
#define SUNI_RACP_IES_CHCSI 0x08 /* R, correctable HCS error */
#define SUNI_RACP_IES_OOCDI 0x10 /* R, change of cell delineation
state */
#define SUNI_RACP_IES_FIFOE 0x20 /* RW, enable FIFO overrun interrupt */
#define SUNI_RACP_IES_HCSE 0x40 /* RW, enable HCS error interrupt */
#define SUNI_RACP_IES_OOCDE 0x80 /* RW, enable cell delineation state
change interrupt */
/* TACP_CS is reg 0x60 */
#define SUNI_TACP_CS_FIFORST 0x01 /* RW, reset transmit FIFO (sticky) */
#define SUNI_TACP_CS_DSCR 0x02 /* RW, disable payload scrambling */
#define SUNI_TACP_CS_HCAADD 0x04 /* RW, add coset polynomial to HCS */
#define SUNI_TACP_CS_DHCS 0x10 /* RW, insert HCS errors */
#define SUNI_TACP_CS_FOVRI 0x20 /* R, FIFO overrun */
#define SUNI_TACP_CS_TSOCI 0x40 /* R, TSOC input high */
#define SUNI_TACP_CS_FIFOE 0x80 /* RW, enable FIFO overrun interrupt */
/* TACP_IUCHP is reg 0x61 */
#define SUNI_TACP_IUCHP_CLP 0x01 /* RW, 8th bit of 4th octet of i/u
pattern */
#define SUNI_TACP_IUCHP_PTI 0x0e /* RW, 5th-7th bits of 4th octet of i/u
pattern */
#define SUNI_TACP_IUCHP_PTI_SHIFT 1
#define SUNI_TACP_IUCHP_GFC 0xf0 /* RW, 1st-4th bits of 1st octet of i/u
pattern */
#define SUNI_TACP_IUCHP_GFC_SHIFT 4
/* SPTB_CTRL is reg 0x68 */
#define SUNI_SPTB_CTRL_LEN16 0x01 /* path trace message length */
/* MT is reg 0x80 */
#define SUNI_MT_HIZIO 0x01 /* RW, all but data bus & MP interface
tri-state */
#define SUNI_MT_HIZDATA 0x02 /* W, also tri-state data bus */
#define SUNI_MT_IOTST 0x04 /* RW, enable test mode */
#define SUNI_MT_DBCTRL 0x08 /* W, control data bus by CSB pin */
#define SUNI_MT_PMCTST 0x10 /* W, PMC test mode */
#define SUNI_MT_DS27_53 0x80 /* RW, select between 8- or 16- bit */
#define SUNI_IDLE_PATTERN 0x6a /* idle pattern */
#ifdef __KERNEL__
struct suni_priv {
struct k_sonet_stats sonet_stats; /* link diagnostics */
int loop_mode; /* loopback mode */
int type; /* phy type */
struct atm_dev *dev; /* device back-pointer */
struct suni_priv *next; /* next SUNI */
};
int suni_init(struct atm_dev *dev);
#endif
#endif

21
drivers/atm/tonga.h
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@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/tonga.h - Efficient Networks Tonga (PCI bridge) declarations */
/* Written 1995 by Werner Almesberger, EPFL LRC */
#ifndef DRIVER_ATM_TONGA_H
#define DRIVER_ATM_TONGA_H
#define PCI_TONGA_CTRL 0x60 /* control register */
#define END_SWAP_DMA 0x80 /* endian swap on DMA */
#define END_SWAP_BYTE 0x40 /* endian swap on slave byte accesses */
#define END_SWAP_WORD 0x20 /* endian swap on slave word accesses */
#define SEPROM_MAGIC 0x0c /* obscure required pattern (ASIC only) */
#define SEPROM_DATA 0x02 /* serial EEPROM data (ASIC only) */
#define SEPROM_CLK 0x01 /* serial EEPROM clock (ASIC only) */
#define SEPROM_ESI_BASE 64 /* start of ESI in serial EEPROM */
#endif

35
drivers/atm/zeprom.h
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@ -1,35 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/zeprom.h - ZeitNet ZN122x EEPROM (NM93C46) declarations */
/* Written 1995,1996 by Werner Almesberger, EPFL LRC */
#ifndef DRIVER_ATM_ZEPROM_H
#define DRIVER_ATM_ZEPROM_H
/* Different versions use different control registers */
#define ZEPROM_V1_REG PCI_VENDOR_ID /* PCI register */
#define ZEPROM_V2_REG 0x40
/* Bits in control register */
#define ZEPROM_SK 0x80000000 /* strobe (probably on raising edge) */
#define ZEPROM_CS 0x40000000 /* Chip Select */
#define ZEPROM_DI 0x20000000 /* Data Input */
#define ZEPROM_DO 0x10000000 /* Data Output */
#define ZEPROM_SIZE 32 /* 32 bytes */
#define ZEPROM_V1_ESI_OFF 24 /* ESI offset in EEPROM (V1) */
#define ZEPROM_V2_ESI_OFF 4 /* ESI offset in EEPROM (V2) */
#define ZEPROM_CMD_LEN 3 /* commands are three bits */
#define ZEPROM_ADDR_LEN 6 /* addresses are six bits */
/* Commands (3 bits) */
#define ZEPROM_CMD_READ 6
/* No other commands are needed. */
#endif

27
drivers/isdn/Kconfig
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@ -1,27 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# ISDN device configuration
#
menuconfig ISDN
bool "ISDN support"
depends on NET && NETDEVICES
help
ISDN ("Integrated Services Digital Network", called RNIS in France)
is a fully digital telephone service that can be used for voice and
data connections. If your computer is equipped with an ISDN
adapter you can use it to connect to your Internet service provider
(with SLIP or PPP) faster than via a conventional telephone modem
(though still much slower than with DSL) or to make and accept
voice calls (eg. turning your PC into a software answering machine
or PABX).
Select this option if you want your kernel to support ISDN.
if ISDN
source "drivers/isdn/capi/Kconfig"
source "drivers/isdn/mISDN/Kconfig"
endif # ISDN

8
drivers/isdn/Makefile
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@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for the kernel ISDN subsystem and device drivers.
# Object files in subdirectories
obj-$(CONFIG_BT_CMTP) += capi/
obj-$(CONFIG_MISDN) += mISDN/
obj-$(CONFIG_ISDN) += hardware/

32
drivers/isdn/capi/Kconfig
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@ -1,32 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
config ISDN_CAPI
def_bool ISDN && BT
help
This provides CAPI (the Common ISDN Application Programming
Interface) Version 2.0, a standard making it easy for programs to
access ISDN hardware in a device independent way. (For details see
<https://www.capi.org/>.) CAPI supports making and accepting voice
and data connections, controlling call options and protocols,
as well as ISDN supplementary services like call forwarding or
three-party conferences (if supported by the specific hardware
driver).
This subsystem requires a hardware specific driver.
See CONFIG_BT_CMTP for the last remaining regular driver
in the kernel that uses the CAPI subsystem.
config CAPI_TRACE
def_bool BT_CMTP
help
If you say Y here, the kernelcapi driver can make verbose traces
of CAPI messages. This feature can be enabled/disabled via IOCTL for
every controller (default disabled).
config ISDN_CAPI_MIDDLEWARE
def_bool BT_CMTP && TTY
help
This option will enhance the capabilities of the /dev/capi20
interface. It will provide a means of moving a data connection,
established via the usual /dev/capi20 interface to a special tty
device. If you want to use pppd with pppdcapiplugin to dial up to
your ISP, say Y here.

6
drivers/isdn/capi/Makefile
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@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for the CAPI subsystem used by BT_CMTP
obj-$(CONFIG_BT_CMTP) += kernelcapi.o
kernelcapi-y := kcapi.o capiutil.o capi.o
kernelcapi-$(CONFIG_PROC_FS) += kcapi_proc.o

1435
drivers/isdn/capi/capi.c
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File diff suppressed because it is too large Load Diff

677
drivers/isdn/capi/capiutil.c
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@ -1,677 +0,0 @@
/* $Id: capiutil.c,v 1.13.6.4 2001/09/23 22:24:33 kai Exp $
*
* CAPI 2.0 convert capi message to capi message struct
*
* From CAPI 2.0 Development Kit AVM 1995 (msg.c)
* Rewritten for Linux 1996 by Carsten Paeth <calle@calle.de>
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/isdn/capiutil.h>
#include <linux/slab.h>
#include "kcapi.h"
/* from CAPI2.0 DDK AVM Berlin GmbH */
typedef struct {
int typ;
size_t off;
} _cdef;
#define _CBYTE 1
#define _CWORD 2
#define _CDWORD 3
#define _CSTRUCT 4
#define _CMSTRUCT 5
#define _CEND 6
static _cdef cdef[] =
{
/*00 */
{_CEND},
/*01 */
{_CEND},
/*02 */
{_CEND},
/*03 */
{_CDWORD, offsetof(_cmsg, adr.adrController)},
/*04 */
{_CMSTRUCT, offsetof(_cmsg, AdditionalInfo)},
/*05 */
{_CSTRUCT, offsetof(_cmsg, B1configuration)},
/*06 */
{_CWORD, offsetof(_cmsg, B1protocol)},
/*07 */
{_CSTRUCT, offsetof(_cmsg, B2configuration)},
/*08 */
{_CWORD, offsetof(_cmsg, B2protocol)},
/*09 */
{_CSTRUCT, offsetof(_cmsg, B3configuration)},
/*0a */
{_CWORD, offsetof(_cmsg, B3protocol)},
/*0b */
{_CSTRUCT, offsetof(_cmsg, BC)},
/*0c */
{_CSTRUCT, offsetof(_cmsg, BChannelinformation)},
/*0d */
{_CMSTRUCT, offsetof(_cmsg, BProtocol)},
/*0e */
{_CSTRUCT, offsetof(_cmsg, CalledPartyNumber)},
/*0f */
{_CSTRUCT, offsetof(_cmsg, CalledPartySubaddress)},
/*10 */
{_CSTRUCT, offsetof(_cmsg, CallingPartyNumber)},
/*11 */
{_CSTRUCT, offsetof(_cmsg, CallingPartySubaddress)},
/*12 */
{_CDWORD, offsetof(_cmsg, CIPmask)},
/*13 */
{_CDWORD, offsetof(_cmsg, CIPmask2)},
/*14 */
{_CWORD, offsetof(_cmsg, CIPValue)},
/*15 */
{_CDWORD, offsetof(_cmsg, Class)},
/*16 */
{_CSTRUCT, offsetof(_cmsg, ConnectedNumber)},
/*17 */
{_CSTRUCT, offsetof(_cmsg, ConnectedSubaddress)},
/*18 */
{_CDWORD, offsetof(_cmsg, Data)},
/*19 */
{_CWORD, offsetof(_cmsg, DataHandle)},
/*1a */
{_CWORD, offsetof(_cmsg, DataLength)},
/*1b */
{_CSTRUCT, offsetof(_cmsg, FacilityConfirmationParameter)},
/*1c */
{_CSTRUCT, offsetof(_cmsg, Facilitydataarray)},
/*1d */
{_CSTRUCT, offsetof(_cmsg, FacilityIndicationParameter)},
/*1e */
{_CSTRUCT, offsetof(_cmsg, FacilityRequestParameter)},
/*1f */
{_CWORD, offsetof(_cmsg, FacilitySelector)},
/*20 */
{_CWORD, offsetof(_cmsg, Flags)},
/*21 */
{_CDWORD, offsetof(_cmsg, Function)},
/*22 */
{_CSTRUCT, offsetof(_cmsg, HLC)},
/*23 */
{_CWORD, offsetof(_cmsg, Info)},
/*24 */
{_CSTRUCT, offsetof(_cmsg, InfoElement)},
/*25 */
{_CDWORD, offsetof(_cmsg, InfoMask)},
/*26 */
{_CWORD, offsetof(_cmsg, InfoNumber)},
/*27 */
{_CSTRUCT, offsetof(_cmsg, Keypadfacility)},
/*28 */
{_CSTRUCT, offsetof(_cmsg, LLC)},
/*29 */
{_CSTRUCT, offsetof(_cmsg, ManuData)},
/*2a */
{_CDWORD, offsetof(_cmsg, ManuID)},
/*2b */
{_CSTRUCT, offsetof(_cmsg, NCPI)},
/*2c */
{_CWORD, offsetof(_cmsg, Reason)},
/*2d */
{_CWORD, offsetof(_cmsg, Reason_B3)},
/*2e */
{_CWORD, offsetof(_cmsg, Reject)},
/*2f */
{_CSTRUCT, offsetof(_cmsg, Useruserdata)}
};
static unsigned char *cpars[] =
{
/* ALERT_REQ */ [0x01] = "\x03\x04\x0c\x27\x2f\x1c\x01\x01",
/* CONNECT_REQ */ [0x02] = "\x03\x14\x0e\x10\x0f\x11\x0d\x06\x08\x0a\x05\x07\x09\x01\x0b\x28\x22\x04\x0c\x27\x2f\x1c\x01\x01",
/* DISCONNECT_REQ */ [0x04] = "\x03\x04\x0c\x27\x2f\x1c\x01\x01",
/* LISTEN_REQ */ [0x05] = "\x03\x25\x12\x13\x10\x11\x01",
/* INFO_REQ */ [0x08] = "\x03\x0e\x04\x0c\x27\x2f\x1c\x01\x01",
/* FACILITY_REQ */ [0x09] = "\x03\x1f\x1e\x01",
/* SELECT_B_PROTOCOL_REQ */ [0x0a] = "\x03\x0d\x06\x08\x0a\x05\x07\x09\x01\x01",
/* CONNECT_B3_REQ */ [0x0b] = "\x03\x2b\x01",
/* DISCONNECT_B3_REQ */ [0x0d] = "\x03\x2b\x01",
/* DATA_B3_REQ */ [0x0f] = "\x03\x18\x1a\x19\x20\x01",
/* RESET_B3_REQ */ [0x10] = "\x03\x2b\x01",
/* ALERT_CONF */ [0x13] = "\x03\x23\x01",
/* CONNECT_CONF */ [0x14] = "\x03\x23\x01",
/* DISCONNECT_CONF */ [0x16] = "\x03\x23\x01",
/* LISTEN_CONF */ [0x17] = "\x03\x23\x01",
/* MANUFACTURER_REQ */ [0x18] = "\x03\x2a\x15\x21\x29\x01",
/* INFO_CONF */ [0x1a] = "\x03\x23\x01",
/* FACILITY_CONF */ [0x1b] = "\x03\x23\x1f\x1b\x01",
/* SELECT_B_PROTOCOL_CONF */ [0x1c] = "\x03\x23\x01",
/* CONNECT_B3_CONF */ [0x1d] = "\x03\x23\x01",
/* DISCONNECT_B3_CONF */ [0x1f] = "\x03\x23\x01",
/* DATA_B3_CONF */ [0x21] = "\x03\x19\x23\x01",
/* RESET_B3_CONF */ [0x22] = "\x03\x23\x01",
/* CONNECT_IND */ [0x26] = "\x03\x14\x0e\x10\x0f\x11\x0b\x28\x22\x04\x0c\x27\x2f\x1c\x01\x01",
/* CONNECT_ACTIVE_IND */ [0x27] = "\x03\x16\x17\x28\x01",
/* DISCONNECT_IND */ [0x28] = "\x03\x2c\x01",
/* MANUFACTURER_CONF */ [0x2a] = "\x03\x2a\x15\x21\x29\x01",
/* INFO_IND */ [0x2c] = "\x03\x26\x24\x01",
/* FACILITY_IND */ [0x2d] = "\x03\x1f\x1d\x01",
/* CONNECT_B3_IND */ [0x2f] = "\x03\x2b\x01",
/* CONNECT_B3_ACTIVE_IND */ [0x30] = "\x03\x2b\x01",
/* DISCONNECT_B3_IND */ [0x31] = "\x03\x2d\x2b\x01",
/* DATA_B3_IND */ [0x33] = "\x03\x18\x1a\x19\x20\x01",
/* RESET_B3_IND */ [0x34] = "\x03\x2b\x01",
/* CONNECT_B3_T90_ACTIVE_IND */ [0x35] = "\x03\x2b\x01",
/* CONNECT_RESP */ [0x38] = "\x03\x2e\x0d\x06\x08\x0a\x05\x07\x09\x01\x16\x17\x28\x04\x0c\x27\x2f\x1c\x01\x01",
/* CONNECT_ACTIVE_RESP */ [0x39] = "\x03\x01",
/* DISCONNECT_RESP */ [0x3a] = "\x03\x01",
/* MANUFACTURER_IND */ [0x3c] = "\x03\x2a\x15\x21\x29\x01",
/* INFO_RESP */ [0x3e] = "\x03\x01",
/* FACILITY_RESP */ [0x3f] = "\x03\x1f\x01",
/* CONNECT_B3_RESP */ [0x41] = "\x03\x2e\x2b\x01",
/* CONNECT_B3_ACTIVE_RESP */ [0x42] = "\x03\x01",
/* DISCONNECT_B3_RESP */ [0x43] = "\x03\x01",
/* DATA_B3_RESP */ [0x45] = "\x03\x19\x01",
/* RESET_B3_RESP */ [0x46] = "\x03\x01",
/* CONNECT_B3_T90_ACTIVE_RESP */ [0x47] = "\x03\x01",
/* MANUFACTURER_RESP */ [0x4e] = "\x03\x2a\x15\x21\x29\x01",
};
/*-------------------------------------------------------*/
#define byteTLcpy(x, y) *(u8 *)(x) = *(u8 *)(y);
#define wordTLcpy(x, y) *(u16 *)(x) = *(u16 *)(y);
#define dwordTLcpy(x, y) memcpy(x, y, 4);
#define structTLcpy(x, y, l) memcpy(x, y, l)
#define structTLcpyovl(x, y, l) memmove(x, y, l)
#define byteTRcpy(x, y) *(u8 *)(y) = *(u8 *)(x);
#define wordTRcpy(x, y) *(u16 *)(y) = *(u16 *)(x);
#define dwordTRcpy(x, y) memcpy(y, x, 4);
#define structTRcpy(x, y, l) memcpy(y, x, l)
#define structTRcpyovl(x, y, l) memmove(y, x, l)
/*-------------------------------------------------------*/
static unsigned command_2_index(u8 c, u8 sc)
{
if (c & 0x80)
c = 0x9 + (c & 0x0f);
else if (c == 0x41)
c = 0x9 + 0x1;
if (c > 0x18)
c = 0x00;
return (sc & 3) * (0x9 + 0x9) + c;
}
/**
* capi_cmd2par() - find parameter string for CAPI 2.0 command/subcommand
* @cmd: command number
* @subcmd: subcommand number
*
* Return value: static string, NULL if command/subcommand unknown
*/
static unsigned char *capi_cmd2par(u8 cmd, u8 subcmd)
{
return cpars[command_2_index(cmd, subcmd)];
}
/*-------------------------------------------------------*/
#define TYP (cdef[cmsg->par[cmsg->p]].typ)
#define OFF (((u8 *)cmsg) + cdef[cmsg->par[cmsg->p]].off)
static void jumpcstruct(_cmsg *cmsg)
{
unsigned layer;
for (cmsg->p++, layer = 1; layer;) {
/* $$$$$ assert (cmsg->p); */
cmsg->p++;
switch (TYP) {
case _CMSTRUCT:
layer++;
break;
case _CEND:
layer--;
break;
}
}
}
/*-------------------------------------------------------*/
static char *mnames[] =
{
[0x01] = "ALERT_REQ",
[0x02] = "CONNECT_REQ",
[0x04] = "DISCONNECT_REQ",
[0x05] = "LISTEN_REQ",
[0x08] = "INFO_REQ",
[0x09] = "FACILITY_REQ",
[0x0a] = "SELECT_B_PROTOCOL_REQ",
[0x0b] = "CONNECT_B3_REQ",
[0x0d] = "DISCONNECT_B3_REQ",
[0x0f] = "DATA_B3_REQ",
[0x10] = "RESET_B3_REQ",
[0x13] = "ALERT_CONF",
[0x14] = "CONNECT_CONF",
[0x16] = "DISCONNECT_CONF",
[0x17] = "LISTEN_CONF",
[0x18] = "MANUFACTURER_REQ",
[0x1a] = "INFO_CONF",
[0x1b] = "FACILITY_CONF",
[0x1c] = "SELECT_B_PROTOCOL_CONF",
[0x1d] = "CONNECT_B3_CONF",
[0x1f] = "DISCONNECT_B3_CONF",
[0x21] = "DATA_B3_CONF",
[0x22] = "RESET_B3_CONF",
[0x26] = "CONNECT_IND",
[0x27] = "CONNECT_ACTIVE_IND",
[0x28] = "DISCONNECT_IND",
[0x2a] = "MANUFACTURER_CONF",
[0x2c] = "INFO_IND",
[0x2d] = "FACILITY_IND",
[0x2f] = "CONNECT_B3_IND",
[0x30] = "CONNECT_B3_ACTIVE_IND",
[0x31] = "DISCONNECT_B3_IND",
[0x33] = "DATA_B3_IND",
[0x34] = "RESET_B3_IND",
[0x35] = "CONNECT_B3_T90_ACTIVE_IND",
[0x38] = "CONNECT_RESP",
[0x39] = "CONNECT_ACTIVE_RESP",
[0x3a] = "DISCONNECT_RESP",
[0x3c] = "MANUFACTURER_IND",
[0x3e] = "INFO_RESP",
[0x3f] = "FACILITY_RESP",
[0x41] = "CONNECT_B3_RESP",
[0x42] = "CONNECT_B3_ACTIVE_RESP",
[0x43] = "DISCONNECT_B3_RESP",
[0x45] = "DATA_B3_RESP",
[0x46] = "RESET_B3_RESP",
[0x47] = "CONNECT_B3_T90_ACTIVE_RESP",
[0x4e] = "MANUFACTURER_RESP"
};
/**
* capi_cmd2str() - convert CAPI 2.0 command/subcommand number to name
* @cmd: command number
* @subcmd: subcommand number
*
* Return value: static string
*/
char *capi_cmd2str(u8 cmd, u8 subcmd)
{
char *result;
result = mnames[command_2_index(cmd, subcmd)];
if (result == NULL)
result = "INVALID_COMMAND";
return result;
}
/*-------------------------------------------------------*/
#ifdef CONFIG_CAPI_TRACE
/*-------------------------------------------------------*/
static char *pnames[] =
{
/*00 */ NULL,
/*01 */ NULL,
/*02 */ NULL,
/*03 */ "Controller/PLCI/NCCI",
/*04 */ "AdditionalInfo",
/*05 */ "B1configuration",
/*06 */ "B1protocol",
/*07 */ "B2configuration",
/*08 */ "B2protocol",
/*09 */ "B3configuration",
/*0a */ "B3protocol",
/*0b */ "BC",
/*0c */ "BChannelinformation",
/*0d */ "BProtocol",
/*0e */ "CalledPartyNumber",
/*0f */ "CalledPartySubaddress",
/*10 */ "CallingPartyNumber",
/*11 */ "CallingPartySubaddress",
/*12 */ "CIPmask",
/*13 */ "CIPmask2",
/*14 */ "CIPValue",
/*15 */ "Class",
/*16 */ "ConnectedNumber",
/*17 */ "ConnectedSubaddress",
/*18 */ "Data32",
/*19 */ "DataHandle",
/*1a */ "DataLength",
/*1b */ "FacilityConfirmationParameter",
/*1c */ "Facilitydataarray",
/*1d */ "FacilityIndicationParameter",
/*1e */ "FacilityRequestParameter",
/*1f */ "FacilitySelector",
/*20 */ "Flags",
/*21 */ "Function",
/*22 */ "HLC",
/*23 */ "Info",
/*24 */ "InfoElement",
/*25 */ "InfoMask",
/*26 */ "InfoNumber",
/*27 */ "Keypadfacility",
/*28 */ "LLC",
/*29 */ "ManuData",
/*2a */ "ManuID",
/*2b */ "NCPI",
/*2c */ "Reason",
/*2d */ "Reason_B3",
/*2e */ "Reject",
/*2f */ "Useruserdata"
};
#include <linux/stdarg.h>
/*-------------------------------------------------------*/
static _cdebbuf *bufprint(_cdebbuf *cdb, char *fmt, ...)
{
va_list f;
size_t n, r;
if (!cdb)
return NULL;
va_start(f, fmt);
r = cdb->size - cdb->pos;
n = vsnprintf(cdb->p, r, fmt, f);
va_end(f);
if (n >= r) {
/* truncated, need bigger buffer */
size_t ns = 2 * cdb->size;
u_char *nb;
while ((ns - cdb->pos) <= n)
ns *= 2;
nb = kmalloc(ns, GFP_ATOMIC);
if (!nb) {
cdebbuf_free(cdb);
return NULL;
}
memcpy(nb, cdb->buf, cdb->pos);
kfree(cdb->buf);
nb[cdb->pos] = 0;
cdb->buf = nb;
cdb->p = cdb->buf + cdb->pos;
cdb->size = ns;
va_start(f, fmt);
r = cdb->size - cdb->pos;
n = vsnprintf(cdb->p, r, fmt, f);
va_end(f);
}
cdb->p += n;
cdb->pos += n;
return cdb;
}
static _cdebbuf *printstructlen(_cdebbuf *cdb, u8 *m, unsigned len)
{
unsigned hex = 0;
if (!cdb)
return NULL;
for (; len; len--, m++)
if (isalnum(*m) || *m == ' ') {
if (hex)
cdb = bufprint(cdb, ">");
cdb = bufprint(cdb, "%c", *m);
hex = 0;
} else {
if (!hex)
cdb = bufprint(cdb, "<%02x", *m);
else
cdb = bufprint(cdb, " %02x", *m);
hex = 1;
}
if (hex)
cdb = bufprint(cdb, ">");
return cdb;
}
static _cdebbuf *printstruct(_cdebbuf *cdb, u8 *m)
{
unsigned len;
if (m[0] != 0xff) {
len = m[0];
m += 1;
} else {
len = ((u16 *) (m + 1))[0];
m += 3;
}
cdb = printstructlen(cdb, m, len);
return cdb;
}
/*-------------------------------------------------------*/
#define NAME (pnames[cmsg->par[cmsg->p]])
static _cdebbuf *protocol_message_2_pars(_cdebbuf *cdb, _cmsg *cmsg, int level)
{
if (!cmsg->par)
return NULL; /* invalid command/subcommand */
for (; TYP != _CEND; cmsg->p++) {
int slen = 29 + 3 - level;
int i;
if (!cdb)
return NULL;
cdb = bufprint(cdb, " ");
for (i = 0; i < level - 1; i++)
cdb = bufprint(cdb, " ");
switch (TYP) {
case _CBYTE:
cdb = bufprint(cdb, "%-*s = 0x%x\n", slen, NAME, *(u8 *) (cmsg->m + cmsg->l));
cmsg->l++;
break;
case _CWORD:
cdb = bufprint(cdb, "%-*s = 0x%x\n", slen, NAME, *(u16 *) (cmsg->m + cmsg->l));
cmsg->l += 2;
break;
case _CDWORD:
cdb = bufprint(cdb, "%-*s = 0x%lx\n", slen, NAME, *(u32 *) (cmsg->m + cmsg->l));
cmsg->l += 4;
break;
case _CSTRUCT:
cdb = bufprint(cdb, "%-*s = ", slen, NAME);
if (cmsg->m[cmsg->l] == '\0')
cdb = bufprint(cdb, "default");
else
cdb = printstruct(cdb, cmsg->m + cmsg->l);
cdb = bufprint(cdb, "\n");
if (cmsg->m[cmsg->l] != 0xff)
cmsg->l += 1 + cmsg->m[cmsg->l];
else
cmsg->l += 3 + *(u16 *) (cmsg->m + cmsg->l + 1);
break;
case _CMSTRUCT:
/*----- Metastruktur 0 -----*/
if (cmsg->m[cmsg->l] == '\0') {
cdb = bufprint(cdb, "%-*s = default\n", slen, NAME);
cmsg->l++;
jumpcstruct(cmsg);
} else {
char *name = NAME;
unsigned _l = cmsg->l;
cdb = bufprint(cdb, "%-*s\n", slen, name);
cmsg->l = (cmsg->m + _l)[0] == 255 ? cmsg->l + 3 : cmsg->l + 1;
cmsg->p++;
cdb = protocol_message_2_pars(cdb, cmsg, level + 1);
}
break;
}
}
return cdb;
}
/*-------------------------------------------------------*/
static _cdebbuf *g_debbuf;
static u_long g_debbuf_lock;
static _cmsg *g_cmsg;
static _cdebbuf *cdebbuf_alloc(void)
{
_cdebbuf *cdb;
if (likely(!test_and_set_bit(1, &g_debbuf_lock))) {
cdb = g_debbuf;
goto init;
} else
cdb = kmalloc_obj(_cdebbuf, GFP_ATOMIC);
if (!cdb)
return NULL;
cdb->buf = kmalloc(CDEBUG_SIZE, GFP_ATOMIC);
if (!cdb->buf) {
kfree(cdb);
return NULL;
}
cdb->size = CDEBUG_SIZE;
init:
cdb->buf[0] = 0;
cdb->p = cdb->buf;
cdb->pos = 0;
return cdb;
}
/**
* cdebbuf_free() - free CAPI debug buffer
* @cdb: buffer to free
*/
void cdebbuf_free(_cdebbuf *cdb)
{
if (likely(cdb == g_debbuf)) {
test_and_clear_bit(1, &g_debbuf_lock);
return;
}
if (likely(cdb))
kfree(cdb->buf);
kfree(cdb);
}
/**
* capi_message2str() - format CAPI 2.0 message for printing
* @msg: CAPI 2.0 message
*
* Allocates a CAPI debug buffer and fills it with a printable representation
* of the CAPI 2.0 message in @msg.
* Return value: allocated debug buffer, NULL on error
* The returned buffer should be freed by a call to cdebbuf_free() after use.
*/
_cdebbuf *capi_message2str(u8 *msg)
{
_cdebbuf *cdb;
_cmsg *cmsg;
cdb = cdebbuf_alloc();
if (unlikely(!cdb))
return NULL;
if (likely(cdb == g_debbuf))
cmsg = g_cmsg;
else
cmsg = kmalloc_obj(_cmsg, GFP_ATOMIC);
if (unlikely(!cmsg)) {
cdebbuf_free(cdb);
return NULL;
}
cmsg->m = msg;
cmsg->l = 8;
cmsg->p = 0;
byteTRcpy(cmsg->m + 4, &cmsg->Command);
byteTRcpy(cmsg->m + 5, &cmsg->Subcommand);
cmsg->par = capi_cmd2par(cmsg->Command, cmsg->Subcommand);
cdb = bufprint(cdb, "%-26s ID=%03d #0x%04x LEN=%04d\n",
capi_cmd2str(cmsg->Command, cmsg->Subcommand),
((unsigned short *) msg)[1],
((unsigned short *) msg)[3],
((unsigned short *) msg)[0]);
cdb = protocol_message_2_pars(cdb, cmsg, 1);
if (unlikely(cmsg != g_cmsg))
kfree(cmsg);
return cdb;
}
int __init cdebug_init(void)
{
g_cmsg = kmalloc_obj(_cmsg);
if (!g_cmsg)
return -ENOMEM;
g_debbuf = kmalloc_obj(_cdebbuf);
if (!g_debbuf) {
kfree(g_cmsg);
return -ENOMEM;
}
g_debbuf->buf = kmalloc(CDEBUG_GSIZE, GFP_KERNEL);
if (!g_debbuf->buf) {
kfree(g_cmsg);
kfree(g_debbuf);
return -ENOMEM;
}
g_debbuf->size = CDEBUG_GSIZE;
g_debbuf->buf[0] = 0;
g_debbuf->p = g_debbuf->buf;
g_debbuf->pos = 0;
return 0;
}
void cdebug_exit(void)
{
if (g_debbuf)
kfree(g_debbuf->buf);
kfree(g_debbuf);
kfree(g_cmsg);
}
#else /* !CONFIG_CAPI_TRACE */
static _cdebbuf g_debbuf = {"CONFIG_CAPI_TRACE not enabled", NULL, 0, 0};
_cdebbuf *capi_message2str(u8 *msg)
{
return &g_debbuf;
}
_cdebbuf *capi_cmsg2str(_cmsg *cmsg)
{
return &g_debbuf;
}
void cdebbuf_free(_cdebbuf *cdb)
{
}
int __init cdebug_init(void)
{
return 0;
}
void cdebug_exit(void)
{
}
#endif

933
drivers/isdn/capi/kcapi.c
View File

@ -1,933 +0,0 @@
/* $Id: kcapi.c,v 1.1.2.8 2004/03/26 19:57:20 armin Exp $
*
* Kernel CAPI 2.0 Module
*
* Copyright 1999 by Carsten Paeth <calle@calle.de>
* Copyright 2002 by Kai Germaschewski <kai@germaschewski.name>
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
*/
#include "kcapi.h"
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/proc_fs.h>
#include <linux/sched/signal.h>
#include <linux/seq_file.h>
#include <linux/skbuff.h>
#include <linux/workqueue.h>
#include <linux/capi.h>
#include <linux/kernelcapi.h>
#include <linux/init.h>
#include <linux/moduleparam.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/isdn/capicmd.h>
#include <linux/isdn/capiutil.h>
#include <linux/mutex.h>
#include <linux/rcupdate.h>
static int showcapimsgs;
static struct workqueue_struct *kcapi_wq;
module_param(showcapimsgs, uint, 0);
/* ------------------------------------------------------------- */
struct capictr_event {
struct work_struct work;
unsigned int type;
u32 controller;
};
/* ------------------------------------------------------------- */
static const struct capi_version driver_version = {2, 0, 1, 1 << 4};
static char driver_serial[CAPI_SERIAL_LEN] = "0004711";
static char capi_manufakturer[64] = "AVM Berlin";
#define NCCI2CTRL(ncci) (((ncci) >> 24) & 0x7f)
struct capi_ctr *capi_controller[CAPI_MAXCONTR];
DEFINE_MUTEX(capi_controller_lock);
struct capi20_appl *capi_applications[CAPI_MAXAPPL];
static int ncontrollers;
/* -------- controller ref counting -------------------------------------- */
static inline struct capi_ctr *
capi_ctr_get(struct capi_ctr *ctr)
{
if (!try_module_get(ctr->owner))
return NULL;
return ctr;
}
static inline void
capi_ctr_put(struct capi_ctr *ctr)
{
module_put(ctr->owner);
}
/* ------------------------------------------------------------- */
static inline struct capi_ctr *get_capi_ctr_by_nr(u16 contr)
{
if (contr < 1 || contr - 1 >= CAPI_MAXCONTR)
return NULL;
return capi_controller[contr - 1];
}
static inline struct capi20_appl *__get_capi_appl_by_nr(u16 applid)
{
lockdep_assert_held(&capi_controller_lock);
if (applid < 1 || applid - 1 >= CAPI_MAXAPPL)
return NULL;
return capi_applications[applid - 1];
}
static inline struct capi20_appl *get_capi_appl_by_nr(u16 applid)
{
if (applid < 1 || applid - 1 >= CAPI_MAXAPPL)
return NULL;
return rcu_dereference(capi_applications[applid - 1]);
}
/* -------- util functions ------------------------------------ */
static inline int capi_cmd_valid(u8 cmd)
{
switch (cmd) {
case CAPI_ALERT:
case CAPI_CONNECT:
case CAPI_CONNECT_ACTIVE:
case CAPI_CONNECT_B3_ACTIVE:
case CAPI_CONNECT_B3:
case CAPI_CONNECT_B3_T90_ACTIVE:
case CAPI_DATA_B3:
case CAPI_DISCONNECT_B3:
case CAPI_DISCONNECT:
case CAPI_FACILITY:
case CAPI_INFO:
case CAPI_LISTEN:
case CAPI_MANUFACTURER:
case CAPI_RESET_B3:
case CAPI_SELECT_B_PROTOCOL:
return 1;
}
return 0;
}
static inline int capi_subcmd_valid(u8 subcmd)
{
switch (subcmd) {
case CAPI_REQ:
case CAPI_CONF:
case CAPI_IND:
case CAPI_RESP:
return 1;
}
return 0;
}
/* ------------------------------------------------------------ */
static void
register_appl(struct capi_ctr *ctr, u16 applid, capi_register_params *rparam)
{
ctr = capi_ctr_get(ctr);
if (ctr)
ctr->register_appl(ctr, applid, rparam);
else
printk(KERN_WARNING "%s: cannot get controller resources\n",
__func__);
}
static void release_appl(struct capi_ctr *ctr, u16 applid)
{
DBG("applid %#x", applid);
ctr->release_appl(ctr, applid);
capi_ctr_put(ctr);
}
static void notify_up(u32 contr)
{
struct capi20_appl *ap;
struct capi_ctr *ctr;
u16 applid;
mutex_lock(&capi_controller_lock);
if (showcapimsgs & 1)
printk(KERN_DEBUG "kcapi: notify up contr %d\n", contr);
ctr = get_capi_ctr_by_nr(contr);
if (ctr) {
if (ctr->state == CAPI_CTR_RUNNING)
goto unlock_out;
ctr->state = CAPI_CTR_RUNNING;
for (applid = 1; applid <= CAPI_MAXAPPL; applid++) {
ap = __get_capi_appl_by_nr(applid);
if (ap)
register_appl(ctr, applid, &ap->rparam);
}
} else
printk(KERN_WARNING "%s: invalid contr %d\n", __func__, contr);
unlock_out:
mutex_unlock(&capi_controller_lock);
}
static void ctr_down(struct capi_ctr *ctr, int new_state)
{
struct capi20_appl *ap;
u16 applid;
if (ctr->state == CAPI_CTR_DETECTED || ctr->state == CAPI_CTR_DETACHED)
return;
ctr->state = new_state;
memset(ctr->manu, 0, sizeof(ctr->manu));
memset(&ctr->version, 0, sizeof(ctr->version));
memset(&ctr->profile, 0, sizeof(ctr->profile));
memset(ctr->serial, 0, sizeof(ctr->serial));
for (applid = 1; applid <= CAPI_MAXAPPL; applid++) {
ap = __get_capi_appl_by_nr(applid);
if (ap)
capi_ctr_put(ctr);
}
}
static void notify_down(u32 contr)
{
struct capi_ctr *ctr;
mutex_lock(&capi_controller_lock);
if (showcapimsgs & 1)
printk(KERN_DEBUG "kcapi: notify down contr %d\n", contr);
ctr = get_capi_ctr_by_nr(contr);
if (ctr)
ctr_down(ctr, CAPI_CTR_DETECTED);
else
printk(KERN_WARNING "%s: invalid contr %d\n", __func__, contr);
mutex_unlock(&capi_controller_lock);
}
static void do_notify_work(struct work_struct *work)
{
struct capictr_event *event =
container_of(work, struct capictr_event, work);
switch (event->type) {
case CAPICTR_UP:
notify_up(event->controller);
break;
case CAPICTR_DOWN:
notify_down(event->controller);
break;
}
kfree(event);
}
static int notify_push(unsigned int event_type, u32 controller)
{
struct capictr_event *event = kmalloc_obj(*event, GFP_ATOMIC);
if (!event)
return -ENOMEM;
INIT_WORK(&event->work, do_notify_work);
event->type = event_type;
event->controller = controller;
queue_work(kcapi_wq, &event->work);
return 0;
}
/* -------- Receiver ------------------------------------------ */
static void recv_handler(struct work_struct *work)
{
struct sk_buff *skb;
struct capi20_appl *ap =
container_of(work, struct capi20_appl, recv_work);
if ((!ap) || (ap->release_in_progress))
return;
mutex_lock(&ap->recv_mtx);
while ((skb = skb_dequeue(&ap->recv_queue))) {
if (CAPIMSG_CMD(skb->data) == CAPI_DATA_B3_IND)
ap->nrecvdatapkt++;
else
ap->nrecvctlpkt++;
ap->recv_message(ap, skb);
}
mutex_unlock(&ap->recv_mtx);
}
/**
* capi_ctr_handle_message() - handle incoming CAPI message
* @ctr: controller descriptor structure.
* @appl: application ID.
* @skb: message.
*
* Called by hardware driver to pass a CAPI message to the application.
*/
void capi_ctr_handle_message(struct capi_ctr *ctr, u16 appl,
struct sk_buff *skb)
{
struct capi20_appl *ap;
int showctl = 0;
u8 cmd, subcmd;
_cdebbuf *cdb;
if (ctr->state != CAPI_CTR_RUNNING) {
cdb = capi_message2str(skb->data);
if (cdb) {
printk(KERN_INFO "kcapi: controller [%03d] not active, got: %s",
ctr->cnr, cdb->buf);
cdebbuf_free(cdb);
} else
printk(KERN_INFO "kcapi: controller [%03d] not active, cannot trace\n",
ctr->cnr);
goto error;
}
cmd = CAPIMSG_COMMAND(skb->data);
subcmd = CAPIMSG_SUBCOMMAND(skb->data);
if (cmd == CAPI_DATA_B3 && subcmd == CAPI_IND) {
ctr->nrecvdatapkt++;
if (ctr->traceflag > 2)
showctl |= 2;
} else {
ctr->nrecvctlpkt++;
if (ctr->traceflag)
showctl |= 2;
}
showctl |= (ctr->traceflag & 1);
if (showctl & 2) {
if (showctl & 1) {
printk(KERN_DEBUG "kcapi: got [%03d] id#%d %s len=%u\n",
ctr->cnr, CAPIMSG_APPID(skb->data),
capi_cmd2str(cmd, subcmd),
CAPIMSG_LEN(skb->data));
} else {
cdb = capi_message2str(skb->data);
if (cdb) {
printk(KERN_DEBUG "kcapi: got [%03d] %s\n",
ctr->cnr, cdb->buf);
cdebbuf_free(cdb);
} else
printk(KERN_DEBUG "kcapi: got [%03d] id#%d %s len=%u, cannot trace\n",
ctr->cnr, CAPIMSG_APPID(skb->data),
capi_cmd2str(cmd, subcmd),
CAPIMSG_LEN(skb->data));
}
}
rcu_read_lock();
ap = get_capi_appl_by_nr(CAPIMSG_APPID(skb->data));
if (!ap) {
rcu_read_unlock();
cdb = capi_message2str(skb->data);
if (cdb) {
printk(KERN_ERR "kcapi: handle_message: applid %d state released (%s)\n",
CAPIMSG_APPID(skb->data), cdb->buf);
cdebbuf_free(cdb);
} else
printk(KERN_ERR "kcapi: handle_message: applid %d state released (%s) cannot trace\n",
CAPIMSG_APPID(skb->data),
capi_cmd2str(cmd, subcmd));
goto error;
}
skb_queue_tail(&ap->recv_queue, skb);
queue_work(kcapi_wq, &ap->recv_work);
rcu_read_unlock();
return;
error:
kfree_skb(skb);
}
EXPORT_SYMBOL(capi_ctr_handle_message);
/**
* capi_ctr_ready() - signal CAPI controller ready
* @ctr: controller descriptor structure.
*
* Called by hardware driver to signal that the controller is up and running.
*/
void capi_ctr_ready(struct capi_ctr *ctr)
{
printk(KERN_NOTICE "kcapi: controller [%03d] \"%s\" ready.\n",
ctr->cnr, ctr->name);
notify_push(CAPICTR_UP, ctr->cnr);
}
EXPORT_SYMBOL(capi_ctr_ready);
/**
* capi_ctr_down() - signal CAPI controller not ready
* @ctr: controller descriptor structure.
*
* Called by hardware driver to signal that the controller is down and
* unavailable for use.
*/
void capi_ctr_down(struct capi_ctr *ctr)
{
printk(KERN_NOTICE "kcapi: controller [%03d] down.\n", ctr->cnr);
notify_push(CAPICTR_DOWN, ctr->cnr);
}
EXPORT_SYMBOL(capi_ctr_down);
/* ------------------------------------------------------------- */
/**
* attach_capi_ctr() - register CAPI controller
* @ctr: controller descriptor structure.
*
* Called by hardware driver to register a controller with the CAPI subsystem.
* Return value: 0 on success, error code < 0 on error
*/
int attach_capi_ctr(struct capi_ctr *ctr)
{
int i;
mutex_lock(&capi_controller_lock);
for (i = 0; i < CAPI_MAXCONTR; i++) {
if (!capi_controller[i])
break;
}
if (i == CAPI_MAXCONTR) {
mutex_unlock(&capi_controller_lock);
printk(KERN_ERR "kcapi: out of controller slots\n");
return -EBUSY;
}
capi_controller[i] = ctr;
ctr->nrecvctlpkt = 0;
ctr->nrecvdatapkt = 0;
ctr->nsentctlpkt = 0;
ctr->nsentdatapkt = 0;
ctr->cnr = i + 1;
ctr->state = CAPI_CTR_DETECTED;
ctr->blocked = 0;
ctr->traceflag = showcapimsgs;
sprintf(ctr->procfn, "capi/controllers/%d", ctr->cnr);
ctr->procent = proc_create_single_data(ctr->procfn, 0, NULL,
ctr->proc_show, ctr);
ncontrollers++;
mutex_unlock(&capi_controller_lock);
printk(KERN_NOTICE "kcapi: controller [%03d]: %s attached\n",
ctr->cnr, ctr->name);
return 0;
}
EXPORT_SYMBOL(attach_capi_ctr);
/**
* detach_capi_ctr() - unregister CAPI controller
* @ctr: controller descriptor structure.
*
* Called by hardware driver to remove the registration of a controller
* with the CAPI subsystem.
* Return value: 0 on success, error code < 0 on error
*/
int detach_capi_ctr(struct capi_ctr *ctr)
{
int err = 0;
mutex_lock(&capi_controller_lock);
ctr_down(ctr, CAPI_CTR_DETACHED);
if (ctr->cnr < 1 || ctr->cnr - 1 >= CAPI_MAXCONTR) {
err = -EINVAL;
goto unlock_out;
}
if (capi_controller[ctr->cnr - 1] != ctr) {
err = -EINVAL;
goto unlock_out;
}
capi_controller[ctr->cnr - 1] = NULL;
ncontrollers--;
if (ctr->procent)
remove_proc_entry(ctr->procfn, NULL);
printk(KERN_NOTICE "kcapi: controller [%03d]: %s unregistered\n",
ctr->cnr, ctr->name);
unlock_out:
mutex_unlock(&capi_controller_lock);
return err;
}
EXPORT_SYMBOL(detach_capi_ctr);
/* ------------------------------------------------------------- */
/* -------- CAPI2.0 Interface ---------------------------------- */
/* ------------------------------------------------------------- */
/**
* capi20_isinstalled() - CAPI 2.0 operation CAPI_INSTALLED
*
* Return value: CAPI result code (CAPI_NOERROR if at least one ISDN controller
* is ready for use, CAPI_REGNOTINSTALLED otherwise)
*/
u16 capi20_isinstalled(void)
{
u16 ret = CAPI_REGNOTINSTALLED;
int i;
mutex_lock(&capi_controller_lock);
for (i = 0; i < CAPI_MAXCONTR; i++)
if (capi_controller[i] &&
capi_controller[i]->state == CAPI_CTR_RUNNING) {
ret = CAPI_NOERROR;
break;
}
mutex_unlock(&capi_controller_lock);
return ret;
}
/**
* capi20_register() - CAPI 2.0 operation CAPI_REGISTER
* @ap: CAPI application descriptor structure.
*
* Register an application's presence with CAPI.
* A unique application ID is assigned and stored in @ap->applid.
* After this function returns successfully, the message receive
* callback function @ap->recv_message() may be called at any time
* until capi20_release() has been called for the same @ap.
* Return value: CAPI result code
*/
u16 capi20_register(struct capi20_appl *ap)
{
int i;
u16 applid;
DBG("");
if (ap->rparam.datablklen < 128)
return CAPI_LOGBLKSIZETOSMALL;
ap->nrecvctlpkt = 0;
ap->nrecvdatapkt = 0;
ap->nsentctlpkt = 0;
ap->nsentdatapkt = 0;
mutex_init(&ap->recv_mtx);
skb_queue_head_init(&ap->recv_queue);
INIT_WORK(&ap->recv_work, recv_handler);
ap->release_in_progress = 0;
mutex_lock(&capi_controller_lock);
for (applid = 1; applid <= CAPI_MAXAPPL; applid++) {
if (capi_applications[applid - 1] == NULL)
break;
}
if (applid > CAPI_MAXAPPL) {
mutex_unlock(&capi_controller_lock);
return CAPI_TOOMANYAPPLS;
}
ap->applid = applid;
capi_applications[applid - 1] = ap;
for (i = 0; i < CAPI_MAXCONTR; i++) {
if (!capi_controller[i] ||
capi_controller[i]->state != CAPI_CTR_RUNNING)
continue;
register_appl(capi_controller[i], applid, &ap->rparam);
}
mutex_unlock(&capi_controller_lock);
if (showcapimsgs & 1) {
printk(KERN_DEBUG "kcapi: appl %d up\n", applid);
}
return CAPI_NOERROR;
}
/**
* capi20_release() - CAPI 2.0 operation CAPI_RELEASE
* @ap: CAPI application descriptor structure.
*
* Terminate an application's registration with CAPI.
* After this function returns successfully, the message receive
* callback function @ap->recv_message() will no longer be called.
* Return value: CAPI result code
*/
u16 capi20_release(struct capi20_appl *ap)
{
int i;
DBG("applid %#x", ap->applid);
mutex_lock(&capi_controller_lock);
ap->release_in_progress = 1;
capi_applications[ap->applid - 1] = NULL;
synchronize_rcu();
for (i = 0; i < CAPI_MAXCONTR; i++) {
if (!capi_controller[i] ||
capi_controller[i]->state != CAPI_CTR_RUNNING)
continue;
release_appl(capi_controller[i], ap->applid);
}
mutex_unlock(&capi_controller_lock);
flush_workqueue(kcapi_wq);
skb_queue_purge(&ap->recv_queue);
if (showcapimsgs & 1) {
printk(KERN_DEBUG "kcapi: appl %d down\n", ap->applid);
}
return CAPI_NOERROR;
}
/**
* capi20_put_message() - CAPI 2.0 operation CAPI_PUT_MESSAGE
* @ap: CAPI application descriptor structure.
* @skb: CAPI message.
*
* Transfer a single message to CAPI.
* Return value: CAPI result code
*/
u16 capi20_put_message(struct capi20_appl *ap, struct sk_buff *skb)
{
struct capi_ctr *ctr;
int showctl = 0;
u8 cmd, subcmd;
DBG("applid %#x", ap->applid);
if (ncontrollers == 0)
return CAPI_REGNOTINSTALLED;
if ((ap->applid == 0) || ap->release_in_progress)
return CAPI_ILLAPPNR;
if (skb->len < 12
|| !capi_cmd_valid(CAPIMSG_COMMAND(skb->data))
|| !capi_subcmd_valid(CAPIMSG_SUBCOMMAND(skb->data)))
return CAPI_ILLCMDORSUBCMDORMSGTOSMALL;
/*
* The controller reference is protected by the existence of the
* application passed to us. We assume that the caller properly
* synchronizes this service with capi20_release.
*/
ctr = get_capi_ctr_by_nr(CAPIMSG_CONTROLLER(skb->data));
if (!ctr || ctr->state != CAPI_CTR_RUNNING)
return CAPI_REGNOTINSTALLED;
if (ctr->blocked)
return CAPI_SENDQUEUEFULL;
cmd = CAPIMSG_COMMAND(skb->data);
subcmd = CAPIMSG_SUBCOMMAND(skb->data);
if (cmd == CAPI_DATA_B3 && subcmd == CAPI_REQ) {
ctr->nsentdatapkt++;
ap->nsentdatapkt++;
if (ctr->traceflag > 2)
showctl |= 2;
} else {
ctr->nsentctlpkt++;
ap->nsentctlpkt++;
if (ctr->traceflag)
showctl |= 2;
}
showctl |= (ctr->traceflag & 1);
if (showctl & 2) {
if (showctl & 1) {
printk(KERN_DEBUG "kcapi: put [%03d] id#%d %s len=%u\n",
CAPIMSG_CONTROLLER(skb->data),
CAPIMSG_APPID(skb->data),
capi_cmd2str(cmd, subcmd),
CAPIMSG_LEN(skb->data));
} else {
_cdebbuf *cdb = capi_message2str(skb->data);
if (cdb) {
printk(KERN_DEBUG "kcapi: put [%03d] %s\n",
CAPIMSG_CONTROLLER(skb->data),
cdb->buf);
cdebbuf_free(cdb);
} else
printk(KERN_DEBUG "kcapi: put [%03d] id#%d %s len=%u cannot trace\n",
CAPIMSG_CONTROLLER(skb->data),
CAPIMSG_APPID(skb->data),
capi_cmd2str(cmd, subcmd),
CAPIMSG_LEN(skb->data));
}
}
return ctr->send_message(ctr, skb);
}
/**
* capi20_get_manufacturer() - CAPI 2.0 operation CAPI_GET_MANUFACTURER
* @contr: controller number.
* @buf: result buffer (64 bytes).
*
* Retrieve information about the manufacturer of the specified ISDN controller
* or (for @contr == 0) the driver itself.
* Return value: CAPI result code
*/
u16 capi20_get_manufacturer(u32 contr, u8 buf[CAPI_MANUFACTURER_LEN])
{
struct capi_ctr *ctr;
u16 ret;
if (contr == 0) {
strscpy_pad(buf, capi_manufakturer, CAPI_MANUFACTURER_LEN);
return CAPI_NOERROR;
}
mutex_lock(&capi_controller_lock);
ctr = get_capi_ctr_by_nr(contr);
if (ctr && ctr->state == CAPI_CTR_RUNNING) {
strscpy_pad(buf, ctr->manu, CAPI_MANUFACTURER_LEN);
ret = CAPI_NOERROR;
} else
ret = CAPI_REGNOTINSTALLED;
mutex_unlock(&capi_controller_lock);
return ret;
}
/**
* capi20_get_version() - CAPI 2.0 operation CAPI_GET_VERSION
* @contr: controller number.
* @verp: result structure.
*
* Retrieve version information for the specified ISDN controller
* or (for @contr == 0) the driver itself.
* Return value: CAPI result code
*/
u16 capi20_get_version(u32 contr, struct capi_version *verp)
{
struct capi_ctr *ctr;
u16 ret;
if (contr == 0) {
*verp = driver_version;
return CAPI_NOERROR;
}
mutex_lock(&capi_controller_lock);
ctr = get_capi_ctr_by_nr(contr);
if (ctr && ctr->state == CAPI_CTR_RUNNING) {
memcpy(verp, &ctr->version, sizeof(capi_version));
ret = CAPI_NOERROR;
} else
ret = CAPI_REGNOTINSTALLED;
mutex_unlock(&capi_controller_lock);
return ret;
}
/**
* capi20_get_serial() - CAPI 2.0 operation CAPI_GET_SERIAL_NUMBER
* @contr: controller number.
* @serial: result buffer (8 bytes).
*
* Retrieve the serial number of the specified ISDN controller
* or (for @contr == 0) the driver itself.
* Return value: CAPI result code
*/
u16 capi20_get_serial(u32 contr, u8 serial[CAPI_SERIAL_LEN])
{
struct capi_ctr *ctr;
u16 ret;
if (contr == 0) {
strscpy(serial, driver_serial, CAPI_SERIAL_LEN);
return CAPI_NOERROR;
}
mutex_lock(&capi_controller_lock);
ctr = get_capi_ctr_by_nr(contr);
if (ctr && ctr->state == CAPI_CTR_RUNNING) {
strscpy(serial, ctr->serial, CAPI_SERIAL_LEN);
ret = CAPI_NOERROR;
} else
ret = CAPI_REGNOTINSTALLED;
mutex_unlock(&capi_controller_lock);
return ret;
}
/**
* capi20_get_profile() - CAPI 2.0 operation CAPI_GET_PROFILE
* @contr: controller number.
* @profp: result structure.
*
* Retrieve capability information for the specified ISDN controller
* or (for @contr == 0) the number of installed controllers.
* Return value: CAPI result code
*/
u16 capi20_get_profile(u32 contr, struct capi_profile *profp)
{
struct capi_ctr *ctr;
u16 ret;
if (contr == 0) {
profp->ncontroller = ncontrollers;
return CAPI_NOERROR;
}
mutex_lock(&capi_controller_lock);
ctr = get_capi_ctr_by_nr(contr);
if (ctr && ctr->state == CAPI_CTR_RUNNING) {
memcpy(profp, &ctr->profile, sizeof(struct capi_profile));
ret = CAPI_NOERROR;
} else
ret = CAPI_REGNOTINSTALLED;
mutex_unlock(&capi_controller_lock);
return ret;
}
/**
* capi20_manufacturer() - CAPI 2.0 operation CAPI_MANUFACTURER
* @cmd: command.
* @data: parameter.
*
* Perform manufacturer specific command.
* Return value: CAPI result code
*/
int capi20_manufacturer(unsigned long cmd, void __user *data)
{
struct capi_ctr *ctr;
int retval;
switch (cmd) {
case KCAPI_CMD_TRACE:
{
kcapi_flagdef fdef;
if (copy_from_user(&fdef, data, sizeof(kcapi_flagdef)))
return -EFAULT;
mutex_lock(&capi_controller_lock);
ctr = get_capi_ctr_by_nr(fdef.contr);
if (ctr) {
ctr->traceflag = fdef.flag;
printk(KERN_INFO "kcapi: contr [%03d] set trace=%d\n",
ctr->cnr, ctr->traceflag);
retval = 0;
} else
retval = -ESRCH;
mutex_unlock(&capi_controller_lock);
return retval;
}
default:
printk(KERN_ERR "kcapi: manufacturer command %lu unknown.\n",
cmd);
break;
}
return -EINVAL;
}
/* ------------------------------------------------------------- */
/* -------- Init & Cleanup ------------------------------------- */
/* ------------------------------------------------------------- */
/*
* init / exit functions
*/
int __init kcapi_init(void)
{
int err;
kcapi_wq = alloc_workqueue("kcapi", WQ_PERCPU, 0);
if (!kcapi_wq)
return -ENOMEM;
err = cdebug_init();
if (err) {
destroy_workqueue(kcapi_wq);
return err;
}
if (IS_ENABLED(CONFIG_PROC_FS))
kcapi_proc_init();
return 0;
}
void kcapi_exit(void)
{
if (IS_ENABLED(CONFIG_PROC_FS))
kcapi_proc_exit();
cdebug_exit();
destroy_workqueue(kcapi_wq);
}

182
drivers/isdn/capi/kcapi.h
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@ -1,182 +0,0 @@
/*
* Kernel CAPI 2.0 Module
*
* Copyright 1999 by Carsten Paeth <calle@calle.de>
* Copyright 2002 by Kai Germaschewski <kai@germaschewski.name>
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
*/
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/isdn/capilli.h>
#ifdef KCAPI_DEBUG
#define DBG(format, arg...) do { \
printk(KERN_DEBUG "%s: " format "\n" , __func__ , ## arg); \
} while (0)
#else
#define DBG(format, arg...) /* */
#endif
enum {
CAPI_CTR_DETACHED = 0,
CAPI_CTR_DETECTED = 1,
CAPI_CTR_LOADING = 2,
CAPI_CTR_RUNNING = 3,
};
extern struct capi_ctr *capi_controller[CAPI_MAXCONTR];
extern struct mutex capi_controller_lock;
extern struct capi20_appl *capi_applications[CAPI_MAXAPPL];
void kcapi_proc_init(void);
void kcapi_proc_exit(void);
struct capi20_appl {
u16 applid;
capi_register_params rparam;
void (*recv_message)(struct capi20_appl *ap, struct sk_buff *skb);
void *private;
/* internal to kernelcapi.o */
unsigned long nrecvctlpkt;
unsigned long nrecvdatapkt;
unsigned long nsentctlpkt;
unsigned long nsentdatapkt;
struct mutex recv_mtx;
struct sk_buff_head recv_queue;
struct work_struct recv_work;
int release_in_progress;
};
u16 capi20_isinstalled(void);
u16 capi20_register(struct capi20_appl *ap);
u16 capi20_release(struct capi20_appl *ap);
u16 capi20_put_message(struct capi20_appl *ap, struct sk_buff *skb);
u16 capi20_get_manufacturer(u32 contr, u8 buf[CAPI_MANUFACTURER_LEN]);
u16 capi20_get_version(u32 contr, struct capi_version *verp);
u16 capi20_get_serial(u32 contr, u8 serial[CAPI_SERIAL_LEN]);
u16 capi20_get_profile(u32 contr, struct capi_profile *profp);
int capi20_manufacturer(unsigned long cmd, void __user *data);
#define CAPICTR_UP 0
#define CAPICTR_DOWN 1
int kcapi_init(void);
void kcapi_exit(void);
/*----- basic-type definitions -----*/
typedef __u8 *_cstruct;
typedef enum {
CAPI_COMPOSE,
CAPI_DEFAULT
} _cmstruct;
/*
The _cmsg structure contains all possible CAPI 2.0 parameter.
All parameters are stored here first. The function CAPI_CMSG_2_MESSAGE
assembles the parameter and builds CAPI2.0 conform messages.
CAPI_MESSAGE_2_CMSG disassembles CAPI 2.0 messages and stores the
parameter in the _cmsg structure
*/
typedef struct {
/* Header */
__u16 ApplId;
__u8 Command;
__u8 Subcommand;
__u16 Messagenumber;
/* Parameter */
union {
__u32 adrController;
__u32 adrPLCI;
__u32 adrNCCI;
} adr;
_cmstruct AdditionalInfo;
_cstruct B1configuration;
__u16 B1protocol;
_cstruct B2configuration;
__u16 B2protocol;
_cstruct B3configuration;
__u16 B3protocol;
_cstruct BC;
_cstruct BChannelinformation;
_cmstruct BProtocol;
_cstruct CalledPartyNumber;
_cstruct CalledPartySubaddress;
_cstruct CallingPartyNumber;
_cstruct CallingPartySubaddress;
__u32 CIPmask;
__u32 CIPmask2;
__u16 CIPValue;
__u32 Class;
_cstruct ConnectedNumber;
_cstruct ConnectedSubaddress;
__u32 Data;
__u16 DataHandle;
__u16 DataLength;
_cstruct FacilityConfirmationParameter;
_cstruct Facilitydataarray;
_cstruct FacilityIndicationParameter;
_cstruct FacilityRequestParameter;
__u16 FacilitySelector;
__u16 Flags;
__u32 Function;
_cstruct HLC;
__u16 Info;
_cstruct InfoElement;
__u32 InfoMask;
__u16 InfoNumber;
_cstruct Keypadfacility;
_cstruct LLC;
_cstruct ManuData;
__u32 ManuID;
_cstruct NCPI;
__u16 Reason;
__u16 Reason_B3;
__u16 Reject;
_cstruct Useruserdata;
/* intern */
unsigned l, p;
unsigned char *par;
__u8 *m;
/* buffer to construct message */
__u8 buf[180];
} _cmsg;
/*-----------------------------------------------------------------------*/
/*
* Debugging / Tracing functions
*/
char *capi_cmd2str(__u8 cmd, __u8 subcmd);
typedef struct {
u_char *buf;
u_char *p;
size_t size;
size_t pos;
} _cdebbuf;
#define CDEBUG_SIZE 1024
#define CDEBUG_GSIZE 4096
void cdebbuf_free(_cdebbuf *cdb);
int cdebug_init(void);
void cdebug_exit(void);
_cdebbuf *capi_message2str(__u8 *msg);

231
drivers/isdn/capi/kcapi_proc.c
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@ -1,231 +0,0 @@
/*
* Kernel CAPI 2.0 Module - /proc/capi handling
*
* Copyright 1999 by Carsten Paeth <calle@calle.de>
* Copyright 2002 by Kai Germaschewski <kai@germaschewski.name>
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
*/
#include "kcapi.h"
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/init.h>
#include <linux/export.h>
static char *state2str(unsigned short state)
{
switch (state) {
case CAPI_CTR_DETECTED: return "detected";
case CAPI_CTR_LOADING: return "loading";
case CAPI_CTR_RUNNING: return "running";
default: return "???";
}
}
// /proc/capi
// ===========================================================================
// /proc/capi/controller:
// cnr driver cardstate name driverinfo
// /proc/capi/contrstats:
// cnr nrecvctlpkt nrecvdatapkt nsentctlpkt nsentdatapkt
// ---------------------------------------------------------------------------
static void *controller_start(struct seq_file *seq, loff_t *pos)
__acquires(capi_controller_lock)
{
mutex_lock(&capi_controller_lock);
if (*pos < CAPI_MAXCONTR)
return &capi_controller[*pos];
return NULL;
}
static void *controller_next(struct seq_file *seq, void *v, loff_t *pos)
{
++*pos;
if (*pos < CAPI_MAXCONTR)
return &capi_controller[*pos];
return NULL;
}
static void controller_stop(struct seq_file *seq, void *v)
__releases(capi_controller_lock)
{
mutex_unlock(&capi_controller_lock);
}
static int controller_show(struct seq_file *seq, void *v)
{
struct capi_ctr *ctr = *(struct capi_ctr **) v;
if (!ctr)
return 0;
seq_printf(seq, "%d %-10s %-8s %-16s %s\n",
ctr->cnr, ctr->driver_name,
state2str(ctr->state),
ctr->name,
ctr->procinfo ? ctr->procinfo(ctr) : "");
return 0;
}
static int contrstats_show(struct seq_file *seq, void *v)
{
struct capi_ctr *ctr = *(struct capi_ctr **) v;
if (!ctr)
return 0;
seq_printf(seq, "%d %lu %lu %lu %lu\n",
ctr->cnr,
ctr->nrecvctlpkt,
ctr->nrecvdatapkt,
ctr->nsentctlpkt,
ctr->nsentdatapkt);
return 0;
}
static const struct seq_operations seq_controller_ops = {
.start = controller_start,
.next = controller_next,
.stop = controller_stop,
.show = controller_show,
};
static const struct seq_operations seq_contrstats_ops = {
.start = controller_start,
.next = controller_next,
.stop = controller_stop,
.show = contrstats_show,
};
// /proc/capi/applications:
// applid l3cnt dblkcnt dblklen #ncci recvqueuelen
// /proc/capi/applstats:
// applid nrecvctlpkt nrecvdatapkt nsentctlpkt nsentdatapkt
// ---------------------------------------------------------------------------
static void *applications_start(struct seq_file *seq, loff_t *pos)
__acquires(capi_controller_lock)
{
mutex_lock(&capi_controller_lock);
if (*pos < CAPI_MAXAPPL)
return &capi_applications[*pos];
return NULL;
}
static void *
applications_next(struct seq_file *seq, void *v, loff_t *pos)
{
++*pos;
if (*pos < CAPI_MAXAPPL)
return &capi_applications[*pos];
return NULL;
}
static void applications_stop(struct seq_file *seq, void *v)
__releases(capi_controller_lock)
{
mutex_unlock(&capi_controller_lock);
}
static int
applications_show(struct seq_file *seq, void *v)
{
struct capi20_appl *ap = *(struct capi20_appl **) v;
if (!ap)
return 0;
seq_printf(seq, "%u %d %d %d\n",
ap->applid,
ap->rparam.level3cnt,
ap->rparam.datablkcnt,
ap->rparam.datablklen);
return 0;
}
static int
applstats_show(struct seq_file *seq, void *v)
{
struct capi20_appl *ap = *(struct capi20_appl **) v;
if (!ap)
return 0;
seq_printf(seq, "%u %lu %lu %lu %lu\n",
ap->applid,
ap->nrecvctlpkt,
ap->nrecvdatapkt,
ap->nsentctlpkt,
ap->nsentdatapkt);
return 0;
}
static const struct seq_operations seq_applications_ops = {
.start = applications_start,
.next = applications_next,
.stop = applications_stop,
.show = applications_show,
};
static const struct seq_operations seq_applstats_ops = {
.start = applications_start,
.next = applications_next,
.stop = applications_stop,
.show = applstats_show,
};
// ---------------------------------------------------------------------------
/* /proc/capi/drivers is always empty */
static ssize_t empty_read(struct file *file, char __user *buf,
size_t size, loff_t *off)
{
return 0;
}
static const struct proc_ops empty_proc_ops = {
.proc_read = empty_read,
.proc_lseek = default_llseek,
};
// ---------------------------------------------------------------------------
void __init
kcapi_proc_init(void)
{
proc_mkdir("capi", NULL);
proc_mkdir("capi/controllers", NULL);
proc_create_seq("capi/controller", 0, NULL, &seq_controller_ops);
proc_create_seq("capi/contrstats", 0, NULL, &seq_contrstats_ops);
proc_create_seq("capi/applications", 0, NULL, &seq_applications_ops);
proc_create_seq("capi/applstats", 0, NULL, &seq_applstats_ops);
proc_create("capi/driver", 0, NULL, &empty_proc_ops);
}
void
kcapi_proc_exit(void)
{
remove_proc_entry("capi/driver", NULL);
remove_proc_entry("capi/controller", NULL);
remove_proc_entry("capi/contrstats", NULL);
remove_proc_entry("capi/applications", NULL);
remove_proc_entry("capi/applstats", NULL);
remove_proc_entry("capi/controllers", NULL);
remove_proc_entry("capi", NULL);
}

6
drivers/isdn/hardware/Makefile
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@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
# Makefile for the CAPI hardware drivers
# Object files in subdirectories
obj-$(CONFIG_MISDN) += mISDN/

98
drivers/isdn/hardware/mISDN/Kconfig
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@ -1,98 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Hardware for mISDN
#
comment "mISDN hardware drivers"
config MISDN_HFCPCI
tristate "Support for HFC PCI cards"
depends on MISDN
depends on PCI
help
Enable support for cards with Cologne Chip AG's
HFC PCI chip.
config MISDN_HFCMULTI
tristate "Support for HFC multiport cards (HFC-4S/8S/E1)"
depends on (PCI || CPM1) && HAS_IOPORT
depends on MISDN
help
Enable support for cards with Cologne Chip AG's HFC multiport
chip. There are three types of chips that are quite similar,
but the interface is different:
* HFC-4S (4 S/T interfaces on one chip)
* HFC-8S (8 S/T interfaces on one chip)
* HFC-E1 (E1 interface for 2Mbit ISDN)
config MISDN_HFCMULTI_8xx
bool "Support for XHFC embedded board in HFC multiport driver"
depends on MISDN
depends on MISDN_HFCMULTI
depends on CPM1
default CPM1
help
Enable support for the XHFC embedded solution from Speech Design.
config MISDN_HFCUSB
tristate "Support for HFC-S USB based TAs"
depends on USB
help
Enable support for USB ISDN TAs with Cologne Chip AG's
HFC-S USB ISDN Controller
config MISDN_AVMFRITZ
tristate "Support for AVM FRITZ!CARD PCI"
depends on MISDN
depends on PCI && HAS_IOPORT
select MISDN_IPAC
help
Enable support for AVMs FRITZ!CARD PCI cards
config MISDN_SPEEDFAX
tristate "Support for Sedlbauer Speedfax+"
depends on MISDN
depends on PCI && HAS_IOPORT
select MISDN_IPAC
select MISDN_ISAR
help
Enable support for Sedlbauer Speedfax+.
config MISDN_INFINEON
tristate "Support for cards with Infineon chipset"
depends on MISDN
depends on PCI && HAS_IOPORT
select MISDN_IPAC
help
Enable support for cards with ISAC + HSCX, IPAC or IPAC-SX
chip from Infineon (former manufacturer Siemens).
config MISDN_W6692
tristate "Support for cards with Winbond 6692"
depends on MISDN
depends on PCI && HAS_IOPORT
help
Enable support for Winbond 6692 PCI chip based cards.
config MISDN_NETJET
tristate "Support for NETJet cards"
depends on MISDN
depends on PCI && HAS_IOPORT
depends on TTY
select MISDN_IPAC
select MISDN_HDLC
help
Enable support for Traverse Technologies NETJet PCI cards.
config MISDN_HDLC
tristate
select CRC_CCITT
select BITREVERSE
config MISDN_IPAC
tristate
depends on MISDN
config MISDN_ISAR
tristate
depends on MISDN

19
drivers/isdn/hardware/mISDN/Makefile
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@ -1,19 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the modular ISDN hardware drivers
#
#
obj-$(CONFIG_MISDN_HFCPCI) += hfcpci.o
obj-$(CONFIG_MISDN_HFCMULTI) += hfcmulti.o
obj-$(CONFIG_MISDN_HFCUSB) += hfcsusb.o
obj-$(CONFIG_MISDN_AVMFRITZ) += avmfritz.o
obj-$(CONFIG_MISDN_SPEEDFAX) += speedfax.o
obj-$(CONFIG_MISDN_INFINEON) += mISDNinfineon.o
obj-$(CONFIG_MISDN_W6692) += w6692.o
obj-$(CONFIG_MISDN_NETJET) += netjet.o
# chip modules
obj-$(CONFIG_MISDN_IPAC) += mISDNipac.o
obj-$(CONFIG_MISDN_ISAR) += mISDNisar.o
obj-$(CONFIG_MISDN_HDLC) += isdnhdlc.o

1164
drivers/isdn/hardware/mISDN/avmfritz.c
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File diff suppressed because it is too large Load Diff

1236
drivers/isdn/hardware/mISDN/hfc_multi.h
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File diff suppressed because it is too large Load Diff

167
drivers/isdn/hardware/mISDN/hfc_multi_8xx.h
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@ -1,167 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* For License see notice in hfc_multi.c
*
* special IO and init functions for the embedded XHFC board
* from Speech Design
*
*/
#include <asm/cpm1.h>
/* Change this to the value used by your board */
#ifndef IMAP_ADDR
#define IMAP_ADDR 0xFFF00000
#endif
static void
#ifdef HFC_REGISTER_DEBUG
HFC_outb_embsd(struct hfc_multi *hc, u_char reg, u_char val,
const char *function, int line)
#else
HFC_outb_embsd(struct hfc_multi *hc, u_char reg, u_char val)
#endif
{
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
writeb(reg, hc->xhfc_memaddr);
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
writeb(val, hc->xhfc_memdata);
}
static u_char
#ifdef HFC_REGISTER_DEBUG
HFC_inb_embsd(struct hfc_multi *hc, u_char reg, const char *function, int line)
#else
HFC_inb_embsd(struct hfc_multi *hc, u_char reg)
#endif
{
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
writeb(reg, hc->xhfc_memaddr);
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
return readb(hc->xhfc_memdata);
}
static u_short
#ifdef HFC_REGISTER_DEBUG
HFC_inw_embsd(struct hfc_multi *hc, u_char reg, const char *function, int line)
#else
HFC_inw_embsd(struct hfc_multi *hc, u_char reg)
#endif
{
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
writeb(reg, hc->xhfc_memaddr);
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
return readb(hc->xhfc_memdata);
}
static void
#ifdef HFC_REGISTER_DEBUG
HFC_wait_embsd(struct hfc_multi *hc, const char *function, int line)
#else
HFC_wait_embsd(struct hfc_multi *hc)
#endif
{
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
writeb(R_STATUS, hc->xhfc_memaddr);
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
while (readb(hc->xhfc_memdata) & V_BUSY)
cpu_relax();
}
/* write fifo data (EMBSD) */
void
write_fifo_embsd(struct hfc_multi *hc, u_char *data, int len)
{
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
*hc->xhfc_memaddr = A_FIFO_DATA0;
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
while (len) {
*hc->xhfc_memdata = *data;
data++;
len--;
}
}
/* read fifo data (EMBSD) */
void
read_fifo_embsd(struct hfc_multi *hc, u_char *data, int len)
{
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
*hc->xhfc_memaddr = A_FIFO_DATA0;
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
while (len) {
*data = (u_char)(*hc->xhfc_memdata);
data++;
len--;
}
}
static int
setup_embedded(struct hfc_multi *hc, struct hm_map *m)
{
printk(KERN_INFO
"HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
hc->pci_dev = NULL;
if (m->clock2)
test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
hc->leds = m->leds;
hc->ledstate = 0xAFFEAFFE;
hc->opticalsupport = m->opticalsupport;
hc->pci_iobase = 0;
hc->pci_membase = 0;
hc->xhfc_membase = NULL;
hc->xhfc_memaddr = NULL;
hc->xhfc_memdata = NULL;
/* set memory access methods */
if (m->io_mode) /* use mode from card config */
hc->io_mode = m->io_mode;
switch (hc->io_mode) {
case HFC_IO_MODE_EMBSD:
test_and_set_bit(HFC_CHIP_EMBSD, &hc->chip);
hc->slots = 128; /* required */
hc->HFC_outb = HFC_outb_embsd;
hc->HFC_inb = HFC_inb_embsd;
hc->HFC_inw = HFC_inw_embsd;
hc->HFC_wait = HFC_wait_embsd;
hc->read_fifo = read_fifo_embsd;
hc->write_fifo = write_fifo_embsd;
hc->xhfc_origmembase = XHFC_MEMBASE + XHFC_OFFSET * hc->id;
hc->xhfc_membase = (u_char *)ioremap(hc->xhfc_origmembase,
XHFC_MEMSIZE);
if (!hc->xhfc_membase) {
printk(KERN_WARNING
"HFC-multi: failed to remap xhfc address space. "
"(internal error)\n");
return -EIO;
}
hc->xhfc_memaddr = (u_long *)(hc->xhfc_membase + 4);
hc->xhfc_memdata = (u_long *)(hc->xhfc_membase);
printk(KERN_INFO
"HFC-multi: xhfc_membase:%#lx xhfc_origmembase:%#lx "
"xhfc_memaddr:%#lx xhfc_memdata:%#lx\n",
(u_long)hc->xhfc_membase, hc->xhfc_origmembase,
(u_long)hc->xhfc_memaddr, (u_long)hc->xhfc_memdata);
break;
default:
printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
return -EIO;
}
/* Prepare the MPC8XX PortA 10 as output (address/data selector) */
hc->immap = (struct immap *)(IMAP_ADDR);
hc->immap->im_ioport.iop_papar &= ~(PA_XHFC_A0);
hc->immap->im_ioport.iop_paodr &= ~(PA_XHFC_A0);
hc->immap->im_ioport.iop_padir |= PA_XHFC_A0;
/* Prepare the MPC8xx PortB __X__ as input (ISDN__X__IRQ) */
hc->pb_irqmsk = (PB_XHFC_IRQ1 << hc->id);
hc->immap->im_cpm.cp_pbpar &= ~(hc->pb_irqmsk);
hc->immap->im_cpm.cp_pbodr &= ~(hc->pb_irqmsk);
hc->immap->im_cpm.cp_pbdir &= ~(hc->pb_irqmsk);
/* At this point the needed config is done */
/* fifos are still not enabled */
return 0;
}

214
drivers/isdn/hardware/mISDN/hfc_pci.h
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@ -1,214 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* specific defines for CCD's HFC 2BDS0 PCI chips
*
* Author Werner Cornelius (werner@isdn4linux.de)
*
* Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)
*/
/*
* thresholds for transparent B-channel mode
* change mask and threshold simultaneously
*/
#define HFCPCI_BTRANS_THRESHOLD 128
#define HFCPCI_FILLEMPTY 64
#define HFCPCI_BTRANS_THRESMASK 0x00
/* defines for PCI config */
#define PCI_ENA_MEMIO 0x02
#define PCI_ENA_MASTER 0x04
/* GCI/IOM bus monitor registers */
#define HCFPCI_C_I 0x08
#define HFCPCI_TRxR 0x0C
#define HFCPCI_MON1_D 0x28
#define HFCPCI_MON2_D 0x2C
/* GCI/IOM bus timeslot registers */
#define HFCPCI_B1_SSL 0x80
#define HFCPCI_B2_SSL 0x84
#define HFCPCI_AUX1_SSL 0x88
#define HFCPCI_AUX2_SSL 0x8C
#define HFCPCI_B1_RSL 0x90
#define HFCPCI_B2_RSL 0x94
#define HFCPCI_AUX1_RSL 0x98
#define HFCPCI_AUX2_RSL 0x9C
/* GCI/IOM bus data registers */
#define HFCPCI_B1_D 0xA0
#define HFCPCI_B2_D 0xA4
#define HFCPCI_AUX1_D 0xA8
#define HFCPCI_AUX2_D 0xAC
/* GCI/IOM bus configuration registers */
#define HFCPCI_MST_EMOD 0xB4
#define HFCPCI_MST_MODE 0xB8
#define HFCPCI_CONNECT 0xBC
/* Interrupt and status registers */
#define HFCPCI_FIFO_EN 0x44
#define HFCPCI_TRM 0x48
#define HFCPCI_B_MODE 0x4C
#define HFCPCI_CHIP_ID 0x58
#define HFCPCI_CIRM 0x60
#define HFCPCI_CTMT 0x64
#define HFCPCI_INT_M1 0x68
#define HFCPCI_INT_M2 0x6C
#define HFCPCI_INT_S1 0x78
#define HFCPCI_INT_S2 0x7C
#define HFCPCI_STATUS 0x70
/* S/T section registers */
#define HFCPCI_STATES 0xC0
#define HFCPCI_SCTRL 0xC4
#define HFCPCI_SCTRL_E 0xC8
#define HFCPCI_SCTRL_R 0xCC
#define HFCPCI_SQ 0xD0
#define HFCPCI_CLKDEL 0xDC
#define HFCPCI_B1_REC 0xF0
#define HFCPCI_B1_SEND 0xF0
#define HFCPCI_B2_REC 0xF4
#define HFCPCI_B2_SEND 0xF4
#define HFCPCI_D_REC 0xF8
#define HFCPCI_D_SEND 0xF8
#define HFCPCI_E_REC 0xFC
/* bits in status register (READ) */
#define HFCPCI_PCI_PROC 0x02
#define HFCPCI_NBUSY 0x04
#define HFCPCI_TIMER_ELAP 0x10
#define HFCPCI_STATINT 0x20
#define HFCPCI_FRAMEINT 0x40
#define HFCPCI_ANYINT 0x80
/* bits in CTMT (Write) */
#define HFCPCI_CLTIMER 0x80
#define HFCPCI_TIM3_125 0x04
#define HFCPCI_TIM25 0x10
#define HFCPCI_TIM50 0x14
#define HFCPCI_TIM400 0x18
#define HFCPCI_TIM800 0x1C
#define HFCPCI_AUTO_TIMER 0x20
#define HFCPCI_TRANSB2 0x02
#define HFCPCI_TRANSB1 0x01
/* bits in CIRM (Write) */
#define HFCPCI_AUX_MSK 0x07
#define HFCPCI_RESET 0x08
#define HFCPCI_B1_REV 0x40
#define HFCPCI_B2_REV 0x80
/* bits in INT_M1 and INT_S1 */
#define HFCPCI_INTS_B1TRANS 0x01
#define HFCPCI_INTS_B2TRANS 0x02
#define HFCPCI_INTS_DTRANS 0x04
#define HFCPCI_INTS_B1REC 0x08
#define HFCPCI_INTS_B2REC 0x10
#define HFCPCI_INTS_DREC 0x20
#define HFCPCI_INTS_L1STATE 0x40
#define HFCPCI_INTS_TIMER 0x80
/* bits in INT_M2 */
#define HFCPCI_PROC_TRANS 0x01
#define HFCPCI_GCI_I_CHG 0x02
#define HFCPCI_GCI_MON_REC 0x04
#define HFCPCI_IRQ_ENABLE 0x08
#define HFCPCI_PMESEL 0x80
/* bits in STATES */
#define HFCPCI_STATE_MSK 0x0F
#define HFCPCI_LOAD_STATE 0x10
#define HFCPCI_ACTIVATE 0x20
#define HFCPCI_DO_ACTION 0x40
#define HFCPCI_NT_G2_G3 0x80
/* bits in HFCD_MST_MODE */
#define HFCPCI_MASTER 0x01
#define HFCPCI_SLAVE 0x00
#define HFCPCI_F0IO_POSITIV 0x02
#define HFCPCI_F0_NEGATIV 0x04
#define HFCPCI_F0_2C4 0x08
/* remaining bits are for codecs control */
/* bits in HFCD_SCTRL */
#define SCTRL_B1_ENA 0x01
#define SCTRL_B2_ENA 0x02
#define SCTRL_MODE_TE 0x00
#define SCTRL_MODE_NT 0x04
#define SCTRL_LOW_PRIO 0x08
#define SCTRL_SQ_ENA 0x10
#define SCTRL_TEST 0x20
#define SCTRL_NONE_CAP 0x40
#define SCTRL_PWR_DOWN 0x80
/* bits in SCTRL_E */
#define HFCPCI_AUTO_AWAKE 0x01
#define HFCPCI_DBIT_1 0x04
#define HFCPCI_IGNORE_COL 0x08
#define HFCPCI_CHG_B1_B2 0x80
/* bits in FIFO_EN register */
#define HFCPCI_FIFOEN_B1 0x03
#define HFCPCI_FIFOEN_B2 0x0C
#define HFCPCI_FIFOEN_DTX 0x10
#define HFCPCI_FIFOEN_B1TX 0x01
#define HFCPCI_FIFOEN_B1RX 0x02
#define HFCPCI_FIFOEN_B2TX 0x04
#define HFCPCI_FIFOEN_B2RX 0x08
/* definitions of fifo memory area */
#define MAX_D_FRAMES 15
#define MAX_B_FRAMES 31
#define B_SUB_VAL 0x200
#define B_FIFO_SIZE (0x2000 - B_SUB_VAL)
#define D_FIFO_SIZE 512
#define D_FREG_MASK 0xF
struct zt {
__le16 z1; /* Z1 pointer 16 Bit */
__le16 z2; /* Z2 pointer 16 Bit */
};
struct dfifo {
u_char data[D_FIFO_SIZE]; /* FIFO data space */
u_char fill1[0x20A0 - D_FIFO_SIZE]; /* reserved, do not use */
u_char f1, f2; /* f pointers */
u_char fill2[0x20C0 - 0x20A2]; /* reserved, do not use */
/* mask index with D_FREG_MASK for access */
struct zt za[MAX_D_FRAMES + 1];
u_char fill3[0x4000 - 0x2100]; /* align 16K */
};
struct bzfifo {
struct zt za[MAX_B_FRAMES + 1]; /* only range 0x0..0x1F allowed */
u_char f1, f2; /* f pointers */
u_char fill[0x2100 - 0x2082]; /* alignment */
};
union fifo_area {
struct {
struct dfifo d_tx; /* D-send channel */
struct dfifo d_rx; /* D-receive channel */
} d_chan;
struct {
u_char fill1[0x200];
u_char txdat_b1[B_FIFO_SIZE];
struct bzfifo txbz_b1;
struct bzfifo txbz_b2;
u_char txdat_b2[B_FIFO_SIZE];
u_char fill2[D_FIFO_SIZE];
u_char rxdat_b1[B_FIFO_SIZE];
struct bzfifo rxbz_b1;
struct bzfifo rxbz_b2;
u_char rxdat_b2[B_FIFO_SIZE];
} b_chans;
u_char fill[32768];
};
#define Write_hfc(a, b, c) (writeb(c, (a->hw.pci_io) + b))
#define Read_hfc(a, b) (readb((a->hw.pci_io) + b))

5540
drivers/isdn/hardware/mISDN/hfcmulti.c
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2360
drivers/isdn/hardware/mISDN/hfcpci.c
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drivers/isdn/hardware/mISDN/hfcsusb.c
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drivers/isdn/hardware/mISDN/hfcsusb.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* hfcsusb.h, HFC-S USB mISDN driver
*/
#ifndef __HFCSUSB_H__
#define __HFCSUSB_H__
#define DRIVER_NAME "HFC-S_USB"
#define DBG_HFC_CALL_TRACE 0x00010000
#define DBG_HFC_FIFO_VERBOSE 0x00020000
#define DBG_HFC_USB_VERBOSE 0x00100000
#define DBG_HFC_URB_INFO 0x00200000
#define DBG_HFC_URB_ERROR 0x00400000
#define DEFAULT_TRANSP_BURST_SZ 128
#define HFC_CTRL_TIMEOUT 20 /* 5ms timeout writing/reading regs */
#define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
#define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
/* hfcsusb Layer1 commands */
#define HFC_L1_ACTIVATE_TE 1
#define HFC_L1_ACTIVATE_NT 2
#define HFC_L1_DEACTIVATE_NT 3
#define HFC_L1_FORCE_DEACTIVATE_TE 4
/* cmd FLAGS in HFCUSB_STATES register */
#define HFCUSB_LOAD_STATE 0x10
#define HFCUSB_ACTIVATE 0x20
#define HFCUSB_DO_ACTION 0x40
#define HFCUSB_NT_G2_G3 0x80
/* timers */
#define NT_ACTIVATION_TIMER 0x01 /* enables NT mode activation Timer */
#define NT_T1_COUNT 10
#define MAX_BCH_SIZE 2048 /* allowed B-channel packet size */
#define HFCUSB_RX_THRESHOLD 64 /* threshold for fifo report bit rx */
#define HFCUSB_TX_THRESHOLD 96 /* threshold for fifo report bit tx */
#define HFCUSB_CHIP_ID 0x16 /* Chip ID register index */
#define HFCUSB_CIRM 0x00 /* cirm register index */
#define HFCUSB_USB_SIZE 0x07 /* int length register */
#define HFCUSB_USB_SIZE_I 0x06 /* iso length register */
#define HFCUSB_F_CROSS 0x0b /* bit order register */
#define HFCUSB_CLKDEL 0x37 /* bit delay register */
#define HFCUSB_CON_HDLC 0xfa /* channel connect register */
#define HFCUSB_HDLC_PAR 0xfb
#define HFCUSB_SCTRL 0x31 /* S-bus control register (tx) */
#define HFCUSB_SCTRL_E 0x32 /* same for E and special funcs */
#define HFCUSB_SCTRL_R 0x33 /* S-bus control register (rx) */
#define HFCUSB_F_THRES 0x0c /* threshold register */
#define HFCUSB_FIFO 0x0f /* fifo select register */
#define HFCUSB_F_USAGE 0x1a /* fifo usage register */
#define HFCUSB_MST_MODE0 0x14
#define HFCUSB_MST_MODE1 0x15
#define HFCUSB_P_DATA 0x1f
#define HFCUSB_INC_RES_F 0x0e
#define HFCUSB_B1_SSL 0x20
#define HFCUSB_B2_SSL 0x21
#define HFCUSB_B1_RSL 0x24
#define HFCUSB_B2_RSL 0x25
#define HFCUSB_STATES 0x30
#define HFCUSB_CHIPID 0x40 /* ID value of HFC-S USB */
/* fifo registers */
#define HFCUSB_NUM_FIFOS 8 /* maximum number of fifos */
#define HFCUSB_B1_TX 0 /* index for B1 transmit bulk/int */
#define HFCUSB_B1_RX 1 /* index for B1 receive bulk/int */
#define HFCUSB_B2_TX 2
#define HFCUSB_B2_RX 3
#define HFCUSB_D_TX 4
#define HFCUSB_D_RX 5
#define HFCUSB_PCM_TX 6
#define HFCUSB_PCM_RX 7
#define USB_INT 0
#define USB_BULK 1
#define USB_ISOC 2
#define ISOC_PACKETS_D 8
#define ISOC_PACKETS_B 8
#define ISO_BUFFER_SIZE 128
/* defines how much ISO packets are handled in one URB */
static int iso_packets[8] =
{ ISOC_PACKETS_B, ISOC_PACKETS_B, ISOC_PACKETS_B, ISOC_PACKETS_B,
ISOC_PACKETS_D, ISOC_PACKETS_D, ISOC_PACKETS_D, ISOC_PACKETS_D
};
/* Fifo flow Control for TX ISO */
#define SINK_MAX 68
#define SINK_MIN 48
#define SINK_DMIN 12
#define SINK_DMAX 18
#define BITLINE_INF (-96 * 8)
/* HFC-S USB register access by Control-URSs */
#define write_reg_atomic(a, b, c) \
usb_control_msg((a)->dev, (a)->ctrl_out_pipe, 0, 0x40, (c), (b), \
0, 0, HFC_CTRL_TIMEOUT)
#define read_reg_atomic(a, b, c) \
usb_control_msg((a)->dev, (a)->ctrl_in_pipe, 1, 0xC0, 0, (b), (c), \
1, HFC_CTRL_TIMEOUT)
#define HFC_CTRL_BUFSIZE 64
struct ctrl_buf {
__u8 hfcs_reg; /* register number */
__u8 reg_val; /* value to be written (or read) */
};
/*
* URB error codes
* Used to represent a list of values and their respective symbolic names
*/
struct hfcusb_symbolic_list {
const int num;
const char *name;
};
static struct hfcusb_symbolic_list urb_errlist[] = {
{-ENOMEM, "No memory for allocation of internal structures"},
{-ENOSPC, "The host controller's bandwidth is already consumed"},
{-ENOENT, "URB was canceled by unlink_urb"},
{-EXDEV, "ISO transfer only partially completed"},
{-EAGAIN, "Too match scheduled for the future"},
{-ENXIO, "URB already queued"},
{-EFBIG, "Too much ISO frames requested"},
{-ENOSR, "Buffer error (overrun)"},
{-EPIPE, "Specified endpoint is stalled (device not responding)"},
{-EOVERFLOW, "Babble (bad cable?)"},
{-EPROTO, "Bit-stuff error (bad cable?)"},
{-EILSEQ, "CRC/Timeout"},
{-ETIMEDOUT, "NAK (device does not respond)"},
{-ESHUTDOWN, "Device unplugged"},
{-1, NULL}
};
static inline const char *
symbolic(struct hfcusb_symbolic_list list[], const int num)
{
int i;
for (i = 0; list[i].name != NULL; i++)
if (list[i].num == num)
return list[i].name;
return "<unknown USB Error>";
}
/* USB descriptor need to contain one of the following EndPoint combination: */
#define CNF_4INT3ISO 1 /* 4 INT IN, 3 ISO OUT */
#define CNF_3INT3ISO 2 /* 3 INT IN, 3 ISO OUT */
#define CNF_4ISO3ISO 3 /* 4 ISO IN, 3 ISO OUT */
#define CNF_3ISO3ISO 4 /* 3 ISO IN, 3 ISO OUT */
#define EP_NUL 1 /* Endpoint at this position not allowed */
#define EP_NOP 2 /* all type of endpoints allowed at this position */
#define EP_ISO 3 /* Isochron endpoint mandatory at this position */
#define EP_BLK 4 /* Bulk endpoint mandatory at this position */
#define EP_INT 5 /* Interrupt endpoint mandatory at this position */
#define HFC_CHAN_B1 0
#define HFC_CHAN_B2 1
#define HFC_CHAN_D 2
#define HFC_CHAN_E 3
/*
* List of all supported endpoint configuration sets, used to find the
* best matching endpoint configuration within a device's USB descriptor.
* We need at least 3 RX endpoints, and 3 TX endpoints, either
* INT-in and ISO-out, or ISO-in and ISO-out)
* with 4 RX endpoints even E-Channel logging is possible
*/
static int
validconf[][19] = {
/* INT in, ISO out config */
{EP_NUL, EP_INT, EP_NUL, EP_INT, EP_NUL, EP_INT, EP_NOP, EP_INT,
EP_ISO, EP_NUL, EP_ISO, EP_NUL, EP_ISO, EP_NUL, EP_NUL, EP_NUL,
CNF_4INT3ISO, 2, 1},
{EP_NUL, EP_INT, EP_NUL, EP_INT, EP_NUL, EP_INT, EP_NUL, EP_NUL,
EP_ISO, EP_NUL, EP_ISO, EP_NUL, EP_ISO, EP_NUL, EP_NUL, EP_NUL,
CNF_3INT3ISO, 2, 0},
/* ISO in, ISO out config */
{EP_NOP, EP_NOP, EP_NOP, EP_NOP, EP_NOP, EP_NOP, EP_NOP, EP_NOP,
EP_ISO, EP_ISO, EP_ISO, EP_ISO, EP_ISO, EP_ISO, EP_NOP, EP_ISO,
CNF_4ISO3ISO, 2, 1},
{EP_NUL, EP_NUL, EP_NUL, EP_NUL, EP_NUL, EP_NUL, EP_NUL, EP_NUL,
EP_ISO, EP_ISO, EP_ISO, EP_ISO, EP_ISO, EP_ISO, EP_NUL, EP_NUL,
CNF_3ISO3ISO, 2, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* EOL element */
};
/* string description of chosen config */
static char *conf_str[] = {
"4 Interrupt IN + 3 Isochron OUT",
"3 Interrupt IN + 3 Isochron OUT",
"4 Isochron IN + 3 Isochron OUT",
"3 Isochron IN + 3 Isochron OUT"
};
#define LED_OFF 0 /* no LED support */
#define LED_SCHEME1 1 /* LED standard scheme */
#define LED_SCHEME2 2 /* not used yet... */
#define LED_POWER_ON 1
#define LED_POWER_OFF 2
#define LED_S0_ON 3
#define LED_S0_OFF 4
#define LED_B1_ON 5
#define LED_B1_OFF 6
#define LED_B1_DATA 7
#define LED_B2_ON 8
#define LED_B2_OFF 9
#define LED_B2_DATA 10
#define LED_NORMAL 0 /* LEDs are normal */
#define LED_INVERTED 1 /* LEDs are inverted */
/* time in ms to perform a Flashing LED when B-Channel has traffic */
#define LED_TIME 250
struct hfcsusb;
struct usb_fifo;
/* structure defining input+output fifos (interrupt/bulk mode) */
struct iso_urb {
struct urb *urb;
__u8 buffer[ISO_BUFFER_SIZE]; /* buffer rx/tx USB URB data */
struct usb_fifo *owner_fifo; /* pointer to owner fifo */
__u8 indx; /* Fifos's ISO double buffer 0 or 1 ? */
#ifdef ISO_FRAME_START_DEBUG
int start_frames[ISO_FRAME_START_RING_COUNT];
__u8 iso_frm_strt_pos; /* index in start_frame[] */
#endif
};
struct usb_fifo {
int fifonum; /* fifo index attached to this structure */
int active; /* fifo is currently active */
struct hfcsusb *hw; /* pointer to main structure */
int pipe; /* address of endpoint */
__u8 usb_packet_maxlen; /* maximum length for usb transfer */
unsigned int max_size; /* maximum size of receive/send packet */
__u8 intervall; /* interrupt interval */
struct urb *urb; /* transfer structure for usb routines */
__u8 buffer[128]; /* buffer USB INT OUT URB data */
int bit_line; /* how much bits are in the fifo? */
__u8 usb_transfer_mode; /* switched between ISO and INT */
struct iso_urb iso[2]; /* two urbs to have one always
one pending */
struct dchannel *dch; /* link to hfcsusb_t->dch */
struct bchannel *bch; /* link to hfcsusb_t->bch */
struct dchannel *ech; /* link to hfcsusb_t->ech, TODO: E-CHANNEL */
int last_urblen; /* remember length of last packet */
__u8 stop_gracefull; /* stops URB retransmission */
};
struct hfcsusb {
struct list_head list;
struct dchannel dch;
struct bchannel bch[2];
struct dchannel ech; /* TODO : wait for struct echannel ;) */
struct usb_device *dev; /* our device */
struct usb_interface *intf; /* used interface */
int if_used; /* used interface number */
int alt_used; /* used alternate config */
int cfg_used; /* configuration index used */
int vend_idx; /* index in hfcsusb_idtab */
int packet_size;
int iso_packet_size;
struct usb_fifo fifos[HFCUSB_NUM_FIFOS];
/* control pipe background handling */
struct ctrl_buf ctrl_buff[HFC_CTRL_BUFSIZE];
int ctrl_in_idx, ctrl_out_idx, ctrl_cnt;
struct urb *ctrl_urb;
struct usb_ctrlrequest ctrl_write;
struct usb_ctrlrequest ctrl_read;
int ctrl_paksize;
int ctrl_in_pipe, ctrl_out_pipe;
spinlock_t ctrl_lock; /* lock for ctrl */
spinlock_t lock;
__u8 threshold_mask;
__u8 led_state;
__u8 protocol;
int nt_timer;
int open;
__u8 timers;
__u8 initdone;
char name[MISDN_MAX_IDLEN];
};
/* private vendor specific data */
struct hfcsusb_vdata {
__u8 led_scheme; /* led display scheme */
signed short led_bits[8]; /* array of 8 possible LED bitmask */
char *vend_name; /* device name */
};
#define HFC_MAX_TE_LAYER1_STATE 8
#define HFC_MAX_NT_LAYER1_STATE 4
static const char *HFC_TE_LAYER1_STATES[HFC_MAX_TE_LAYER1_STATE + 1] = {
"TE F0 - Reset",
"TE F1 - Reset",
"TE F2 - Sensing",
"TE F3 - Deactivated",
"TE F4 - Awaiting signal",
"TE F5 - Identifying input",
"TE F6 - Synchronized",
"TE F7 - Activated",
"TE F8 - Lost framing",
};
static const char *HFC_NT_LAYER1_STATES[HFC_MAX_NT_LAYER1_STATE + 1] = {
"NT G0 - Reset",
"NT G1 - Deactive",
"NT G2 - Pending activation",
"NT G3 - Active",
"NT G4 - Pending deactivation",
};
/* supported devices */
static const struct usb_device_id hfcsusb_idtab[] = {
{
USB_DEVICE(0x0959, 0x2bd0),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_OFF, {4, 0, 2, 1},
"ISDN USB TA (Cologne Chip HFC-S USB based)"}),
},
{
USB_DEVICE(0x0675, 0x1688),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {1, 2, 0, 0},
"DrayTek miniVigor 128 USB ISDN TA"}),
},
{
USB_DEVICE(0x07b0, 0x0007),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {0x80, -64, -32, -16},
"Billion tiny USB ISDN TA 128"}),
},
{
USB_DEVICE(0x0742, 0x2008),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {4, 0, 2, 1},
"Stollmann USB TA"}),
},
{
USB_DEVICE(0x0742, 0x2009),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {4, 0, 2, 1},
"Aceex USB ISDN TA"}),
},
{
USB_DEVICE(0x0742, 0x200A),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {4, 0, 2, 1},
"OEM USB ISDN TA"}),
},
{
USB_DEVICE(0x08e3, 0x0301),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {2, 0, 1, 4},
"Olitec USB RNIS"}),
},
{
USB_DEVICE(0x07fa, 0x0846),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {0x80, -64, -32, -16},
"Bewan Modem RNIS USB"}),
},
{
USB_DEVICE(0x07fa, 0x0847),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {0x80, -64, -32, -16},
"Djinn Numeris USB"}),
},
{
USB_DEVICE(0x07b0, 0x0006),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {0x80, -64, -32, -16},
"Twister ISDN TA"}),
},
{
USB_DEVICE(0x071d, 0x1005),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {0x02, 0, 0x01, 0x04},
"Eicon DIVA USB 4.0"}),
},
{
USB_DEVICE(0x0586, 0x0102),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {0x88, -64, -32, -16},
"ZyXEL OMNI.NET USB II"}),
},
{
USB_DEVICE(0x1ae7, 0x0525),
.driver_info = (unsigned long) &((struct hfcsusb_vdata)
{LED_SCHEME1, {0x88, -64, -32, -16},
"X-Tensions USB ISDN TA XC-525"}),
},
{ }
};
MODULE_DEVICE_TABLE(usb, hfcsusb_idtab);
#endif /* __HFCSUSB_H__ */

96
drivers/isdn/hardware/mISDN/iohelper.h
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@ -1,96 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* iohelper.h
* helper for define functions to access ISDN hardware
* supported are memory mapped IO
* indirect port IO (one port for address, one for data)
*
* Author Karsten Keil <keil@isdn4linux.de>
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*/
#ifndef _IOHELPER_H
#define _IOHELPER_H
typedef u8 (read_reg_func)(void *hwp, u8 offset);
typedef void (write_reg_func)(void *hwp, u8 offset, u8 value);
typedef void (fifo_func)(void *hwp, u8 offset, u8 *datap, int size);
struct _ioport {
u32 port;
u32 ale;
};
#define IOFUNC_IO(name, hws, ap) \
static u8 Read##name##_IO(void *p, u8 off) { \
struct hws *hw = p; \
return inb(hw->ap.port + off); \
} \
static void Write##name##_IO(void *p, u8 off, u8 val) { \
struct hws *hw = p; \
outb(val, hw->ap.port + off); \
} \
static void ReadFiFo##name##_IO(void *p, u8 off, u8 *dp, int size) { \
struct hws *hw = p; \
insb(hw->ap.port + off, dp, size); \
} \
static void WriteFiFo##name##_IO(void *p, u8 off, u8 *dp, int size) { \
struct hws *hw = p; \
outsb(hw->ap.port + off, dp, size); \
}
#define IOFUNC_IND(name, hws, ap) \
static u8 Read##name##_IND(void *p, u8 off) { \
struct hws *hw = p; \
outb(off, hw->ap.ale); \
return inb(hw->ap.port); \
} \
static void Write##name##_IND(void *p, u8 off, u8 val) { \
struct hws *hw = p; \
outb(off, hw->ap.ale); \
outb(val, hw->ap.port); \
} \
static void ReadFiFo##name##_IND(void *p, u8 off, u8 *dp, int size) { \
struct hws *hw = p; \
outb(off, hw->ap.ale); \
insb(hw->ap.port, dp, size); \
} \
static void WriteFiFo##name##_IND(void *p, u8 off, u8 *dp, int size) { \
struct hws *hw = p; \
outb(off, hw->ap.ale); \
outsb(hw->ap.port, dp, size); \
}
#define IOFUNC_MEMIO(name, hws, typ, adr) \
static u8 Read##name##_MIO(void *p, u8 off) { \
struct hws *hw = p; \
return readb(((typ *)hw->adr) + off); \
} \
static void Write##name##_MIO(void *p, u8 off, u8 val) { \
struct hws *hw = p; \
writeb(val, ((typ *)hw->adr) + off); \
} \
static void ReadFiFo##name##_MIO(void *p, u8 off, u8 *dp, int size) { \
struct hws *hw = p; \
while (size--) \
*dp++ = readb(((typ *)hw->adr) + off); \
} \
static void WriteFiFo##name##_MIO(void *p, u8 off, u8 *dp, int size) { \
struct hws *hw = p; \
while (size--) \
writeb(*dp++, ((typ *)hw->adr) + off); \
}
#define ASSIGN_FUNC(typ, name, dest) do { \
dest.read_reg = &Read##name##_##typ; \
dest.write_reg = &Write##name##_##typ; \
dest.read_fifo = &ReadFiFo##name##_##typ; \
dest.write_fifo = &WriteFiFo##name##_##typ; \
} while (0)
#define ASSIGN_FUNC_IPAC(typ, target) do { \
ASSIGN_FUNC(typ, ISAC, target.isac); \
ASSIGN_FUNC(typ, IPAC, target); \
} while (0)
#endif

393
drivers/isdn/hardware/mISDN/ipac.h
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@ -1,393 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* ipac.h Defines for the Infineon (former Siemens) ISDN
* chip series
*
* Author Karsten Keil <keil@isdn4linux.de>
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*/
#include "iohelper.h"
struct isac_hw {
struct dchannel dch;
u32 type;
u32 off; /* offset to isac regs */
char *name;
spinlock_t *hwlock; /* lock HW access */
read_reg_func *read_reg;
write_reg_func *write_reg;
fifo_func *read_fifo;
fifo_func *write_fifo;
int (*monitor)(void *, u32, u8 *, int);
void (*release)(struct isac_hw *);
int (*init)(struct isac_hw *);
int (*ctrl)(struct isac_hw *, u32, u_long);
int (*open)(struct isac_hw *, struct channel_req *);
u8 *mon_tx;
u8 *mon_rx;
int mon_txp;
int mon_txc;
int mon_rxp;
struct arcofi_msg *arcofi_list;
struct timer_list arcofitimer;
wait_queue_head_t arcofi_wait;
u8 arcofi_bc;
u8 arcofi_state;
u8 mocr;
u8 adf2;
u8 state;
};
struct ipac_hw;
struct hscx_hw {
struct bchannel bch;
struct ipac_hw *ip;
u8 fifo_size;
u8 off; /* offset to ICA or ICB */
u8 slot;
char log[64];
};
struct ipac_hw {
struct isac_hw isac;
struct hscx_hw hscx[2];
char *name;
void *hw;
spinlock_t *hwlock; /* lock HW access */
struct module *owner;
u32 type;
read_reg_func *read_reg;
write_reg_func *write_reg;
fifo_func *read_fifo;
fifo_func *write_fifo;
void (*release)(struct ipac_hw *);
int (*init)(struct ipac_hw *);
int (*ctrl)(struct ipac_hw *, u32, u_long);
u8 conf;
};
#define IPAC_TYPE_ISAC 0x0010
#define IPAC_TYPE_IPAC 0x0020
#define IPAC_TYPE_ISACX 0x0040
#define IPAC_TYPE_IPACX 0x0080
#define IPAC_TYPE_HSCX 0x0100
#define ISAC_USE_ARCOFI 0x1000
/* Monitor functions */
#define MONITOR_RX_0 0x1000
#define MONITOR_RX_1 0x1001
#define MONITOR_TX_0 0x2000
#define MONITOR_TX_1 0x2001
/* All registers original Siemens Spec */
/* IPAC/ISAC registers */
#define ISAC_ISTA 0x20
#define ISAC_MASK 0x20
#define ISAC_CMDR 0x21
#define ISAC_STAR 0x21
#define ISAC_MODE 0x22
#define ISAC_TIMR 0x23
#define ISAC_EXIR 0x24
#define ISAC_RBCL 0x25
#define ISAC_RSTA 0x27
#define ISAC_RBCH 0x2A
#define ISAC_SPCR 0x30
#define ISAC_CIR0 0x31
#define ISAC_CIX0 0x31
#define ISAC_MOR0 0x32
#define ISAC_MOX0 0x32
#define ISAC_CIR1 0x33
#define ISAC_CIX1 0x33
#define ISAC_MOR1 0x34
#define ISAC_MOX1 0x34
#define ISAC_STCR 0x37
#define ISAC_ADF1 0x38
#define ISAC_ADF2 0x39
#define ISAC_MOCR 0x3a
#define ISAC_MOSR 0x3a
#define ISAC_SQRR 0x3b
#define ISAC_SQXR 0x3b
#define ISAC_RBCH_XAC 0x80
#define IPAC_D_TIN2 0x01
/* IPAC/HSCX */
#define IPAC_ISTAB 0x20 /* RD */
#define IPAC_MASKB 0x20 /* WR */
#define IPAC_STARB 0x21 /* RD */
#define IPAC_CMDRB 0x21 /* WR */
#define IPAC_MODEB 0x22 /* R/W */
#define IPAC_EXIRB 0x24 /* RD */
#define IPAC_RBCLB 0x25 /* RD */
#define IPAC_RAH1 0x26 /* WR */
#define IPAC_RAH2 0x27 /* WR */
#define IPAC_RSTAB 0x27 /* RD */
#define IPAC_RAL1 0x28 /* R/W */
#define IPAC_RAL2 0x29 /* WR */
#define IPAC_RHCRB 0x29 /* RD */
#define IPAC_XBCL 0x2A /* WR */
#define IPAC_CCR2 0x2C /* R/W */
#define IPAC_RBCHB 0x2D /* RD */
#define IPAC_XBCH 0x2D /* WR */
#define HSCX_VSTR 0x2E /* RD */
#define IPAC_RLCR 0x2E /* WR */
#define IPAC_CCR1 0x2F /* R/W */
#define IPAC_TSAX 0x30 /* WR */
#define IPAC_TSAR 0x31 /* WR */
#define IPAC_XCCR 0x32 /* WR */
#define IPAC_RCCR 0x33 /* WR */
/* IPAC_ISTAB/IPAC_MASKB bits */
#define IPAC_B_XPR 0x10
#define IPAC_B_RPF 0x40
#define IPAC_B_RME 0x80
#define IPAC_B_ON 0x2F
/* IPAC_EXIRB bits */
#define IPAC_B_RFS 0x04
#define IPAC_B_RFO 0x10
#define IPAC_B_XDU 0x40
#define IPAC_B_XMR 0x80
/* IPAC special registers */
#define IPAC_CONF 0xC0 /* R/W */
#define IPAC_ISTA 0xC1 /* RD */
#define IPAC_MASK 0xC1 /* WR */
#define IPAC_ID 0xC2 /* RD */
#define IPAC_ACFG 0xC3 /* R/W */
#define IPAC_AOE 0xC4 /* R/W */
#define IPAC_ARX 0xC5 /* RD */
#define IPAC_ATX 0xC5 /* WR */
#define IPAC_PITA1 0xC6 /* R/W */
#define IPAC_PITA2 0xC7 /* R/W */
#define IPAC_POTA1 0xC8 /* R/W */
#define IPAC_POTA2 0xC9 /* R/W */
#define IPAC_PCFG 0xCA /* R/W */
#define IPAC_SCFG 0xCB /* R/W */
#define IPAC_TIMR2 0xCC /* R/W */
/* IPAC_ISTA/_MASK bits */
#define IPAC__EXB 0x01
#define IPAC__ICB 0x02
#define IPAC__EXA 0x04
#define IPAC__ICA 0x08
#define IPAC__EXD 0x10
#define IPAC__ICD 0x20
#define IPAC__INT0 0x40
#define IPAC__INT1 0x80
#define IPAC__ON 0xC0
/* HSCX ISTA/MASK bits */
#define HSCX__EXB 0x01
#define HSCX__EXA 0x02
#define HSCX__ICA 0x04
/* ISAC/ISACX/IPAC/IPACX L1 commands */
#define ISAC_CMD_TIM 0x0
#define ISAC_CMD_RS 0x1
#define ISAC_CMD_SCZ 0x4
#define ISAC_CMD_SSZ 0x2
#define ISAC_CMD_AR8 0x8
#define ISAC_CMD_AR10 0x9
#define ISAC_CMD_ARL 0xA
#define ISAC_CMD_DUI 0xF
/* ISAC/ISACX/IPAC/IPACX L1 indications */
#define ISAC_IND_DR 0x0
#define ISAC_IND_RS 0x1
#define ISAC_IND_SD 0x2
#define ISAC_IND_DIS 0x3
#define ISAC_IND_RSY 0x4
#define ISAC_IND_DR6 0x5
#define ISAC_IND_EI 0x6
#define ISAC_IND_PU 0x7
#define ISAC_IND_ARD 0x8
#define ISAC_IND_TI 0xA
#define ISAC_IND_ATI 0xB
#define ISAC_IND_AI8 0xC
#define ISAC_IND_AI10 0xD
#define ISAC_IND_DID 0xF
/* the new ISACX / IPACX */
/* D-channel registers */
#define ISACX_RFIFOD 0x00 /* RD */
#define ISACX_XFIFOD 0x00 /* WR */
#define ISACX_ISTAD 0x20 /* RD */
#define ISACX_MASKD 0x20 /* WR */
#define ISACX_STARD 0x21 /* RD */
#define ISACX_CMDRD 0x21 /* WR */
#define ISACX_MODED 0x22 /* R/W */
#define ISACX_EXMD1 0x23 /* R/W */
#define ISACX_TIMR1 0x24 /* R/W */
#define ISACX_SAP1 0x25 /* WR */
#define ISACX_SAP2 0x26 /* WR */
#define ISACX_RBCLD 0x26 /* RD */
#define ISACX_RBCHD 0x27 /* RD */
#define ISACX_TEI1 0x27 /* WR */
#define ISACX_TEI2 0x28 /* WR */
#define ISACX_RSTAD 0x28 /* RD */
#define ISACX_TMD 0x29 /* R/W */
#define ISACX_CIR0 0x2E /* RD */
#define ISACX_CIX0 0x2E /* WR */
#define ISACX_CIR1 0x2F /* RD */
#define ISACX_CIX1 0x2F /* WR */
/* Transceiver registers */
#define ISACX_TR_CONF0 0x30 /* R/W */
#define ISACX_TR_CONF1 0x31 /* R/W */
#define ISACX_TR_CONF2 0x32 /* R/W */
#define ISACX_TR_STA 0x33 /* RD */
#define ISACX_TR_CMD 0x34 /* R/W */
#define ISACX_SQRR1 0x35 /* RD */
#define ISACX_SQXR1 0x35 /* WR */
#define ISACX_SQRR2 0x36 /* RD */
#define ISACX_SQXR2 0x36 /* WR */
#define ISACX_SQRR3 0x37 /* RD */
#define ISACX_SQXR3 0x37 /* WR */
#define ISACX_ISTATR 0x38 /* RD */
#define ISACX_MASKTR 0x39 /* R/W */
#define ISACX_TR_MODE 0x3A /* R/W */
#define ISACX_ACFG1 0x3C /* R/W */
#define ISACX_ACFG2 0x3D /* R/W */
#define ISACX_AOE 0x3E /* R/W */
#define ISACX_ARX 0x3F /* RD */
#define ISACX_ATX 0x3F /* WR */
/* IOM: Timeslot, DPS, CDA */
#define ISACX_CDA10 0x40 /* R/W */
#define ISACX_CDA11 0x41 /* R/W */
#define ISACX_CDA20 0x42 /* R/W */
#define ISACX_CDA21 0x43 /* R/W */
#define ISACX_CDA_TSDP10 0x44 /* R/W */
#define ISACX_CDA_TSDP11 0x45 /* R/W */
#define ISACX_CDA_TSDP20 0x46 /* R/W */
#define ISACX_CDA_TSDP21 0x47 /* R/W */
#define ISACX_BCHA_TSDP_BC1 0x48 /* R/W */
#define ISACX_BCHA_TSDP_BC2 0x49 /* R/W */
#define ISACX_BCHB_TSDP_BC1 0x4A /* R/W */
#define ISACX_BCHB_TSDP_BC2 0x4B /* R/W */
#define ISACX_TR_TSDP_BC1 0x4C /* R/W */
#define ISACX_TR_TSDP_BC2 0x4D /* R/W */
#define ISACX_CDA1_CR 0x4E /* R/W */
#define ISACX_CDA2_CR 0x4F /* R/W */
/* IOM: Contol, Sync transfer, Monitor */
#define ISACX_TR_CR 0x50 /* R/W */
#define ISACX_TRC_CR 0x50 /* R/W */
#define ISACX_BCHA_CR 0x51 /* R/W */
#define ISACX_BCHB_CR 0x52 /* R/W */
#define ISACX_DCI_CR 0x53 /* R/W */
#define ISACX_DCIC_CR 0x53 /* R/W */
#define ISACX_MON_CR 0x54 /* R/W */
#define ISACX_SDS1_CR 0x55 /* R/W */
#define ISACX_SDS2_CR 0x56 /* R/W */
#define ISACX_IOM_CR 0x57 /* R/W */
#define ISACX_STI 0x58 /* RD */
#define ISACX_ASTI 0x58 /* WR */
#define ISACX_MSTI 0x59 /* R/W */
#define ISACX_SDS_CONF 0x5A /* R/W */
#define ISACX_MCDA 0x5B /* RD */
#define ISACX_MOR 0x5C /* RD */
#define ISACX_MOX 0x5C /* WR */
#define ISACX_MOSR 0x5D /* RD */
#define ISACX_MOCR 0x5E /* R/W */
#define ISACX_MSTA 0x5F /* RD */
#define ISACX_MCONF 0x5F /* WR */
/* Interrupt and general registers */
#define ISACX_ISTA 0x60 /* RD */
#define ISACX_MASK 0x60 /* WR */
#define ISACX_AUXI 0x61 /* RD */
#define ISACX_AUXM 0x61 /* WR */
#define ISACX_MODE1 0x62 /* R/W */
#define ISACX_MODE2 0x63 /* R/W */
#define ISACX_ID 0x64 /* RD */
#define ISACX_SRES 0x64 /* WR */
#define ISACX_TIMR2 0x65 /* R/W */
/* Register Bits */
/* ISACX/IPACX _ISTAD (R) and _MASKD (W) */
#define ISACX_D_XDU 0x04
#define ISACX_D_XMR 0x08
#define ISACX_D_XPR 0x10
#define ISACX_D_RFO 0x20
#define ISACX_D_RPF 0x40
#define ISACX_D_RME 0x80
/* ISACX/IPACX _ISTA (R) and _MASK (W) */
#define ISACX__ICD 0x01
#define ISACX__MOS 0x02
#define ISACX__TRAN 0x04
#define ISACX__AUX 0x08
#define ISACX__CIC 0x10
#define ISACX__ST 0x20
#define IPACX__ON 0x2C
#define IPACX__ICB 0x40
#define IPACX__ICA 0x80
/* ISACX/IPACX _CMDRD (W) */
#define ISACX_CMDRD_XRES 0x01
#define ISACX_CMDRD_XME 0x02
#define ISACX_CMDRD_XTF 0x08
#define ISACX_CMDRD_STI 0x10
#define ISACX_CMDRD_RRES 0x40
#define ISACX_CMDRD_RMC 0x80
/* ISACX/IPACX _RSTAD (R) */
#define ISACX_RSTAD_TA 0x01
#define ISACX_RSTAD_CR 0x02
#define ISACX_RSTAD_SA0 0x04
#define ISACX_RSTAD_SA1 0x08
#define ISACX_RSTAD_RAB 0x10
#define ISACX_RSTAD_CRC 0x20
#define ISACX_RSTAD_RDO 0x40
#define ISACX_RSTAD_VFR 0x80
/* ISACX/IPACX _CIR0 (R) */
#define ISACX_CIR0_BAS 0x01
#define ISACX_CIR0_SG 0x08
#define ISACX_CIR0_CIC1 0x08
#define ISACX_CIR0_CIC0 0x08
/* B-channel registers */
#define IPACX_OFF_ICA 0x70
#define IPACX_OFF_ICB 0x80
/* ICA: IPACX_OFF_ICA + Reg ICB: IPACX_OFF_ICB + Reg */
#define IPACX_ISTAB 0x00 /* RD */
#define IPACX_MASKB 0x00 /* WR */
#define IPACX_STARB 0x01 /* RD */
#define IPACX_CMDRB 0x01 /* WR */
#define IPACX_MODEB 0x02 /* R/W */
#define IPACX_EXMB 0x03 /* R/W */
#define IPACX_RAH1 0x05 /* WR */
#define IPACX_RAH2 0x06 /* WR */
#define IPACX_RBCLB 0x06 /* RD */
#define IPACX_RBCHB 0x07 /* RD */
#define IPACX_RAL1 0x07 /* WR */
#define IPACX_RAL2 0x08 /* WR */
#define IPACX_RSTAB 0x08 /* RD */
#define IPACX_TMB 0x09 /* R/W */
#define IPACX_RFIFOB 0x0A /* RD */
#define IPACX_XFIFOB 0x0A /* WR */
/* IPACX_ISTAB / IPACX_MASKB bits */
#define IPACX_B_XDU 0x04
#define IPACX_B_XPR 0x10
#define IPACX_B_RFO 0x20
#define IPACX_B_RPF 0x40
#define IPACX_B_RME 0x80
#define IPACX_B_ON 0x0B
extern int mISDNisac_init(struct isac_hw *, void *);
extern irqreturn_t mISDNisac_irq(struct isac_hw *, u8);
extern u32 mISDNipac_init(struct ipac_hw *, void *);
extern irqreturn_t mISDNipac_irq(struct ipac_hw *, int);

256
drivers/isdn/hardware/mISDN/isar.h
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@ -1,256 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* isar.h ISAR (Siemens PSB 7110) specific defines
*
* Author Karsten Keil (keil@isdn4linux.de)
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*/
#include "iohelper.h"
struct isar_hw;
struct isar_ch {
struct bchannel bch;
struct isar_hw *is;
struct timer_list ftimer;
u8 nr;
u8 dpath;
u8 mml;
u8 state;
u8 cmd;
u8 mod;
u8 newcmd;
u8 newmod;
u8 try_mod;
u8 conmsg[16];
};
struct isar_hw {
struct isar_ch ch[2];
void *hw;
spinlock_t *hwlock; /* lock HW access */
char *name;
struct module *owner;
read_reg_func *read_reg;
write_reg_func *write_reg;
fifo_func *read_fifo;
fifo_func *write_fifo;
int (*ctrl)(void *, u32, u_long);
void (*release)(struct isar_hw *);
int (*init)(struct isar_hw *);
int (*open)(struct isar_hw *, struct channel_req *);
int (*firmware)(struct isar_hw *, const u8 *, int);
unsigned long Flags;
int version;
u8 bstat;
u8 iis;
u8 cmsb;
u8 clsb;
u8 buf[256];
u8 log[256];
};
#define ISAR_IRQMSK 0x04
#define ISAR_IRQSTA 0x04
#define ISAR_IRQBIT 0x75
#define ISAR_CTRL_H 0x61
#define ISAR_CTRL_L 0x60
#define ISAR_IIS 0x58
#define ISAR_IIA 0x58
#define ISAR_HIS 0x50
#define ISAR_HIA 0x50
#define ISAR_MBOX 0x4c
#define ISAR_WADR 0x4a
#define ISAR_RADR 0x48
#define ISAR_HIS_VNR 0x14
#define ISAR_HIS_DKEY 0x02
#define ISAR_HIS_FIRM 0x1e
#define ISAR_HIS_STDSP 0x08
#define ISAR_HIS_DIAG 0x05
#define ISAR_HIS_P0CFG 0x3c
#define ISAR_HIS_P12CFG 0x24
#define ISAR_HIS_SARTCFG 0x25
#define ISAR_HIS_PUMPCFG 0x26
#define ISAR_HIS_PUMPCTRL 0x2a
#define ISAR_HIS_IOM2CFG 0x27
#define ISAR_HIS_IOM2REQ 0x07
#define ISAR_HIS_IOM2CTRL 0x2b
#define ISAR_HIS_BSTREQ 0x0c
#define ISAR_HIS_PSTREQ 0x0e
#define ISAR_HIS_SDATA 0x20
#define ISAR_HIS_DPS1 0x40
#define ISAR_HIS_DPS2 0x80
#define SET_DPS(x) ((x << 6) & 0xc0)
#define ISAR_IIS_MSCMSD 0x3f
#define ISAR_IIS_VNR 0x15
#define ISAR_IIS_DKEY 0x03
#define ISAR_IIS_FIRM 0x1f
#define ISAR_IIS_STDSP 0x09
#define ISAR_IIS_DIAG 0x25
#define ISAR_IIS_GSTEV 0x00
#define ISAR_IIS_BSTEV 0x28
#define ISAR_IIS_BSTRSP 0x2c
#define ISAR_IIS_PSTRSP 0x2e
#define ISAR_IIS_PSTEV 0x2a
#define ISAR_IIS_IOM2RSP 0x27
#define ISAR_IIS_RDATA 0x20
#define ISAR_IIS_INVMSG 0x3f
#define ISAR_CTRL_SWVER 0x10
#define ISAR_CTRL_STST 0x40
#define ISAR_MSG_HWVER 0x20
#define ISAR_DP1_USE 1
#define ISAR_DP2_USE 2
#define ISAR_RATE_REQ 3
#define PMOD_DISABLE 0
#define PMOD_FAX 1
#define PMOD_DATAMODEM 2
#define PMOD_HALFDUPLEX 3
#define PMOD_V110 4
#define PMOD_DTMF 5
#define PMOD_DTMF_TRANS 6
#define PMOD_BYPASS 7
#define PCTRL_ORIG 0x80
#define PV32P2_V23R 0x40
#define PV32P2_V22A 0x20
#define PV32P2_V22B 0x10
#define PV32P2_V22C 0x08
#define PV32P2_V21 0x02
#define PV32P2_BEL 0x01
/* LSB MSB in ISAR doc wrong !!! Arghhh */
#define PV32P3_AMOD 0x80
#define PV32P3_V32B 0x02
#define PV32P3_V23B 0x01
#define PV32P4_48 0x11
#define PV32P5_48 0x05
#define PV32P4_UT48 0x11
#define PV32P5_UT48 0x0d
#define PV32P4_96 0x11
#define PV32P5_96 0x03
#define PV32P4_UT96 0x11
#define PV32P5_UT96 0x0f
#define PV32P4_B96 0x91
#define PV32P5_B96 0x0b
#define PV32P4_UTB96 0xd1
#define PV32P5_UTB96 0x0f
#define PV32P4_120 0xb1
#define PV32P5_120 0x09
#define PV32P4_UT120 0xf1
#define PV32P5_UT120 0x0f
#define PV32P4_144 0x99
#define PV32P5_144 0x09
#define PV32P4_UT144 0xf9
#define PV32P5_UT144 0x0f
#define PV32P6_CTN 0x01
#define PV32P6_ATN 0x02
#define PFAXP2_CTN 0x01
#define PFAXP2_ATN 0x04
#define PSEV_10MS_TIMER 0x02
#define PSEV_CON_ON 0x18
#define PSEV_CON_OFF 0x19
#define PSEV_V24_OFF 0x20
#define PSEV_CTS_ON 0x21
#define PSEV_CTS_OFF 0x22
#define PSEV_DCD_ON 0x23
#define PSEV_DCD_OFF 0x24
#define PSEV_DSR_ON 0x25
#define PSEV_DSR_OFF 0x26
#define PSEV_REM_RET 0xcc
#define PSEV_REM_REN 0xcd
#define PSEV_GSTN_CLR 0xd4
#define PSEV_RSP_READY 0xbc
#define PSEV_LINE_TX_H 0xb3
#define PSEV_LINE_TX_B 0xb2
#define PSEV_LINE_RX_H 0xb1
#define PSEV_LINE_RX_B 0xb0
#define PSEV_RSP_CONN 0xb5
#define PSEV_RSP_DISC 0xb7
#define PSEV_RSP_FCERR 0xb9
#define PSEV_RSP_SILDET 0xbe
#define PSEV_RSP_SILOFF 0xab
#define PSEV_FLAGS_DET 0xba
#define PCTRL_CMD_TDTMF 0x5a
#define PCTRL_CMD_FTH 0xa7
#define PCTRL_CMD_FRH 0xa5
#define PCTRL_CMD_FTM 0xa8
#define PCTRL_CMD_FRM 0xa6
#define PCTRL_CMD_SILON 0xac
#define PCTRL_CMD_CONT 0xa2
#define PCTRL_CMD_ESC 0xa4
#define PCTRL_CMD_SILOFF 0xab
#define PCTRL_CMD_HALT 0xa9
#define PCTRL_LOC_RET 0xcf
#define PCTRL_LOC_REN 0xce
#define SMODE_DISABLE 0
#define SMODE_V14 2
#define SMODE_HDLC 3
#define SMODE_BINARY 4
#define SMODE_FSK_V14 5
#define SCTRL_HDMC_BOTH 0x00
#define SCTRL_HDMC_DTX 0x80
#define SCTRL_HDMC_DRX 0x40
#define S_P1_OVSP 0x40
#define S_P1_SNP 0x20
#define S_P1_EOP 0x10
#define S_P1_EDP 0x08
#define S_P1_NSB 0x04
#define S_P1_CHS_8 0x03
#define S_P1_CHS_7 0x02
#define S_P1_CHS_6 0x01
#define S_P1_CHS_5 0x00
#define S_P2_BFT_DEF 0x10
#define IOM_CTRL_ENA 0x80
#define IOM_CTRL_NOPCM 0x00
#define IOM_CTRL_ALAW 0x02
#define IOM_CTRL_ULAW 0x04
#define IOM_CTRL_RCV 0x01
#define IOM_P1_TXD 0x10
#define HDLC_FED 0x40
#define HDLC_FSD 0x20
#define HDLC_FST 0x20
#define HDLC_ERROR 0x1c
#define HDLC_ERR_FAD 0x10
#define HDLC_ERR_RER 0x08
#define HDLC_ERR_CER 0x04
#define SART_NMD 0x01
#define BSTAT_RDM0 0x1
#define BSTAT_RDM1 0x2
#define BSTAT_RDM2 0x4
#define BSTAT_RDM3 0x8
#define BSTEV_TBO 0x1f
#define BSTEV_RBO 0x2f
/* FAX State Machine */
#define STFAX_NULL 0
#define STFAX_READY 1
#define STFAX_LINE 2
#define STFAX_CONT 3
#define STFAX_ACTIV 4
#define STFAX_ESCAPE 5
#define STFAX_SILDET 6
extern u32 mISDNisar_init(struct isar_hw *, void *);
extern void mISDNisar_irq(struct isar_hw *);

617
drivers/isdn/hardware/mISDN/isdnhdlc.c
View File

@ -1,617 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* isdnhdlc.c -- General purpose ISDN HDLC decoder.
*
* Copyright (C)
* 2009 Karsten Keil <keil@b1-systems.de>
* 2002 Wolfgang Mües <wolfgang@iksw-muees.de>
* 2001 Frode Isaksen <fisaksen@bewan.com>
* 2001 Kai Germaschewski <kai.germaschewski@gmx.de>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/crc-ccitt.h>
#include <linux/bitrev.h>
#include "isdnhdlc.h"
/*-------------------------------------------------------------------*/
MODULE_AUTHOR("Wolfgang Mües <wolfgang@iksw-muees.de>, "
"Frode Isaksen <fisaksen@bewan.com>, "
"Kai Germaschewski <kai.germaschewski@gmx.de>");
MODULE_DESCRIPTION("General purpose ISDN HDLC decoder");
MODULE_LICENSE("GPL");
/*-------------------------------------------------------------------*/
enum {
HDLC_FAST_IDLE, HDLC_GET_FLAG_B0, HDLC_GETFLAG_B1A6, HDLC_GETFLAG_B7,
HDLC_GET_DATA, HDLC_FAST_FLAG
};
enum {
HDLC_SEND_DATA, HDLC_SEND_CRC1, HDLC_SEND_FAST_FLAG,
HDLC_SEND_FIRST_FLAG, HDLC_SEND_CRC2, HDLC_SEND_CLOSING_FLAG,
HDLC_SEND_IDLE1, HDLC_SEND_FAST_IDLE, HDLC_SENDFLAG_B0,
HDLC_SENDFLAG_B1A6, HDLC_SENDFLAG_B7, STOPPED, HDLC_SENDFLAG_ONE
};
void isdnhdlc_rcv_init(struct isdnhdlc_vars *hdlc, u32 features)
{
memset(hdlc, 0, sizeof(struct isdnhdlc_vars));
hdlc->state = HDLC_GET_DATA;
if (features & HDLC_56KBIT)
hdlc->do_adapt56 = 1;
if (features & HDLC_BITREVERSE)
hdlc->do_bitreverse = 1;
}
EXPORT_SYMBOL(isdnhdlc_out_init);
void isdnhdlc_out_init(struct isdnhdlc_vars *hdlc, u32 features)
{
memset(hdlc, 0, sizeof(struct isdnhdlc_vars));
if (features & HDLC_DCHANNEL) {
hdlc->dchannel = 1;
hdlc->state = HDLC_SEND_FIRST_FLAG;
} else {
hdlc->dchannel = 0;
hdlc->state = HDLC_SEND_FAST_FLAG;
hdlc->ffvalue = 0x7e;
}
hdlc->cbin = 0x7e;
if (features & HDLC_56KBIT) {
hdlc->do_adapt56 = 1;
hdlc->state = HDLC_SENDFLAG_B0;
} else
hdlc->data_bits = 8;
if (features & HDLC_BITREVERSE)
hdlc->do_bitreverse = 1;
}
EXPORT_SYMBOL(isdnhdlc_rcv_init);
static int
check_frame(struct isdnhdlc_vars *hdlc)
{
int status;
if (hdlc->dstpos < 2) /* too small - framing error */
status = -HDLC_FRAMING_ERROR;
else if (hdlc->crc != 0xf0b8) /* crc error */
status = -HDLC_CRC_ERROR;
else {
/* remove CRC */
hdlc->dstpos -= 2;
/* good frame */
status = hdlc->dstpos;
}
return status;
}
/*
isdnhdlc_decode - decodes HDLC frames from a transparent bit stream.
The source buffer is scanned for valid HDLC frames looking for
flags (01111110) to indicate the start of a frame. If the start of
the frame is found, the bit stuffing is removed (0 after 5 1's).
When a new flag is found, the complete frame has been received
and the CRC is checked.
If a valid frame is found, the function returns the frame length
excluding the CRC with the bit HDLC_END_OF_FRAME set.
If the beginning of a valid frame is found, the function returns
the length.
If a framing error is found (too many 1s and not a flag) the function
returns the length with the bit HDLC_FRAMING_ERROR set.
If a CRC error is found the function returns the length with the
bit HDLC_CRC_ERROR set.
If the frame length exceeds the destination buffer size, the function
returns the length with the bit HDLC_LENGTH_ERROR set.
src - source buffer
slen - source buffer length
count - number of bytes removed (decoded) from the source buffer
dst _ destination buffer
dsize - destination buffer size
returns - number of decoded bytes in the destination buffer and status
flag.
*/
int isdnhdlc_decode(struct isdnhdlc_vars *hdlc, const u8 *src, int slen,
int *count, u8 *dst, int dsize)
{
int status = 0;
static const unsigned char fast_flag[] = {
0x00, 0x00, 0x00, 0x20, 0x30, 0x38, 0x3c, 0x3e, 0x3f
};
static const unsigned char fast_flag_value[] = {
0x00, 0x7e, 0xfc, 0xf9, 0xf3, 0xe7, 0xcf, 0x9f, 0x3f
};
static const unsigned char fast_abort[] = {
0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff
};
#define handle_fast_flag(h) \
do { \
if (h->cbin == fast_flag[h->bit_shift]) { \
h->ffvalue = fast_flag_value[h->bit_shift]; \
h->state = HDLC_FAST_FLAG; \
h->ffbit_shift = h->bit_shift; \
h->bit_shift = 1; \
} else { \
h->state = HDLC_GET_DATA; \
h->data_received = 0; \
} \
} while (0)
#define handle_abort(h) \
do { \
h->shift_reg = fast_abort[h->ffbit_shift - 1]; \
h->hdlc_bits1 = h->ffbit_shift - 2; \
if (h->hdlc_bits1 < 0) \
h->hdlc_bits1 = 0; \
h->data_bits = h->ffbit_shift - 1; \
h->state = HDLC_GET_DATA; \
h->data_received = 0; \
} while (0)
*count = slen;
while (slen > 0) {
if (hdlc->bit_shift == 0) {
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
hdlc->cbin = bitrev8(*src++);
else
hdlc->cbin = *src++;
slen--;
hdlc->bit_shift = 8;
if (hdlc->do_adapt56)
hdlc->bit_shift--;
}
switch (hdlc->state) {
case STOPPED:
return 0;
case HDLC_FAST_IDLE:
if (hdlc->cbin == 0xff) {
hdlc->bit_shift = 0;
break;
}
hdlc->state = HDLC_GET_FLAG_B0;
hdlc->hdlc_bits1 = 0;
hdlc->bit_shift = 8;
break;
case HDLC_GET_FLAG_B0:
if (!(hdlc->cbin & 0x80)) {
hdlc->state = HDLC_GETFLAG_B1A6;
hdlc->hdlc_bits1 = 0;
} else {
if ((!hdlc->do_adapt56) &&
(++hdlc->hdlc_bits1 >= 8) &&
(hdlc->bit_shift == 1))
hdlc->state = HDLC_FAST_IDLE;
}
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GETFLAG_B1A6:
if (hdlc->cbin & 0x80) {
hdlc->hdlc_bits1++;
if (hdlc->hdlc_bits1 == 6)
hdlc->state = HDLC_GETFLAG_B7;
} else
hdlc->hdlc_bits1 = 0;
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GETFLAG_B7:
if (hdlc->cbin & 0x80) {
hdlc->state = HDLC_GET_FLAG_B0;
} else {
hdlc->state = HDLC_GET_DATA;
hdlc->crc = 0xffff;
hdlc->shift_reg = 0;
hdlc->hdlc_bits1 = 0;
hdlc->data_bits = 0;
hdlc->data_received = 0;
}
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GET_DATA:
if (hdlc->cbin & 0x80) {
hdlc->hdlc_bits1++;
switch (hdlc->hdlc_bits1) {
case 6:
break;
case 7:
if (hdlc->data_received)
/* bad frame */
status = -HDLC_FRAMING_ERROR;
if (!hdlc->do_adapt56) {
if (hdlc->cbin == fast_abort
[hdlc->bit_shift + 1]) {
hdlc->state =
HDLC_FAST_IDLE;
hdlc->bit_shift = 1;
break;
}
} else
hdlc->state = HDLC_GET_FLAG_B0;
break;
default:
hdlc->shift_reg >>= 1;
hdlc->shift_reg |= 0x80;
hdlc->data_bits++;
break;
}
} else {
switch (hdlc->hdlc_bits1) {
case 5:
break;
case 6:
if (hdlc->data_received)
status = check_frame(hdlc);
hdlc->crc = 0xffff;
hdlc->shift_reg = 0;
hdlc->data_bits = 0;
if (!hdlc->do_adapt56)
handle_fast_flag(hdlc);
else {
hdlc->state = HDLC_GET_DATA;
hdlc->data_received = 0;
}
break;
default:
hdlc->shift_reg >>= 1;
hdlc->data_bits++;
break;
}
hdlc->hdlc_bits1 = 0;
}
if (status) {
hdlc->dstpos = 0;
*count -= slen;
hdlc->cbin <<= 1;
hdlc->bit_shift--;
return status;
}
if (hdlc->data_bits == 8) {
hdlc->data_bits = 0;
hdlc->data_received = 1;
hdlc->crc = crc_ccitt_byte(hdlc->crc,
hdlc->shift_reg);
/* good byte received */
if (hdlc->dstpos < dsize)
dst[hdlc->dstpos++] = hdlc->shift_reg;
else {
/* frame too long */
status = -HDLC_LENGTH_ERROR;
hdlc->dstpos = 0;
}
}
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_FAST_FLAG:
if (hdlc->cbin == hdlc->ffvalue) {
hdlc->bit_shift = 0;
break;
} else {
if (hdlc->cbin == 0xff) {
hdlc->state = HDLC_FAST_IDLE;
hdlc->bit_shift = 0;
} else if (hdlc->ffbit_shift == 8) {
hdlc->state = HDLC_GETFLAG_B7;
break;
} else
handle_abort(hdlc);
}
break;
default:
break;
}
}
*count -= slen;
return 0;
}
EXPORT_SYMBOL(isdnhdlc_decode);
/*
isdnhdlc_encode - encodes HDLC frames to a transparent bit stream.
The bit stream starts with a beginning flag (01111110). After
that each byte is added to the bit stream with bit stuffing added
(0 after 5 1's).
When the last byte has been removed from the source buffer, the
CRC (2 bytes is added) and the frame terminates with the ending flag.
For the dchannel, the idle character (all 1's) is also added at the end.
If this function is called with empty source buffer (slen=0), flags or
idle character will be generated.
src - source buffer
slen - source buffer length
count - number of bytes removed (encoded) from source buffer
dst _ destination buffer
dsize - destination buffer size
returns - number of encoded bytes in the destination buffer
*/
int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const u8 *src, u16 slen,
int *count, u8 *dst, int dsize)
{
static const unsigned char xfast_flag_value[] = {
0x7e, 0x3f, 0x9f, 0xcf, 0xe7, 0xf3, 0xf9, 0xfc, 0x7e
};
int len = 0;
*count = slen;
/* special handling for one byte frames */
if ((slen == 1) && (hdlc->state == HDLC_SEND_FAST_FLAG))
hdlc->state = HDLC_SENDFLAG_ONE;
while (dsize > 0) {
if (hdlc->bit_shift == 0) {
if (slen && !hdlc->do_closing) {
hdlc->shift_reg = *src++;
slen--;
if (slen == 0)
/* closing sequence, CRC + flag(s) */
hdlc->do_closing = 1;
hdlc->bit_shift = 8;
} else {
if (hdlc->state == HDLC_SEND_DATA) {
if (hdlc->data_received) {
hdlc->state = HDLC_SEND_CRC1;
hdlc->crc ^= 0xffff;
hdlc->bit_shift = 8;
hdlc->shift_reg =
hdlc->crc & 0xff;
} else if (!hdlc->do_adapt56)
hdlc->state =
HDLC_SEND_FAST_FLAG;
else
hdlc->state =
HDLC_SENDFLAG_B0;
}
}
}
switch (hdlc->state) {
case STOPPED:
while (dsize--)
*dst++ = 0xff;
return dsize;
case HDLC_SEND_FAST_FLAG:
hdlc->do_closing = 0;
if (slen == 0) {
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
*dst++ = bitrev8(hdlc->ffvalue);
else
*dst++ = hdlc->ffvalue;
len++;
dsize--;
break;
}
fallthrough;
case HDLC_SENDFLAG_ONE:
if (hdlc->bit_shift == 8) {
hdlc->cbin = hdlc->ffvalue >>
(8 - hdlc->data_bits);
hdlc->state = HDLC_SEND_DATA;
hdlc->crc = 0xffff;
hdlc->hdlc_bits1 = 0;
hdlc->data_received = 1;
}
break;
case HDLC_SENDFLAG_B0:
hdlc->do_closing = 0;
hdlc->cbin <<= 1;
hdlc->data_bits++;
hdlc->hdlc_bits1 = 0;
hdlc->state = HDLC_SENDFLAG_B1A6;
break;
case HDLC_SENDFLAG_B1A6:
hdlc->cbin <<= 1;
hdlc->data_bits++;
hdlc->cbin++;
if (++hdlc->hdlc_bits1 == 6)
hdlc->state = HDLC_SENDFLAG_B7;
break;
case HDLC_SENDFLAG_B7:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if (slen == 0) {
hdlc->state = HDLC_SENDFLAG_B0;
break;
}
if (hdlc->bit_shift == 8) {
hdlc->state = HDLC_SEND_DATA;
hdlc->crc = 0xffff;
hdlc->hdlc_bits1 = 0;
hdlc->data_received = 1;
}
break;
case HDLC_SEND_FIRST_FLAG:
hdlc->data_received = 1;
if (hdlc->data_bits == 8) {
hdlc->state = HDLC_SEND_DATA;
hdlc->crc = 0xffff;
hdlc->hdlc_bits1 = 0;
break;
}
hdlc->cbin <<= 1;
hdlc->data_bits++;
if (hdlc->shift_reg & 0x01)
hdlc->cbin++;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
if (hdlc->bit_shift == 0) {
hdlc->state = HDLC_SEND_DATA;
hdlc->crc = 0xffff;
hdlc->hdlc_bits1 = 0;
}
break;
case HDLC_SEND_DATA:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if (hdlc->hdlc_bits1 == 5) {
hdlc->hdlc_bits1 = 0;
break;
}
if (hdlc->bit_shift == 8)
hdlc->crc = crc_ccitt_byte(hdlc->crc,
hdlc->shift_reg);
if (hdlc->shift_reg & 0x01) {
hdlc->hdlc_bits1++;
hdlc->cbin++;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
} else {
hdlc->hdlc_bits1 = 0;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
}
break;
case HDLC_SEND_CRC1:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if (hdlc->hdlc_bits1 == 5) {
hdlc->hdlc_bits1 = 0;
break;
}
if (hdlc->shift_reg & 0x01) {
hdlc->hdlc_bits1++;
hdlc->cbin++;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
} else {
hdlc->hdlc_bits1 = 0;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
}
if (hdlc->bit_shift == 0) {
hdlc->shift_reg = (hdlc->crc >> 8);
hdlc->state = HDLC_SEND_CRC2;
hdlc->bit_shift = 8;
}
break;
case HDLC_SEND_CRC2:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if (hdlc->hdlc_bits1 == 5) {
hdlc->hdlc_bits1 = 0;
break;
}
if (hdlc->shift_reg & 0x01) {
hdlc->hdlc_bits1++;
hdlc->cbin++;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
} else {
hdlc->hdlc_bits1 = 0;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
}
if (hdlc->bit_shift == 0) {
hdlc->shift_reg = 0x7e;
hdlc->state = HDLC_SEND_CLOSING_FLAG;
hdlc->bit_shift = 8;
}
break;
case HDLC_SEND_CLOSING_FLAG:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if (hdlc->hdlc_bits1 == 5) {
hdlc->hdlc_bits1 = 0;
break;
}
if (hdlc->shift_reg & 0x01)
hdlc->cbin++;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
if (hdlc->bit_shift == 0) {
hdlc->ffvalue =
xfast_flag_value[hdlc->data_bits];
if (hdlc->dchannel) {
hdlc->ffvalue = 0x7e;
hdlc->state = HDLC_SEND_IDLE1;
hdlc->bit_shift = 8-hdlc->data_bits;
if (hdlc->bit_shift == 0)
hdlc->state =
HDLC_SEND_FAST_IDLE;
} else {
if (!hdlc->do_adapt56) {
hdlc->state =
HDLC_SEND_FAST_FLAG;
hdlc->data_received = 0;
} else {
hdlc->state = HDLC_SENDFLAG_B0;
hdlc->data_received = 0;
}
/* Finished this frame, send flags */
if (dsize > 1)
dsize = 1;
}
}
break;
case HDLC_SEND_IDLE1:
hdlc->do_closing = 0;
hdlc->cbin <<= 1;
hdlc->cbin++;
hdlc->data_bits++;
hdlc->bit_shift--;
if (hdlc->bit_shift == 0) {
hdlc->state = HDLC_SEND_FAST_IDLE;
hdlc->bit_shift = 0;
}
break;
case HDLC_SEND_FAST_IDLE:
hdlc->do_closing = 0;
hdlc->cbin = 0xff;
hdlc->data_bits = 8;
if (hdlc->bit_shift == 8) {
hdlc->cbin = 0x7e;
hdlc->state = HDLC_SEND_FIRST_FLAG;
} else {
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
*dst++ = bitrev8(hdlc->cbin);
else
*dst++ = hdlc->cbin;
hdlc->bit_shift = 0;
hdlc->data_bits = 0;
len++;
dsize = 0;
}
break;
default:
break;
}
if (hdlc->do_adapt56) {
if (hdlc->data_bits == 7) {
hdlc->cbin <<= 1;
hdlc->cbin++;
hdlc->data_bits++;
}
}
if (hdlc->data_bits == 8) {
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
*dst++ = bitrev8(hdlc->cbin);
else
*dst++ = hdlc->cbin;
hdlc->data_bits = 0;
len++;
dsize--;
}
}
*count -= slen;
return len;
}
EXPORT_SYMBOL(isdnhdlc_encode);

69
drivers/isdn/hardware/mISDN/isdnhdlc.h
View File

@ -1,69 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* hdlc.h -- General purpose ISDN HDLC decoder.
*
* Implementation of a HDLC decoder/encoder in software.
* Necessary because some ISDN devices don't have HDLC
* controllers.
*
* Copyright (C)
* 2009 Karsten Keil <keil@b1-systems.de>
* 2002 Wolfgang Mües <wolfgang@iksw-muees.de>
* 2001 Frode Isaksen <fisaksen@bewan.com>
* 2001 Kai Germaschewski <kai.germaschewski@gmx.de>
*/
#ifndef __ISDNHDLC_H__
#define __ISDNHDLC_H__
struct isdnhdlc_vars {
int bit_shift;
int hdlc_bits1;
int data_bits;
int ffbit_shift; /* encoding only */
int state;
int dstpos;
u16 crc;
u8 cbin;
u8 shift_reg;
u8 ffvalue;
/* set if transferring data */
u32 data_received:1;
/* set if D channel (send idle instead of flags) */
u32 dchannel:1;
/* set if 56K adaptation */
u32 do_adapt56:1;
/* set if in closing phase (need to send CRC + flag) */
u32 do_closing:1;
/* set if data is bitreverse */
u32 do_bitreverse:1;
};
/* Feature Flags */
#define HDLC_56KBIT 0x01
#define HDLC_DCHANNEL 0x02
#define HDLC_BITREVERSE 0x04
/*
The return value from isdnhdlc_decode is
the frame length, 0 if no complete frame was decoded,
or a negative error number
*/
#define HDLC_FRAMING_ERROR 1
#define HDLC_CRC_ERROR 2
#define HDLC_LENGTH_ERROR 3
extern void isdnhdlc_rcv_init(struct isdnhdlc_vars *hdlc, u32 features);
extern int isdnhdlc_decode(struct isdnhdlc_vars *hdlc, const u8 *src,
int slen, int *count, u8 *dst, int dsize);
extern void isdnhdlc_out_init(struct isdnhdlc_vars *hdlc, u32 features);
extern int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const u8 *src,
u16 slen, int *count, u8 *dst, int dsize);
#endif /* __ISDNHDLC_H__ */

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