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dt-bindings for Google GS101 clock controllers for v6.9

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The Devicetree binding headers for Samsung Exynos and Google GS101 clock
 controllers, used by the Samsung clock controller drivers.
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Merge tag 'samsung-dt-bindings-clk-6.9-2' into next/clk

dt-bindings for Google GS101 clock controllers for v6.9

The Devicetree binding headers for Samsung Exynos and Google GS101 clock
controllers, used by the Samsung clock controller drivers.
This commit is contained in:
Krzysztof Kozlowski 2024-01-23 13:45:50 +01:00
commit 64e57b7db4
3 changed files with 106 additions and 2 deletions
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25
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
View File

@ -30,14 +30,15 @@ properties:
- google,gs101-cmu-top
- google,gs101-cmu-apm
- google,gs101-cmu-misc
- google,gs101-cmu-peric0
clocks:
minItems: 1
maxItems: 2
maxItems: 3
clock-names:
minItems: 1
maxItems: 2
maxItems: 3
"#clock-cells":
const: 1
@ -88,6 +89,26 @@ allOf:
- const: bus
- const: sss
- if:
properties:
compatible:
contains:
const: google,gs101-cmu-peric0
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
- description: Connectivity Peripheral 0 bus clock (from CMU_TOP)
- description: Connectivity Peripheral 0 IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: ip
additionalProperties: false
examples:

2
include/dt-bindings/clock/exynos850.h
View File

@ -320,6 +320,8 @@
#define CLK_GOUT_SSS_PCLK 12
#define CLK_GOUT_GPIO_CORE_PCLK 13
#define CLK_GOUT_SYSREG_CORE_PCLK 14
#define CLK_GOUT_PDMA_CORE_ACLK 15
#define CLK_GOUT_SPDMA_CORE_ACLK 16
/* CMU_DPU */
#define CLK_MOUT_DPU_USER 1

81
include/dt-bindings/clock/google,gs101.h
View File

@ -389,4 +389,85 @@
#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73
#define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_BUS_USER 1
#define CLK_MOUT_PERIC0_I3C_USER 2
#define CLK_MOUT_PERIC0_USI0_UART_USER 3
#define CLK_MOUT_PERIC0_USI14_USI_USER 4
#define CLK_MOUT_PERIC0_USI1_USI_USER 5
#define CLK_MOUT_PERIC0_USI2_USI_USER 6
#define CLK_MOUT_PERIC0_USI3_USI_USER 7
#define CLK_MOUT_PERIC0_USI4_USI_USER 8
#define CLK_MOUT_PERIC0_USI5_USI_USER 9
#define CLK_MOUT_PERIC0_USI6_USI_USER 10
#define CLK_MOUT_PERIC0_USI7_USI_USER 11
#define CLK_MOUT_PERIC0_USI8_USI_USER 12
#define CLK_DOUT_PERIC0_I3C 13
#define CLK_DOUT_PERIC0_USI0_UART 14
#define CLK_DOUT_PERIC0_USI14_USI 15
#define CLK_DOUT_PERIC0_USI1_USI 16
#define CLK_DOUT_PERIC0_USI2_USI 17
#define CLK_DOUT_PERIC0_USI3_USI 18
#define CLK_DOUT_PERIC0_USI4_USI 19
#define CLK_DOUT_PERIC0_USI5_USI 20
#define CLK_DOUT_PERIC0_USI6_USI 21
#define CLK_DOUT_PERIC0_USI7_USI 22
#define CLK_DOUT_PERIC0_USI8_USI 23
#define CLK_GOUT_PERIC0_IP 24
#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25
#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26
#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27
#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28
#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29
#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62
#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63
#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64
#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65
#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66
#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67
#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */