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arm64: dts: freescale: imx8mm-verdin: Split UART_2 pinctrl group

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Some carrier board reuse the UART_2 control signals as GPIO, split
the pinctrl RTS/CTS in separated nodes to maximize flexibility.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Francesco Dolcini 2026-04-09 11:58:48 +02:00 committed by Frank Li
parent ca6371cdd9
commit 6481943667
1 changed files with 12 additions and 4 deletions
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16
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
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@ -735,7 +735,7 @@ &uart2 {
/* Verdin UART_2 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_cts>, <&pinctrl_uart3_rts>;
uart-has-rtscts;
};
@ -1144,12 +1144,20 @@ pinctrl_uart2: uart2grp {
<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
};
pinctrl_uart3_cts: uart3ctsgrp {
fsl,pins =
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
};
pinctrl_uart3_rts: uart3rtsgrp {
fsl,pins =
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>; /* SODIMM 141 */
};
pinctrl_uart3: uart3grp {
fsl,pins =
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>; /* SODIMM 137 */
};
pinctrl_uart4: uart4grp {