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iio: adc: rzg2l_adc: Add support for Renesas RZ/G3S

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Add ADC support for the Renesas RZ/G3S SoC. The key features of this IP
include:
- 9 channels, with one dedicated to reading the temperature reported by the
  Thermal Sensor Unit (TSU)
- A different default ADCMP value, which is written to the ADM3 register.
- Different default sampling rates
- ADM3.ADSMP field is 8 bits wide
- ADINT.INTEN field is 11 bits wide

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20241206111337.726244-14-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Claudiu Beznea 2024-12-06 13:13:35 +02:00 committed by Jonathan Cameron
parent 4af77feab3
commit 645fb7c22f
1 changed files with 9 additions and 0 deletions
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9
drivers/iio/adc/rzg2l_adc.c
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@ -504,7 +504,16 @@ static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
.adivc = true
};
static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
.num_channels = 9,
.default_adcmp = 0x1d,
.default_adsmp = { 0x7f, 0xff },
.adsmp_mask = GENMASK(7, 0),
.adint_inten_mask = GENMASK(11, 0),
};
static const struct of_device_id rzg2l_adc_match[] = {
{ .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
{ .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
{ /* sentinel */ }
};