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ASoC: SOF: imx8: use common imx chip interface
The common interface for imx chips (defined in imx-common.c) contains the definitions for a lot of functions required by the SOF core. As such, the platform driver can just use the common definitions instead of duplicating code by re-defining aforementioned functions. Make the transition to the new common interface. This consists of: 1) Removing unneeded functions, which are already defined in the common interface. 2) Defining some chip-specific operations/structures required by the interface to work. 3) Dropping structure definitions that are no longer needed. 4) Adapting some existing functions to the new interface. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250207162246.3104-3-laurentiumihalcea111@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Laurentiu Mihalcea
Mark Brown
parent
651e0ed391
commit
645753d013
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright 2019 NXP
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// Copyright 2019-2025 NXP
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//
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// Author: Daniel Baluta <daniel.baluta@nxp.com>
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//
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@ -41,100 +41,28 @@
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#define MBOX_OFFSET 0x800000
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#define MBOX_SIZE 0x1000
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struct imx8_priv {
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struct device *dev;
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struct snd_sof_dev *sdev;
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/* DSP IPC handler */
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struct imx_dsp_ipc *dsp_ipc;
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struct platform_device *ipc_dev;
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/* System Controller IPC handler */
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struct imx_sc_ipc *sc_ipc;
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/* Power domain handling */
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int num_domains;
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struct device **pd_dev;
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struct device_link **link;
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struct clk_bulk_data *clks;
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int clk_num;
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};
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static int imx8_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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return MBOX_OFFSET;
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}
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static int imx8_get_window_offset(struct snd_sof_dev *sdev, u32 id)
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{
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return MBOX_OFFSET;
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}
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static void imx8_dsp_handle_reply(struct imx_dsp_ipc *ipc)
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{
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struct imx8_priv *priv = imx_dsp_get_data(ipc);
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unsigned long flags;
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spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
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snd_sof_ipc_process_reply(priv->sdev, 0);
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spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
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}
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static void imx8_dsp_handle_request(struct imx_dsp_ipc *ipc)
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{
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struct imx8_priv *priv = imx_dsp_get_data(ipc);
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u32 p; /* panic code */
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/* Read the message from the debug box. */
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sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
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/* Check to see if the message is a panic code (0x0dead***) */
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if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
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snd_sof_dsp_panic(priv->sdev, p, true);
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else
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snd_sof_ipc_msgs_rx(priv->sdev);
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}
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static struct imx_dsp_ops dsp_ops = {
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.handle_reply = imx8_dsp_handle_reply,
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.handle_request = imx8_dsp_handle_request,
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};
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static int imx8_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct imx8_priv *priv = sdev->pdata->hw_pdata;
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
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return 0;
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}
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/*
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* DSP control.
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*/
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static int imx8x_run(struct snd_sof_dev *sdev)
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{
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struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
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int ret;
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ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
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ret = imx_sc_misc_set_control(get_chip_pdata(sdev), IMX_SC_R_DSP,
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IMX_SC_C_OFS_SEL, 1);
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if (ret < 0) {
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dev_err(sdev->dev, "Error system address offset source select\n");
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return ret;
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}
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ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
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ret = imx_sc_misc_set_control(get_chip_pdata(sdev), IMX_SC_R_DSP,
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IMX_SC_C_OFS_AUDIO, 0x80);
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if (ret < 0) {
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dev_err(sdev->dev, "Error system address offset of AUDIO\n");
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return ret;
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}
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ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
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ret = imx_sc_misc_set_control(get_chip_pdata(sdev), IMX_SC_R_DSP,
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IMX_SC_C_OFS_PERIPH, 0x5A);
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if (ret < 0) {
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dev_err(sdev->dev, "Error system address offset of PERIPH %d\n",
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@ -142,14 +70,14 @@ static int imx8x_run(struct snd_sof_dev *sdev)
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return ret;
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}
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ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
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ret = imx_sc_misc_set_control(get_chip_pdata(sdev), IMX_SC_R_DSP,
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IMX_SC_C_OFS_IRQ, 0x51);
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if (ret < 0) {
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dev_err(sdev->dev, "Error system address offset of IRQ\n");
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return ret;
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}
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imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
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imx_sc_pm_cpu_start(get_chip_pdata(sdev), IMX_SC_R_DSP, true,
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RESET_VECTOR_VADDR);
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return 0;
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@ -157,17 +85,16 @@ static int imx8x_run(struct snd_sof_dev *sdev)
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static int imx8_run(struct snd_sof_dev *sdev)
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{
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struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
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int ret;
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ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
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ret = imx_sc_misc_set_control(get_chip_pdata(sdev), IMX_SC_R_DSP,
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IMX_SC_C_OFS_SEL, 0);
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if (ret < 0) {
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dev_err(sdev->dev, "Error system address offset source select\n");
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return ret;
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}
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imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
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imx_sc_pm_cpu_start(get_chip_pdata(sdev), IMX_SC_R_DSP, true,
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RESET_VECTOR_VADDR);
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return 0;
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@ -175,272 +102,20 @@ static int imx8_run(struct snd_sof_dev *sdev)
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static int imx8_probe(struct snd_sof_dev *sdev)
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{
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struct platform_device *pdev = to_platform_device(sdev->dev);
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struct device_node *np = pdev->dev.of_node;
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struct device_node *res_node;
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struct resource *mmio;
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struct imx8_priv *priv;
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struct resource res;
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u32 base, size;
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int ret = 0;
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int i;
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struct imx_sc_ipc *sc_ipc_handle;
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struct imx_common_data *common;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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common = sdev->pdata->hw_pdata;
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sdev->num_cores = 1;
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sdev->pdata->hw_pdata = priv;
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priv->dev = sdev->dev;
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priv->sdev = sdev;
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ret = imx_scu_get_handle(&sc_ipc_handle);
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if (ret < 0)
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return dev_err_probe(sdev->dev, ret,
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"failed to fetch SC IPC handle\n");
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/* power up device associated power domains */
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priv->num_domains = of_count_phandle_with_args(np, "power-domains",
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"#power-domain-cells");
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if (priv->num_domains < 0) {
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dev_err(sdev->dev, "no power-domains property in %pOF\n", np);
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return priv->num_domains;
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}
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priv->pd_dev = devm_kmalloc_array(&pdev->dev, priv->num_domains,
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sizeof(*priv->pd_dev), GFP_KERNEL);
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if (!priv->pd_dev)
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return -ENOMEM;
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priv->link = devm_kmalloc_array(&pdev->dev, priv->num_domains,
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sizeof(*priv->link), GFP_KERNEL);
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if (!priv->link)
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return -ENOMEM;
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for (i = 0; i < priv->num_domains; i++) {
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priv->pd_dev[i] = dev_pm_domain_attach_by_id(&pdev->dev, i);
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if (IS_ERR(priv->pd_dev[i])) {
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ret = PTR_ERR(priv->pd_dev[i]);
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goto exit_unroll_pm;
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}
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priv->link[i] = device_link_add(&pdev->dev, priv->pd_dev[i],
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DL_FLAG_STATELESS |
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DL_FLAG_PM_RUNTIME |
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DL_FLAG_RPM_ACTIVE);
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if (!priv->link[i]) {
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ret = -ENOMEM;
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dev_pm_domain_detach(priv->pd_dev[i], false);
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goto exit_unroll_pm;
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}
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}
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ret = imx_scu_get_handle(&priv->sc_ipc);
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if (ret) {
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dev_err(sdev->dev, "Cannot obtain SCU handle (err = %d)\n",
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ret);
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goto exit_unroll_pm;
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}
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priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
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PLATFORM_DEVID_NONE,
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pdev, sizeof(*pdev));
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if (IS_ERR(priv->ipc_dev)) {
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ret = PTR_ERR(priv->ipc_dev);
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goto exit_unroll_pm;
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}
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priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
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if (!priv->dsp_ipc) {
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/* DSP IPC driver not probed yet, try later */
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ret = -EPROBE_DEFER;
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dev_err(sdev->dev, "Failed to get drvdata\n");
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goto exit_pdev_unregister;
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}
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imx_dsp_set_data(priv->dsp_ipc, priv);
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priv->dsp_ipc->ops = &dsp_ops;
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/* DSP base */
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mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (mmio) {
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base = mmio->start;
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size = resource_size(mmio);
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} else {
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dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
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ret = -EINVAL;
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goto exit_pdev_unregister;
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}
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sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
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if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
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dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
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base, size);
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ret = -ENODEV;
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goto exit_pdev_unregister;
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}
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sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
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res_node = of_parse_phandle(np, "memory-region", 0);
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if (!res_node) {
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dev_err(&pdev->dev, "failed to get memory region node\n");
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ret = -ENODEV;
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goto exit_pdev_unregister;
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}
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ret = of_address_to_resource(res_node, 0, &res);
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of_node_put(res_node);
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if (ret) {
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dev_err(&pdev->dev, "failed to get reserved region address\n");
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goto exit_pdev_unregister;
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}
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sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
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resource_size(&res));
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if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
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dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
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base, size);
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ret = -ENOMEM;
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goto exit_pdev_unregister;
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}
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sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
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/* set default mailbox offset for FW ready message */
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sdev->dsp_box.offset = MBOX_OFFSET;
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ret = devm_clk_bulk_get_all(sdev->dev, &priv->clks);
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if (ret < 0) {
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dev_err(sdev->dev, "failed to fetch clocks: %d\n", ret);
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goto exit_pdev_unregister;
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}
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priv->clk_num = ret;
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ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);
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if (ret < 0) {
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dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
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goto exit_pdev_unregister;
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}
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common->chip_pdata = sc_ipc_handle;
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return 0;
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exit_pdev_unregister:
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platform_device_unregister(priv->ipc_dev);
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exit_unroll_pm:
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while (--i >= 0) {
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device_link_del(priv->link[i]);
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dev_pm_domain_detach(priv->pd_dev[i], false);
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}
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return ret;
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}
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static void imx8_remove(struct snd_sof_dev *sdev)
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{
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struct imx8_priv *priv = sdev->pdata->hw_pdata;
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int i;
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clk_bulk_disable_unprepare(priv->clk_num, priv->clks);
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platform_device_unregister(priv->ipc_dev);
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for (i = 0; i < priv->num_domains; i++) {
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device_link_del(priv->link[i]);
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dev_pm_domain_detach(priv->pd_dev[i], false);
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}
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}
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/* on i.MX8 there is 1 to 1 match between type and BAR idx */
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static int imx8_get_bar_index(struct snd_sof_dev *sdev, u32 type)
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{
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/* Only IRAM and SRAM bars are valid */
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switch (type) {
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case SOF_FW_BLK_TYPE_IRAM:
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case SOF_FW_BLK_TYPE_SRAM:
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return type;
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default:
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return -EINVAL;
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}
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}
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static void imx8_suspend(struct snd_sof_dev *sdev)
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{
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int i;
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struct imx8_priv *priv = (struct imx8_priv *)sdev->pdata->hw_pdata;
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for (i = 0; i < DSP_MU_CHAN_NUM; i++)
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imx_dsp_free_channel(priv->dsp_ipc, i);
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clk_bulk_disable_unprepare(priv->clk_num, priv->clks);
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}
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static int imx8_resume(struct snd_sof_dev *sdev)
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{
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struct imx8_priv *priv = (struct imx8_priv *)sdev->pdata->hw_pdata;
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int ret;
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int i;
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ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);
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if (ret < 0) {
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dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
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return ret;
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}
|
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|
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for (i = 0; i < DSP_MU_CHAN_NUM; i++)
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imx_dsp_request_channel(priv->dsp_ipc, i);
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|
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return 0;
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}
|
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|
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static int imx8_dsp_runtime_resume(struct snd_sof_dev *sdev)
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{
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int ret;
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const struct sof_dsp_power_state target_dsp_state = {
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.state = SOF_DSP_PM_D0,
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};
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ret = imx8_resume(sdev);
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if (ret < 0)
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return ret;
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|
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return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
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}
|
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|
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static int imx8_dsp_runtime_suspend(struct snd_sof_dev *sdev)
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{
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const struct sof_dsp_power_state target_dsp_state = {
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.state = SOF_DSP_PM_D3,
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};
|
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|
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imx8_suspend(sdev);
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|
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return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
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}
|
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|
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static int imx8_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
|
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{
|
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const struct sof_dsp_power_state target_dsp_state = {
|
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.state = target_state,
|
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};
|
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|
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if (!pm_runtime_suspended(sdev->dev))
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imx8_suspend(sdev);
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|
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return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
|
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}
|
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|
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static int imx8_dsp_resume(struct snd_sof_dev *sdev)
|
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{
|
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int ret;
|
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const struct sof_dsp_power_state target_dsp_state = {
|
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.state = SOF_DSP_PM_D0,
|
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};
|
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|
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ret = imx8_resume(sdev);
|
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if (ret < 0)
|
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return ret;
|
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|
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if (pm_runtime_suspended(sdev->dev)) {
|
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pm_runtime_disable(sdev->dev);
|
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pm_runtime_set_active(sdev->dev);
|
||||
pm_runtime_mark_last_busy(sdev->dev);
|
||||
pm_runtime_enable(sdev->dev);
|
||||
pm_runtime_idle(sdev->dev);
|
||||
}
|
||||
|
||||
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
|
||||
}
|
||||
|
||||
static struct snd_soc_dai_driver imx8_dai[] = {
|
||||
|
|
@ -468,135 +143,64 @@ static struct snd_soc_dai_driver imx8_dai[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static int imx8_dsp_set_power_state(struct snd_sof_dev *sdev,
|
||||
const struct sof_dsp_power_state *target_state)
|
||||
static struct snd_sof_dsp_ops sof_imx8_ops;
|
||||
|
||||
static int imx8_ops_init(struct snd_sof_dev *sdev)
|
||||
{
|
||||
sdev->dsp_power_state = *target_state;
|
||||
/* first copy from template */
|
||||
memcpy(&sof_imx8_ops, &sof_imx_ops, sizeof(sof_imx_ops));
|
||||
|
||||
/* then set common imx8 ops */
|
||||
sof_imx8_ops.dbg_dump = imx8_dump;
|
||||
sof_imx8_ops.dsp_arch_ops = &sof_xtensa_arch_ops;
|
||||
sof_imx8_ops.debugfs_add_region_item =
|
||||
snd_sof_debugfs_add_region_item_iomem;
|
||||
|
||||
/* ... and finally set DAI driver */
|
||||
sof_imx8_ops.drv = get_chip_info(sdev)->drv;
|
||||
sof_imx8_ops.num_drv = get_chip_info(sdev)->num_drv;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* i.MX8 ops */
|
||||
static const struct snd_sof_dsp_ops sof_imx8_ops = {
|
||||
/* probe and remove */
|
||||
.probe = imx8_probe,
|
||||
.remove = imx8_remove,
|
||||
/* DSP core boot */
|
||||
.run = imx8_run,
|
||||
|
||||
/* Block IO */
|
||||
.block_read = sof_block_read,
|
||||
.block_write = sof_block_write,
|
||||
|
||||
/* Mailbox IO */
|
||||
.mailbox_read = sof_mailbox_read,
|
||||
.mailbox_write = sof_mailbox_write,
|
||||
|
||||
/* ipc */
|
||||
.send_msg = imx8_send_msg,
|
||||
.get_mailbox_offset = imx8_get_mailbox_offset,
|
||||
.get_window_offset = imx8_get_window_offset,
|
||||
|
||||
.ipc_msg_data = sof_ipc_msg_data,
|
||||
.set_stream_data_offset = sof_set_stream_data_offset,
|
||||
|
||||
.get_bar_index = imx8_get_bar_index,
|
||||
|
||||
/* firmware loading */
|
||||
.load_firmware = snd_sof_load_firmware_memcpy,
|
||||
|
||||
/* Debug information */
|
||||
.dbg_dump = imx8_dump,
|
||||
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
|
||||
|
||||
/* stream callbacks */
|
||||
.pcm_open = sof_stream_pcm_open,
|
||||
.pcm_close = sof_stream_pcm_close,
|
||||
|
||||
/* Firmware ops */
|
||||
.dsp_arch_ops = &sof_xtensa_arch_ops,
|
||||
|
||||
/* DAI drivers */
|
||||
.drv = imx8_dai,
|
||||
.num_drv = ARRAY_SIZE(imx8_dai),
|
||||
|
||||
/* ALSA HW info flags */
|
||||
.hw_info = SNDRV_PCM_INFO_MMAP |
|
||||
SNDRV_PCM_INFO_MMAP_VALID |
|
||||
SNDRV_PCM_INFO_INTERLEAVED |
|
||||
SNDRV_PCM_INFO_PAUSE |
|
||||
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
|
||||
|
||||
/* PM */
|
||||
.runtime_suspend = imx8_dsp_runtime_suspend,
|
||||
.runtime_resume = imx8_dsp_runtime_resume,
|
||||
|
||||
.suspend = imx8_dsp_suspend,
|
||||
.resume = imx8_dsp_resume,
|
||||
|
||||
.set_power_state = imx8_dsp_set_power_state,
|
||||
static const struct imx_chip_ops imx8_chip_ops = {
|
||||
.probe = imx8_probe,
|
||||
.core_kick = imx8_run,
|
||||
};
|
||||
|
||||
/* i.MX8X ops */
|
||||
static const struct snd_sof_dsp_ops sof_imx8x_ops = {
|
||||
/* probe and remove */
|
||||
.probe = imx8_probe,
|
||||
.remove = imx8_remove,
|
||||
/* DSP core boot */
|
||||
.run = imx8x_run,
|
||||
static const struct imx_chip_ops imx8x_chip_ops = {
|
||||
.probe = imx8_probe,
|
||||
.core_kick = imx8x_run,
|
||||
};
|
||||
|
||||
/* Block IO */
|
||||
.block_read = sof_block_read,
|
||||
.block_write = sof_block_write,
|
||||
static struct imx_memory_info imx8_memory_regions[] = {
|
||||
{ .name = "iram", .reserved = false },
|
||||
{ .name = "sram", .reserved = true },
|
||||
{ }
|
||||
};
|
||||
|
||||
/* Mailbox IO */
|
||||
.mailbox_read = sof_mailbox_read,
|
||||
.mailbox_write = sof_mailbox_write,
|
||||
|
||||
/* ipc */
|
||||
.send_msg = imx8_send_msg,
|
||||
.get_mailbox_offset = imx8_get_mailbox_offset,
|
||||
.get_window_offset = imx8_get_window_offset,
|
||||
|
||||
.ipc_msg_data = sof_ipc_msg_data,
|
||||
.set_stream_data_offset = sof_set_stream_data_offset,
|
||||
|
||||
.get_bar_index = imx8_get_bar_index,
|
||||
|
||||
/* firmware loading */
|
||||
.load_firmware = snd_sof_load_firmware_memcpy,
|
||||
|
||||
/* Debug information */
|
||||
.dbg_dump = imx8_dump,
|
||||
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
|
||||
|
||||
/* stream callbacks */
|
||||
.pcm_open = sof_stream_pcm_open,
|
||||
.pcm_close = sof_stream_pcm_close,
|
||||
|
||||
/* Firmware ops */
|
||||
.dsp_arch_ops = &sof_xtensa_arch_ops,
|
||||
|
||||
/* DAI drivers */
|
||||
static const struct imx_chip_info imx8_chip_info = {
|
||||
.ipc_info = {
|
||||
.has_panic_code = true,
|
||||
.boot_mbox_offset = 0x800000,
|
||||
.window_offset = 0x800000,
|
||||
},
|
||||
.memory = imx8_memory_regions,
|
||||
.drv = imx8_dai,
|
||||
.num_drv = ARRAY_SIZE(imx8_dai),
|
||||
.ops = &imx8_chip_ops,
|
||||
};
|
||||
|
||||
/* PM */
|
||||
.runtime_suspend = imx8_dsp_runtime_suspend,
|
||||
.runtime_resume = imx8_dsp_runtime_resume,
|
||||
|
||||
.suspend = imx8_dsp_suspend,
|
||||
.resume = imx8_dsp_resume,
|
||||
|
||||
.set_power_state = imx8_dsp_set_power_state,
|
||||
|
||||
/* ALSA HW info flags */
|
||||
.hw_info = SNDRV_PCM_INFO_MMAP |
|
||||
SNDRV_PCM_INFO_MMAP_VALID |
|
||||
SNDRV_PCM_INFO_INTERLEAVED |
|
||||
SNDRV_PCM_INFO_PAUSE |
|
||||
SNDRV_PCM_INFO_BATCH |
|
||||
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP
|
||||
static const struct imx_chip_info imx8x_chip_info = {
|
||||
.ipc_info = {
|
||||
.has_panic_code = true,
|
||||
.boot_mbox_offset = 0x800000,
|
||||
.window_offset = 0x800000,
|
||||
},
|
||||
.memory = imx8_memory_regions,
|
||||
.drv = imx8_dai,
|
||||
.num_drv = ARRAY_SIZE(imx8_dai),
|
||||
.ops = &imx8x_chip_ops,
|
||||
};
|
||||
|
||||
static struct snd_sof_of_mach sof_imx8_machs[] = {
|
||||
|
|
@ -636,6 +240,7 @@ static struct snd_sof_of_mach sof_imx8_machs[] = {
|
|||
|
||||
static struct sof_dev_desc sof_of_imx8qxp_desc = {
|
||||
.of_machines = sof_imx8_machs,
|
||||
.chip_info = &imx8x_chip_info,
|
||||
.ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
|
||||
.ipc_default = SOF_IPC_TYPE_3,
|
||||
.default_fw_path = {
|
||||
|
|
@ -648,11 +253,13 @@ static struct sof_dev_desc sof_of_imx8qxp_desc = {
|
|||
[SOF_IPC_TYPE_3] = "sof-imx8x.ri",
|
||||
},
|
||||
.nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
|
||||
.ops = &sof_imx8x_ops,
|
||||
.ops = &sof_imx8_ops,
|
||||
.ops_init = imx8_ops_init,
|
||||
};
|
||||
|
||||
static struct sof_dev_desc sof_of_imx8qm_desc = {
|
||||
.of_machines = sof_imx8_machs,
|
||||
.chip_info = &imx8_chip_info,
|
||||
.ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
|
||||
.ipc_default = SOF_IPC_TYPE_3,
|
||||
.default_fw_path = {
|
||||
|
|
@ -666,6 +273,7 @@ static struct sof_dev_desc sof_of_imx8qm_desc = {
|
|||
},
|
||||
.nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
|
||||
.ops = &sof_imx8_ops,
|
||||
.ops_init = imx8_ops_init,
|
||||
};
|
||||
|
||||
static const struct of_device_id sof_of_imx8_ids[] = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user