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arm64: dts: qcom: msm8998: Use the correct GPLL0_DIV leg for MMCC

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MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output.
We've already been using the correct one in the non-div case, start
doing so for the other one as well.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-8-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio 2023-07-03 20:20:12 +02:00 committed by Bjorn Andersson
parent 00ada6afea
commit 63f4e4b447
1 changed files with 4 additions and 2 deletions
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6
arch/arm64/boot/dts/qcom/msm8998.dtsi
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@ -2724,7 +2724,8 @@ mmcc: clock-controller@c8c0000 {
"dsi1byte",
"hdmipll",
"dplink",
"dpvco";
"dpvco",
"gpll0_div";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_MMSS_GPLL0_CLK>,
<0>,
@ -2733,7 +2734,8 @@ mmcc: clock-controller@c8c0000 {
<0>,
<0>,
<0>,
<0>;
<0>,
<&gcc GCC_MMSS_GPLL0_DIV_CLK>;
};
mmss_smmu: iommu@cd00000 {